1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 HasMExtension: Boolean = true, 47 HasCExtension: Boolean = true, 48 HasDiv: Boolean = true, 49 HasICache: Boolean = true, 50 HasDCache: Boolean = true, 51 AddrBits: Int = 64, 52 VAddrBits: Int = 39, 53 HasFPU: Boolean = true, 54 HasCustomCSRCacheOp: Boolean = true, 55 FetchWidth: Int = 8, 56 AsidLength: Int = 16, 57 EnableBPU: Boolean = true, 58 EnableBPD: Boolean = true, 59 EnableRAS: Boolean = true, 60 EnableLB: Boolean = false, 61 EnableLoop: Boolean = true, 62 EnableSC: Boolean = true, 63 EnbaleTlbDebug: Boolean = false, 64 EnableJal: Boolean = false, 65 EnableFauFTB: Boolean = true, 66 UbtbGHRLength: Int = 4, 67 // HistoryLength: Int = 512, 68 EnableGHistDiff: Boolean = true, 69 UbtbSize: Int = 256, 70 FtbSize: Int = 2048, 71 RasSize: Int = 32, 72 CacheLineSize: Int = 512, 73 FtbWays: Int = 4, 74 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 75 // Sets Hist Tag 76 // Seq(( 2048, 2, 8), 77 // ( 2048, 9, 8), 78 // ( 2048, 13, 8), 79 // ( 2048, 20, 8), 80 // ( 2048, 26, 8), 81 // ( 2048, 44, 8), 82 // ( 2048, 73, 8), 83 // ( 2048, 256, 8)), 84 Seq(( 4096, 8, 8), 85 ( 4096, 13, 8), 86 ( 4096, 32, 8), 87 ( 4096, 119, 8)), 88 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 89 // Sets Hist Tag 90 Seq(( 256, 4, 9), 91 ( 256, 8, 9), 92 ( 512, 13, 9), 93 ( 512, 16, 9), 94 ( 512, 32, 9)), 95 SCNRows: Int = 512, 96 SCNTables: Int = 4, 97 SCCtrBits: Int = 6, 98 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 99 numBr: Int = 2, 100 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 101 ((resp_in: BranchPredictionResp, p: Parameters) => { 102 val ftb = Module(new FTB()(p)) 103 val ubtb =Module(new FauFTB()(p)) 104 // val bim = Module(new BIM()(p)) 105 val tage = Module(new Tage_SC()(p)) 106 val ras = Module(new RAS()(p)) 107 val ittage = Module(new ITTage()(p)) 108 val preds = Seq(ubtb, tage, ftb, ittage, ras) 109 preds.map(_.io := DontCare) 110 111 // ubtb.io.resp_in(0) := resp_in 112 // bim.io.resp_in(0) := ubtb.io.resp 113 // btb.io.resp_in(0) := bim.io.resp 114 // tage.io.resp_in(0) := btb.io.resp 115 // loop.io.resp_in(0) := tage.io.resp 116 ubtb.io.in.bits.resp_in(0) := resp_in 117 tage.io.in.bits.resp_in(0) := ubtb.io.out 118 ftb.io.in.bits.resp_in(0) := tage.io.out 119 ittage.io.in.bits.resp_in(0) := ftb.io.out 120 ras.io.in.bits.resp_in(0) := ittage.io.out 121 122 (preds, ras.io.out) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 LoadQueueSize: Int = 80, 133 LoadQueueNWriteBanks: Int = 8, 134 StoreQueueSize: Int = 64, 135 StoreQueueNWriteBanks: Int = 8, 136 VlsQueueSize: Int = 8, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 158 LoadPipelineWidth: Int = 2, 159 StorePipelineWidth: Int = 2, 160 VecMemSrcInWidth: Int = 2, 161 VecMemInstWbWidth: Int = 1, 162 VecMemDispatchWidth: Int = 1, 163 StoreBufferSize: Int = 16, 164 StoreBufferThreshold: Int = 7, 165 EnsbufferWidth: Int = 2, 166 UncacheBufferSize: Int = 4, 167 EnableLoadToLoadForward: Boolean = true, 168 EnableFastForward: Boolean = false, 169 EnableLdVioCheckAfterReset: Boolean = true, 170 EnableSoftPrefetchAfterReset: Boolean = true, 171 EnableCacheErrorAfterReset: Boolean = true, 172 EnableDCacheWPU: Boolean = false, 173 EnableAccurateLoadError: Boolean = true, 174 EnableUncacheWriteOutstanding: Boolean = false, 175 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 176 ReSelectLen: Int = 7, // load replay queue replay select counter len 177 itlbParameters: TLBParameters = TLBParameters( 178 name = "itlb", 179 fetchi = true, 180 useDmode = false, 181 normalNWays = 32, 182 normalReplacer = Some("plru"), 183 superNWays = 4, 184 superReplacer = Some("plru") 185 ), 186 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 187 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 188 ldtlbParameters: TLBParameters = TLBParameters( 189 name = "ldtlb", 190 normalNSets = 64, 191 normalNWays = 1, 192 normalAssociative = "sa", 193 normalReplacer = Some("setplru"), 194 superNWays = 16, 195 normalAsVictim = true, 196 outReplace = false, 197 partialStaticPMP = true, 198 outsideRecvFlush = true, 199 saveLevel = true 200 ), 201 sttlbParameters: TLBParameters = TLBParameters( 202 name = "sttlb", 203 normalNSets = 64, 204 normalNWays = 1, 205 normalAssociative = "sa", 206 normalReplacer = Some("setplru"), 207 superNWays = 16, 208 normalAsVictim = true, 209 outReplace = false, 210 partialStaticPMP = true, 211 outsideRecvFlush = true, 212 saveLevel = true 213 ), 214 pftlbParameters: TLBParameters = TLBParameters( 215 name = "pftlb", 216 normalNSets = 64, 217 normalNWays = 1, 218 normalAssociative = "sa", 219 normalReplacer = Some("setplru"), 220 superNWays = 16, 221 normalAsVictim = true, 222 outReplace = false, 223 partialStaticPMP = true, 224 outsideRecvFlush = true, 225 saveLevel = true 226 ), 227 refillBothTlb: Boolean = false, 228 btlbParameters: TLBParameters = TLBParameters( 229 name = "btlb", 230 normalNSets = 1, 231 normalNWays = 64, 232 superNWays = 4, 233 ), 234 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 235 NumPerfCounters: Int = 16, 236 icacheParameters: ICacheParameters = ICacheParameters( 237 tagECC = Some("parity"), 238 dataECC = Some("parity"), 239 replacer = Some("setplru"), 240 nMissEntries = 2, 241 nProbeEntries = 2, 242 nPrefetchEntries = 12, 243 nPrefBufferEntries = 64, 244 hasPrefetch = true, 245 ), 246 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 247 tagECC = Some("secded"), 248 dataECC = Some("secded"), 249 replacer = Some("setplru"), 250 nMissEntries = 16, 251 nProbeEntries = 8, 252 nReleaseEntries = 18 253 )), 254 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 255 name = "l2", 256 level = 2, 257 ways = 8, 258 sets = 1024, // default 512KB L2 259 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 260 )), 261 L2NBanks: Int = 1, 262 usePTWRepeater: Boolean = false, 263 softTLB: Boolean = false, // dpi-c l1tlb debug only 264 softPTW: Boolean = false, // dpi-c l2tlb debug only 265 softPTWDelay: Int = 1 266){ 267 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 268 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 269 270 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 271 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 272 273 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 274 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 275 276 val fpExuConfigs = 277 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 278 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 279 280 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 281} 282 283case object DebugOptionsKey extends Field[DebugOptions] 284 285case class DebugOptions 286( 287 FPGAPlatform: Boolean = false, 288 EnableDifftest: Boolean = false, 289 AlwaysBasicDiff: Boolean = true, 290 EnableDebug: Boolean = false, 291 EnablePerfDebug: Boolean = true, 292 UseDRAMSim: Boolean = false, 293 EnableTopDown: Boolean = false 294) 295 296trait HasXSParameter { 297 298 implicit val p: Parameters 299 300 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 301 302 val coreParams = p(XSCoreParamsKey) 303 val env = p(DebugOptionsKey) 304 305 val XLEN = coreParams.XLEN 306 val minFLen = 32 307 val fLen = 64 308 def xLen = XLEN 309 310 val HasMExtension = coreParams.HasMExtension 311 val HasCExtension = coreParams.HasCExtension 312 val HasDiv = coreParams.HasDiv 313 val HasIcache = coreParams.HasICache 314 val HasDcache = coreParams.HasDCache 315 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 316 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 317 val AsidLength = coreParams.AsidLength 318 val ReSelectLen = coreParams.ReSelectLen 319 val AddrBytes = AddrBits / 8 // unused 320 val DataBits = XLEN 321 val DataBytes = DataBits / 8 322 val HasFPU = coreParams.HasFPU 323 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 324 val FetchWidth = coreParams.FetchWidth 325 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 326 val EnableBPU = coreParams.EnableBPU 327 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 328 val EnableRAS = coreParams.EnableRAS 329 val EnableLB = coreParams.EnableLB 330 val EnableLoop = coreParams.EnableLoop 331 val EnableSC = coreParams.EnableSC 332 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 333 val HistoryLength = coreParams.HistoryLength 334 val EnableGHistDiff = coreParams.EnableGHistDiff 335 val UbtbGHRLength = coreParams.UbtbGHRLength 336 val UbtbSize = coreParams.UbtbSize 337 val EnableFauFTB = coreParams.EnableFauFTB 338 val FtbSize = coreParams.FtbSize 339 val FtbWays = coreParams.FtbWays 340 val RasSize = coreParams.RasSize 341 342 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 343 coreParams.branchPredictor(resp_in, p) 344 } 345 val numBr = coreParams.numBr 346 val TageTableInfos = coreParams.TageTableInfos 347 val TageBanks = coreParams.numBr 348 val SCNRows = coreParams.SCNRows 349 val SCCtrBits = coreParams.SCCtrBits 350 val SCHistLens = coreParams.SCHistLens 351 val SCNTables = coreParams.SCNTables 352 353 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 354 case ((n, cb), h) => (n, cb, h) 355 } 356 val ITTageTableInfos = coreParams.ITTageTableInfos 357 type FoldedHistoryInfo = Tuple2[Int, Int] 358 val foldedGHistInfos = 359 (TageTableInfos.map{ case (nRows, h, t) => 360 if (h > 0) 361 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 362 else 363 Set[FoldedHistoryInfo]() 364 }.reduce(_++_).toSet ++ 365 SCTableInfos.map{ case (nRows, _, h) => 366 if (h > 0) 367 Set((h, min(log2Ceil(nRows/TageBanks), h))) 368 else 369 Set[FoldedHistoryInfo]() 370 }.reduce(_++_).toSet ++ 371 ITTageTableInfos.map{ case (nRows, h, t) => 372 if (h > 0) 373 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 374 else 375 Set[FoldedHistoryInfo]() 376 }.reduce(_++_) ++ 377 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 378 ).toList 379 380 381 382 val CacheLineSize = coreParams.CacheLineSize 383 val CacheLineHalfWord = CacheLineSize / 16 384 val ExtHistoryLength = HistoryLength + 64 385 val IBufSize = coreParams.IBufSize 386 val DecodeWidth = coreParams.DecodeWidth 387 val RenameWidth = coreParams.RenameWidth 388 val CommitWidth = coreParams.CommitWidth 389 val FtqSize = coreParams.FtqSize 390 val IssQueSize = coreParams.IssQueSize 391 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 392 val NRPhyRegs = coreParams.NRPhyRegs 393 val PhyRegIdxWidth = log2Up(NRPhyRegs) 394 val RobSize = coreParams.RobSize 395 val IntRefCounterWidth = log2Ceil(RobSize) 396 val LoadQueueSize = coreParams.LoadQueueSize 397 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 398 val StoreQueueSize = coreParams.StoreQueueSize 399 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 400 val VlsQueueSize = coreParams.VlsQueueSize 401 val dpParams = coreParams.dpParams 402 val exuParameters = coreParams.exuParameters 403 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 404 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 405 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 406 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 407 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 408 val LoadPipelineWidth = coreParams.LoadPipelineWidth 409 val StorePipelineWidth = coreParams.StorePipelineWidth 410 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 411 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 412 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 413 val StoreBufferSize = coreParams.StoreBufferSize 414 val StoreBufferThreshold = coreParams.StoreBufferThreshold 415 val EnsbufferWidth = coreParams.EnsbufferWidth 416 val UncacheBufferSize = coreParams.UncacheBufferSize 417 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 418 val EnableFastForward = coreParams.EnableFastForward 419 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 420 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 421 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 422 val EnableDCacheWPU = coreParams.EnableDCacheWPU 423 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 424 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 425 val asidLen = coreParams.MMUAsidLen 426 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 427 val refillBothTlb = coreParams.refillBothTlb 428 val itlbParams = coreParams.itlbParameters 429 val ldtlbParams = coreParams.ldtlbParameters 430 val sttlbParams = coreParams.sttlbParameters 431 val pftlbParams = coreParams.pftlbParameters 432 val btlbParams = coreParams.btlbParameters 433 val l2tlbParams = coreParams.l2tlbParameters 434 val NumPerfCounters = coreParams.NumPerfCounters 435 436 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 437 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 438 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 439 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 440 441 val instBytes = if (HasCExtension) 2 else 4 442 val instOffsetBits = log2Ceil(instBytes) 443 444 val icacheParameters = coreParams.icacheParameters 445 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 446 447 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 448 // for constrained LR/SC loop 449 val LRSCCycles = 64 450 // for lr storm 451 val LRSCBackOff = 8 452 453 // cache hierarchy configurations 454 val l1BusDataWidth = 256 455 456 // load violation predict 457 val ResetTimeMax2Pow = 20 //1078576 458 val ResetTimeMin2Pow = 10 //1024 459 // wait table parameters 460 val WaitTableSize = 1024 461 val MemPredPCWidth = log2Up(WaitTableSize) 462 val LWTUse2BitCounter = true 463 // store set parameters 464 val SSITSize = WaitTableSize 465 val LFSTSize = 32 466 val SSIDWidth = log2Up(LFSTSize) 467 val LFSTWidth = 4 468 val StoreSetEnable = true // LWT will be disabled if SS is enabled 469 470 val loadExuConfigs = coreParams.loadExuConfigs 471 val storeExuConfigs = coreParams.storeExuConfigs 472 473 val intExuConfigs = coreParams.intExuConfigs 474 475 val fpExuConfigs = coreParams.fpExuConfigs 476 477 val exuConfigs = coreParams.exuConfigs 478 479 val PCntIncrStep: Int = 6 480 val numPCntHc: Int = 25 481 val numPCntPtw: Int = 19 482 483 val numCSRPCntFrontend = 8 484 val numCSRPCntCtrl = 8 485 val numCSRPCntLsu = 8 486 val numCSRPCntHc = 5 487} 488