issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
73fee459	31-Jul-2020	LinJiawei <[email protected]>	IssueQueue: fix enq and deq bug IssueQueue.scala
25f2248c	31-Jul-2020	Yinan Xu <[email protected]>	ls issue queue: temporarily set numExist to 0 to avoid stuck /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala
fb019544	31-Jul-2020	LinJiawei <[email protected]>	Backend: add tlbFeedback /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala
4643465d	31-Jul-2020	LinJiawei <[email protected]>	IssueQueue: Optimize log IssueQueue.scala
614b970f	31-Jul-2020	LinJiawei <[email protected]>	IssueQueue: fix uop read bug IssueQueue.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala
1ca5ef0f	31-Jul-2020	linjiawei <[email protected]>	IssueQueue: add log /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala
6b8d1ed8	30-Jul-2020	LinJiawei <[email protected]>	Merge branch 'temp-lsu-test' of https://github.com/RISCVERS/XiangShan into temp-lsu-test /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala ReservationStation.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.h
59e12078	30-Jul-2020	LinJiawei <[email protected]>	IssueQueue: support bypass /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala IssueQueue.scala
74fe9f47	30-Jul-2020	LinJiawei <[email protected]>	IssueQueue: Support regfile read IssueQueue.scala
054d37b6	29-Jul-2020	LinJiawei <[email protected]>	IssueQueue: support enq and deq /XiangShan/src/main/scala/xiangshan/Bundle.scala IssueQueue.scala ReservationStation.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala
bb411583	29-Jul-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/temp-lsu-test' into dev-new-dispatch /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
5712beea	29-Jul-2020	LinJiawei <[email protected]>	IssueQueue: update issue queue io, add 'tlbHit' /XiangShan/src/main/scala/xiangshan/backend/Backend.scala ReservationStation.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala
5a84dde5	29-Jul-2020	LinJiawei <[email protected]>	mem: add replay /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala ReservationStation.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala
6e962ad0	29-Jul-2020	LinJiawei <[email protected]>	Merge refactor-redirect into temp-lsu-test /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
250b716d	29-Jul-2020	Yinan Xu <[email protected]>	dispatch2: refactor logic /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala ReservationStation.scala
b2e6921e	28-Jul-2020	LinJiawei <[email protected]>	Refactor redirect, cputest pass, microbench fail /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sbt /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
5d4fa790	28-Jul-2020	LinJiawei <[email protected]>	Dispatch,IssueQueue: update regfile read logic /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala ReservationStation.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala
6624015f	27-Jul-2020	LinJiawei <[email protected]>	New arch to support out-of-order load/store /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/build.sbt /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/TLB.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala ReservedStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
c7054bab	16-Jul-2020	LinJiawei <[email protected]>	Freelist: use checkpoint to recovery /XiangShan/Makefile /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/test/scala/top/XSSim.scala
b9fd1892	14-Jul-2020	LinJiawei <[email protected]>	Remove xiangshan.utils /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZicsr.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala
0b791572	11-Jul-2020	ZhangZifei <[email protected]>	Merge branch 'master' into refactor-exu /XiangShan/src/main/scala/bus/simplebus/DistributedMem.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/test/scala/top/XSSim.scala
6d95fae2	11-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: all IQ recv bypass and only alu send bypass /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala
d591b145	11-Jul-2020	ZhangZifei <[email protected]>	IssueQueue: enable bypass of alu and fix bug of bypass /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala IssueQueue.scala
c7cacdf5	11-Jul-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/refactor-exu' into improve-dp2 /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVM.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
65c62b20	11-Jul-2020	LinJiawei <[email protected]>	Merge master into refactor-exu /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala IssueQueue.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala
1...<<21 22 23 24 25 26 272829 30 >>...32