1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import bus.simplebus._ 6import xiangshan.backend.brq.BrqPtr 7import xiangshan.backend.rename.FreeListPtr 8 9// Fetch FetchWidth x 32-bit insts from Icache 10class FetchPacket extends XSBundle { 11 val instrs = Vec(FetchWidth, UInt(32.W)) 12 val mask = UInt((FetchWidth*2).W) 13 val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group 14} 15 16// Dequeue DecodeWidth insts from Ibuffer 17class CtrlFlow extends XSBundle { 18 val instr = UInt(32.W) 19 val pc = UInt(VAddrBits.W) 20 val exceptionVec = Vec(16, Bool()) 21 val intrVec = Vec(12, Bool()) 22 val isRVC = Bool() 23 val isBr = Bool() 24 val crossPageIPFFix = Bool() 25} 26 27// Decode DecodeWidth insts at Decode Stage 28class CtrlSignals extends XSBundle { 29 val src1Type, src2Type, src3Type = SrcType() 30 val lsrc1, lsrc2, lsrc3 = UInt(5.W) 31 val ldest = UInt(5.W) 32 val fuType = FuType() 33 val fuOpType = FuOpType() 34 val rfWen = Bool() 35 val fpWen = Bool() 36 val isXSTrap = Bool() 37 val noSpecExec = Bool() // This inst can not be speculated 38 val isBlocked = Bool() // This inst requires pipeline to be blocked 39 val isRVF = Bool() 40 val imm = UInt(XLEN.W) 41} 42 43class CfCtrl extends XSBundle { 44 val cf = new CtrlFlow 45 val ctrl = new CtrlSignals 46 val brTag = new BrqPtr 47} 48 49// CfCtrl -> MicroOp at Rename Stage 50class MicroOp extends CfCtrl { 51 52 val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W) 53 val src1State, src2State, src3State = SrcState() 54 val freelistAllocPtr = new FreeListPtr 55 val roqIdx = UInt(RoqIdxWidth.W) 56} 57 58class Redirect extends XSBundle { 59 val target = UInt(VAddrBits.W) 60 val brTag = new BrqPtr 61 val isException = Bool() 62 val roqIdx = UInt(RoqIdxWidth.W) 63 val freelistAllocPtr = new FreeListPtr 64} 65 66class RedirectInfo extends XSBundle { 67 68 val valid = Bool() // a valid commit form brq/roq 69 val misPred = Bool() // a branch miss prediction ? 70 val redirect = new Redirect 71 72 def flush():Bool = valid && (redirect.isException || misPred) 73} 74 75class Dp1ToDp2IO extends XSBundle { 76 val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)) 77 val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp)) 78 val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp)) 79} 80 81class DebugBundle extends XSBundle{ 82 val isMMIO = Bool() 83} 84 85class ExuInput extends XSBundle { 86 val uop = new MicroOp 87 val src1, src2, src3 = UInt(XLEN.W) 88} 89 90class ExuOutput extends XSBundle { 91 val uop = new MicroOp 92 val data = UInt(XLEN.W) 93 val redirectValid = Bool() 94 val redirect = new Redirect 95 val debug = new DebugBundle 96} 97 98class ExuIO extends XSBundle { 99 val in = Flipped(DecoupledIO(new ExuInput)) 100 val redirect = Flipped(ValidIO(new Redirect)) 101 val out = DecoupledIO(new ExuOutput) 102 103 // for Lsu 104 val dmem = new SimpleBusUC 105 val scommit = Input(UInt(3.W)) 106} 107 108class RoqCommit extends XSBundle { 109 val uop = new MicroOp 110 val isWalk = Bool() 111} 112 113class FrontendToBackendIO extends XSBundle { 114 // to backend end 115 val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow)) 116 // from backend 117 val redirectInfo = Input(new RedirectInfo) 118 val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred 119} 120