feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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chore(dispatch): remove useless code and files (#4288)

style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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area(EXU): add parameter `needCopySrc` in FuConfig (#4063)

fix(scheduler): fix bug of sta valid

timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDispatch

area(backend): only use startAddr in pcMem

area(backend): only pipe wakeupFromIQ and wakeupFromWB once

area(Backend): merge pcMem and pcTargetMem

feat(backend): NewDispatch

area(IssueQueue): encode exuOH as UInt to reduce storage (#4033)

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(Backend): add support for Zacas extension

misc: remove assert temporarily

chore: use scala-provided `distinctBy`

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different

fix(decode): not eliminate old vd when vstart is not zero (#3948)

* when vstart is not zero, it need to combine the old data in the range
of 0 to vstart, so we need old vd in this case
* different instructions may have same fuoptype, so we need to check
both futype and fuoptype to distinguish the instructions

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busytable: support eliminate old vd when read vl's state

area(MemBlock): remove redundant signals to optimize area (#3777)

fix(IssueQueue, BusyTable): refactor wakeup and cancel, and remove redundant logic

fix(Backend): add vecLoadFinalIssueResp

feat(fof): let fof vector load uop always need oldvd wakeup

feat(rv64v): support first only fault instruction

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)