1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15* 16* 17* Acknowledgement 18* 19* This implementation is inspired by several key papers: 20* [1] Robert. M. Tomasulo. "[An efficient algorithm for exploiting multiple arithmetic units.] 21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967. 22***************************************************************************************/ 23 24package xiangshan.backend 25 26import org.chipsalliance.cde.config.Parameters 27import chisel3._ 28import chisel3.util._ 29import device.MsiInfoBundle 30import difftest._ 31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 32import system.HasSoCParameter 33import utility._ 34import xiangshan._ 35import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 37import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 38import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 39import xiangshan.backend.datapath.WbConfig._ 40import xiangshan.backend.datapath.DataConfig._ 41import xiangshan.backend.datapath._ 42import xiangshan.backend.dispatch.CoreDispatchTopDownIO 43import xiangshan.backend.exu.ExuBlock 44import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 45import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 46import xiangshan.backend.issue.EntryBundles._ 47import xiangshan.backend.issue.{Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 48import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 49import xiangshan.backend.trace.TraceCoreInterface 50import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 51import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 52 53import scala.collection.mutable 54 55class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 56 with HasXSParameter { 57 override def shouldBeInlined: Boolean = false 58 val inner = LazyModule(new BackendInlined(params)) 59 lazy val module = new BackendImp(this) 60} 61 62class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 63 val io = IO(new BackendIO()(p, wrapper.params)) 64 io <> wrapper.inner.module.io 65 if (p(DebugOptionsKey).ResetGen) { 66 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 67 } 68} 69 70class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 71 with HasXSParameter { 72 73 override def shouldBeInlined: Boolean = true 74 75 // check read & write port config 76 params.configChecks 77 78 /* Only update the idx in mem-scheduler here 79 * Idx in other schedulers can be updated the same way if needed 80 * 81 * Also note that we filter out the 'stData issue-queues' when counting 82 */ 83 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 84 ibp.updateIdx(idx) 85 } 86 87 println(params.iqWakeUpParams) 88 89 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 90 schdCfg.bindBackendParam(params) 91 } 92 93 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 94 iqCfg.bindBackendParam(params) 95 } 96 97 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 98 exuCfg.bindBackendParam(params) 99 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 100 exuCfg.updateExuIdx(i) 101 } 102 103 println("[Backend] ExuConfigs:") 104 for (exuCfg <- params.allExuParams) { 105 val fuConfigs = exuCfg.fuConfigs 106 val wbPortConfigs = exuCfg.wbPortConfigs 107 val immType = exuCfg.immType 108 109 println("[Backend] " + 110 s"${exuCfg.name}: " + 111 (if (exuCfg.fakeUnit) "fake, " else "") + 112 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 113 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 114 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 115 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 116 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 117 s"srcReg(${exuCfg.numRegSrc})" 118 ) 119 require( 120 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 121 fuConfigs.map(_.writeIntRf).reduce(_ || _), 122 s"${exuCfg.name} int wb port has no priority" 123 ) 124 require( 125 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 126 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 127 s"${exuCfg.name} fp wb port has no priority" 128 ) 129 require( 130 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 131 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 132 s"${exuCfg.name} vec wb port has no priority" 133 ) 134 } 135 136 println(s"[Backend] all fu configs") 137 for (cfg <- FuConfig.allConfigs) { 138 println(s"[Backend] $cfg") 139 } 140 141 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 142 for ((port, seq) <- params.getRdPortParams(IntData())) { 143 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 144 } 145 146 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 147 for ((port, seq) <- params.getWbPortParams(IntData())) { 148 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 149 } 150 151 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 152 for ((port, seq) <- params.getRdPortParams(FpData())) { 153 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 154 } 155 156 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 157 for ((port, seq) <- params.getWbPortParams(FpData())) { 158 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 159 } 160 161 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 162 for ((port, seq) <- params.getRdPortParams(VecData())) { 163 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 164 } 165 166 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 167 for ((port, seq) <- params.getWbPortParams(VecData())) { 168 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 169 } 170 171 println(s"[Backend] Dispatch Configs:") 172 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 173 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 174 175 params.updateCopyPdestInfo 176 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 177 params.allExuParams.map(_.copyNum) 178 val ctrlBlock = LazyModule(new CtrlBlock(params)) 179 val pcTargetMem = LazyModule(new PcTargetMem(params)) 180 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 181 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 182 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 183 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 184 val dataPath = LazyModule(new DataPath(params)) 185 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 186 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 187 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 188 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 189 190 lazy val module = new BackendInlinedImp(this) 191} 192 193class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 194 with HasXSParameter 195 with HasPerfEvents 196 with HasCriticalErrors { 197 implicit private val params: BackendParams = wrapper.params 198 199 val io = IO(new BackendIO()(p, wrapper.params)) 200 201 private val ctrlBlock = wrapper.ctrlBlock.module 202 private val pcTargetMem = wrapper.pcTargetMem.module 203 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 204 private val fpScheduler = wrapper.fpScheduler.get.module 205 private val vfScheduler = wrapper.vfScheduler.get.module 206 private val memScheduler = wrapper.memScheduler.get.module 207 private val dataPath = wrapper.dataPath.module 208 private val intExuBlock = wrapper.intExuBlock.get.module 209 private val fpExuBlock = wrapper.fpExuBlock.get.module 210 private val vfExuBlock = wrapper.vfExuBlock.get.module 211 private val og2ForVector = Module(new Og2ForVector(params)) 212 private val bypassNetwork = Module(new BypassNetwork) 213 private val wbDataPath = Module(new WbDataPath(params)) 214 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 215 private val vecExcpMod = Module(new VecExcpDataMergeModule) 216 217 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 218 intScheduler.io.toSchedulers.wakeupVec ++ 219 fpScheduler.io.toSchedulers.wakeupVec ++ 220 vfScheduler.io.toSchedulers.wakeupVec ++ 221 memScheduler.io.toSchedulers.wakeupVec 222 ).map(x => (x.bits.exuIdx, x)).toMap 223 224 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 225 226 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 227 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 228 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 229 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 230 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 231 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 232 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 233 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 234 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 235 236 private val og1Cancel = dataPath.io.og1Cancel 237 private val og0Cancel = dataPath.io.og0Cancel 238 private val vlFromIntIsZero = intExuBlock.io.vlIsZero.get 239 private val vlFromIntIsVlmax = intExuBlock.io.vlIsVlmax.get 240 private val vlFromVfIsZero = vfExuBlock.io.vlIsZero.get 241 private val vlFromVfIsVlmax = vfExuBlock.io.vlIsVlmax.get 242 243 private val backendCriticalError = Wire(Bool()) 244 245 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 246 ctrlBlock.io.frontend <> io.frontend 247 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 248 ctrlBlock.io.fromCSR.traceCSR := intExuBlock.io.csrio.get.traceCSR 249 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 250 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 251 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 252 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 253 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 254 255 io.mem.lsqEnqIO <> ctrlBlock.io.toMem.lsqEnqIO 256 ctrlBlock.io.fromMemToDispatch.scommit := io.mem.sqDeq 257 ctrlBlock.io.fromMemToDispatch.lcommit := io.mem.lqDeq 258 ctrlBlock.io.fromMemToDispatch.sqDeqPtr := io.mem.sqDeqPtr 259 ctrlBlock.io.fromMemToDispatch.lqDeqPtr := io.mem.lqDeqPtr 260 ctrlBlock.io.fromMemToDispatch.sqCancelCnt := io.mem.sqCancelCnt 261 ctrlBlock.io.fromMemToDispatch.lqCancelCnt := io.mem.lqCancelCnt 262 ctrlBlock.io.toDispatch.wakeUpInt := intScheduler.io.toSchedulers.wakeupVec 263 ctrlBlock.io.toDispatch.wakeUpFp := fpScheduler.io.toSchedulers.wakeupVec 264 ctrlBlock.io.toDispatch.wakeUpVec := vfScheduler.io.toSchedulers.wakeupVec 265 ctrlBlock.io.toDispatch.wakeUpMem := memScheduler.io.toSchedulers.wakeupVec 266 ctrlBlock.io.toDispatch.IQValidNumVec := intScheduler.io.IQValidNumVec ++ fpScheduler.io.IQValidNumVec ++ vfScheduler.io.IQValidNumVec ++ memScheduler.io.IQValidNumVec 267 ctrlBlock.io.toDispatch.ldCancel := io.mem.ldCancel 268 ctrlBlock.io.toDispatch.og0Cancel := og0Cancel 269 ctrlBlock.io.toDispatch.wbPregsInt.zip(wbDataPath.io.toIntPreg).map(x => { 270 x._1.valid := x._2.wen && x._2.intWen 271 x._1.bits := x._2.addr 272 }) 273 ctrlBlock.io.toDispatch.wbPregsFp.zip(wbDataPath.io.toFpPreg).map(x => { 274 x._1.valid := x._2.wen && x._2.fpWen 275 x._1.bits := x._2.addr 276 }) 277 ctrlBlock.io.toDispatch.wbPregsVec.zip(wbDataPath.io.toVfPreg).map(x => { 278 x._1.valid := x._2.wen && x._2.vecWen 279 x._1.bits := x._2.addr 280 }) 281 ctrlBlock.io.toDispatch.wbPregsV0.zip(wbDataPath.io.toV0Preg).map(x => { 282 x._1.valid := x._2.wen && x._2.v0Wen 283 x._1.bits := x._2.addr 284 }) 285 ctrlBlock.io.toDispatch.wbPregsVl.zip(wbDataPath.io.toVlPreg).map(x => { 286 x._1.valid := x._2.wen && x._2.vlWen 287 x._1.bits := x._2.addr 288 }) 289 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 290 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 291 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 292 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 293 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 294 ctrlBlock.io.robio.csr.criticalErrorState := intExuBlock.io.csrio.get.criticalErrorState 295 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 296 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 297 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 298 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 299 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 300 ctrlBlock.io.debugEnqLsq.req := ctrlBlock.io.toMem.lsqEnqIO.req 301 ctrlBlock.io.debugEnqLsq.needAlloc := ctrlBlock.io.toMem.lsqEnqIO.needAlloc 302 ctrlBlock.io.debugEnqLsq.iqAccept := ctrlBlock.io.toMem.lsqEnqIO.iqAccept 303 ctrlBlock.io.fromVecExcpMod.busy := vecExcpMod.o.status.busy 304 305 intScheduler.io.fromTop.hartId := io.fromTop.hartId 306 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 307 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 308 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 309 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 310 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 311 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 312 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 313 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 314 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 315 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 316 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 317 intScheduler.io.ldCancel := io.mem.ldCancel 318 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 319 intScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 320 intScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 321 intScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 322 intScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 323 324 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 325 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 326 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 327 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 328 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 329 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 330 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 331 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 332 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 333 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 334 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 335 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 336 fpScheduler.io.ldCancel := io.mem.ldCancel 337 fpScheduler.io.vlWriteBackInfo.vlFromIntIsZero := false.B 338 fpScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := false.B 339 fpScheduler.io.vlWriteBackInfo.vlFromVfIsZero := false.B 340 fpScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := false.B 341 342 memScheduler.io.fromTop.hartId := io.fromTop.hartId 343 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 344 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 345 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 346 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 347 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 348 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 349 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 350 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 351 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 352 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 353 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 354 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 355 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 356 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 357 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 358 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 359 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 360 sink.valid := source.valid 361 sink.bits := source.bits.robIdx 362 } 363 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 364 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 365 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 366 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 367 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 368 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 369 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 370 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 371 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 372 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 373 memScheduler.io.ldCancel := io.mem.ldCancel 374 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 375 memScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 376 memScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 377 memScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 378 memScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 379 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 380 381 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 382 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 383 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 384 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 385 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 386 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 387 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 388 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 389 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 390 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 391 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 392 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 393 vfScheduler.io.ldCancel := io.mem.ldCancel 394 vfScheduler.io.vlWriteBackInfo.vlFromIntIsZero := vlFromIntIsZero 395 vfScheduler.io.vlWriteBackInfo.vlFromIntIsVlmax := vlFromIntIsVlmax 396 vfScheduler.io.vlWriteBackInfo.vlFromVfIsZero := vlFromVfIsZero 397 vfScheduler.io.vlWriteBackInfo.vlFromVfIsVlmax := vlFromVfIsVlmax 398 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 399 400 dataPath.io.hartId := io.fromTop.hartId 401 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 402 403 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 404 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 405 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 406 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 407 408 dataPath.io.ldCancel := io.mem.ldCancel 409 410 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 411 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 412 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 413 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 414 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 415 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 416 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 417 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 418 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 419 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 420 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 421 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 422 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 423 dataPath.io.fromVecExcpMod.r := vecExcpMod.o.toVPRF.r 424 dataPath.io.fromVecExcpMod.w := vecExcpMod.o.toVPRF.w 425 426 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 427 og2ForVector.io.ldCancel := io.mem.ldCancel 428 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 429 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 430 .foreach { 431 case (og1Mem, datapathMem) => og1Mem <> datapathMem 432 } 433 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 434 435 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 436 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 437 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 438 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 439 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 440 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 441 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 442 .map(x => (x._1, x._3)).foreach { 443 case (bypassMem, datapathMem) => bypassMem <> datapathMem 444 } 445 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 446 .zip(og2ForVector.io.toVecMemExu).foreach { 447 case (bypassMem, og2Mem) => bypassMem <> og2Mem 448 } 449 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 450 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 451 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 452 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 453 } 454 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 455 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 456 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 457 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 458 459 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 460 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 461 s"io.mem.writeback(${io.mem.writeBack.size})" 462 ) 463 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 464 sink.valid := source.valid 465 sink.bits.intWen := source.bits.uop.rfWen && source.bits.isFromLoadUnit 466 sink.bits.pdest := source.bits.uop.pdest 467 sink.bits.data := source.bits.data 468 } 469 470 471 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 472 for (i <- 0 until intExuBlock.io.in.length) { 473 for (j <- 0 until intExuBlock.io.in(i).length) { 474 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 475 NewPipelineConnect( 476 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 477 Mux( 478 bypassNetwork.io.toExus.int(i)(j).fire, 479 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 480 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 481 ), 482 Option("bypassNetwork2intExuBlock") 483 ) 484 } 485 } 486 487 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 488 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 489 490 private val csrin = intExuBlock.io.csrin.get 491 csrin.hartId := io.fromTop.hartId 492 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 493 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 494 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 495 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 496 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 497 csrin.fromVecExcpMod.busy := vecExcpMod.o.status.busy 498 csrin.criticalErrorState := backendCriticalError 499 500 private val csrio = intExuBlock.io.csrio.get 501 csrio.hartId := io.fromTop.hartId 502 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 503 csrio.fpu.isIllegal := false.B // Todo: remove it 504 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 505 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 506 507 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 508 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 509 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 510 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 511 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 512 513 val commitVType = ctrlBlock.io.robio.commitVType.vtype 514 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 515 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 516 517 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 518 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 519 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 520 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 521 debugVl_s1 := RegNext(debugVl_s0) 522 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 523 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 524 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 525 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 526 //Todo here need change design 527 csrio.vpu.set_vtype.valid := commitVType.valid 528 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 529 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 530 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 531 csrio.exception := ctrlBlock.io.robio.exception 532 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 533 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 534 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 535 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 536 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 537 csrio.perf <> io.perf 538 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 539 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 540 private val fenceio = intExuBlock.io.fenceio.get 541 io.fenceio <> fenceio 542 543 // to fpExuBlock 544 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 545 for (i <- 0 until fpExuBlock.io.in.length) { 546 for (j <- 0 until fpExuBlock.io.in(i).length) { 547 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 548 NewPipelineConnect( 549 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 550 Mux( 551 bypassNetwork.io.toExus.fp(i)(j).fire, 552 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 553 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 554 ), 555 Option("bypassNetwork2fpExuBlock") 556 ) 557 } 558 } 559 560 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 561 for (i <- 0 until vfExuBlock.io.in.size) { 562 for (j <- 0 until vfExuBlock.io.in(i).size) { 563 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 564 NewPipelineConnect( 565 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 566 Mux( 567 bypassNetwork.io.toExus.vf(i)(j).fire, 568 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 569 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 570 ), 571 Option("bypassNetwork2vfExuBlock") 572 ) 573 574 } 575 } 576 577 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 578 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 579 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 580 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 581 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 582 583 wbDataPath.io.flush := ctrlBlock.io.redirect 584 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 585 wbDataPath.io.fromIntExu <> intExuBlock.io.out 586 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 587 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 588 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 589 sink.valid := source.valid 590 source.ready := sink.ready 591 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 592 sink.bits.pdest := source.bits.uop.pdest 593 sink.bits.robIdx := source.bits.uop.robIdx 594 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 595 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 596 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 597 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 598 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 599 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 600 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 601 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 602 sink.bits.debug := source.bits.debug 603 sink.bits.debugInfo := source.bits.uop.debugInfo 604 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 605 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 606 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 607 sink.bits.vls.foreach(x => { 608 x.vdIdx := source.bits.vdIdx.get 609 x.vdIdxInField := source.bits.vdIdxInField.get 610 x.vpu := source.bits.uop.vpu 611 x.oldVdPsrc := source.bits.uop.psrc(2) 612 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 613 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 614 x.isStrided := VlduType.isStrided(source.bits.uop.fuOpType) 615 x.isWhole := VlduType.isWhole(source.bits.uop.fuOpType) 616 x.isVecLoad := VlduType.isVecLd(source.bits.uop.fuOpType) 617 x.isVlm := VlduType.isMasked(source.bits.uop.fuOpType) && VlduType.isVecLd(source.bits.uop.fuOpType) 618 }) 619 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 620 } 621 wbDataPath.io.fromCSR.vstart := csrio.vpu.vstart 622 623 vecExcpMod.i.fromExceptionGen := ctrlBlock.io.toVecExcpMod.excpInfo 624 vecExcpMod.i.fromRab.logicPhyRegMap := ctrlBlock.io.toVecExcpMod.logicPhyRegMap 625 vecExcpMod.i.fromRat := ctrlBlock.io.toVecExcpMod.ratOldPest 626 vecExcpMod.i.fromVprf := dataPath.io.toVecExcpMod 627 628 // to mem 629 private val memIssueParams = params.memSchdParams.get.issueBlockParams 630 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 631 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 632 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 633 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 634 635 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 636 for (i <- toMem.indices) { 637 for (j <- toMem(i).indices) { 638 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 639 val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) 640 val issueTimeout = 641 if (needIssueTimeout) 642 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 643 else 644 false.B 645 646 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 647 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 648 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 649 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 650 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 651 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 652 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 653 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 654 } 655 656 if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 657 memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout 658 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 659 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block 660 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 661 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 662 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 663 memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 664 } 665 666 NewPipelineConnect( 667 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 668 Mux( 669 bypassNetwork.io.toExus.mem(i)(j).fire, 670 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 671 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 672 ), 673 Option("bypassNetwork2toMemExus") 674 ) 675 676 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 677 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 678 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 679 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 680 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 681 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 682 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 683 } 684 685 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 686 memScheduler.io.vecLoadIssueResp(i)(j) match { 687 case resp => 688 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 689 resp.bits.fuType := toMem(i)(j).bits.fuType 690 resp.bits.robIdx := toMem(i)(j).bits.robIdx 691 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 692 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 693 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 694 resp.bits.resp := RespType.success 695 } 696 if (backendParams.debugEn){ 697 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 698 } 699 } 700 } 701 } 702 703 io.mem.redirect := ctrlBlock.io.redirect 704 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 705 val enableMdp = Constantin.createRecord("EnableMdp", true) 706 sink.valid := source.valid 707 source.ready := sink.ready 708 sink.bits.iqIdx := source.bits.iqIdx 709 sink.bits.isFirstIssue := source.bits.isFirstIssue 710 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 711 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 712 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 713 sink.bits.uop.fuType := source.bits.fuType 714 sink.bits.uop.fuOpType := source.bits.fuOpType 715 sink.bits.uop.imm := source.bits.imm 716 sink.bits.uop.robIdx := source.bits.robIdx 717 sink.bits.uop.pdest := source.bits.pdest 718 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 719 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 720 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 721 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 722 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 723 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 724 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 725 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 726 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 727 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 728 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 729 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 730 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 731 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 732 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 733 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 734 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 735 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 736 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 737 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 738 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 739 } 740 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 741 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 742 io.mem.tlbCsr := csrio.tlb 743 io.mem.csrCtrl := csrio.customCtrl 744 io.mem.sfence := fenceio.sfence 745 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 746 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 747 require(io.mem.loadPcRead.size == params.LduCnt) 748 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 749 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 750 ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid 751 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 752 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 753 } 754 755 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 756 storePcRead := ctrlBlock.io.memStPcRead(i).data 757 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 758 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 759 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 760 } 761 762 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 763 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 764 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 765 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 766 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 767 }) 768 769 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 770 771 // mem io 772 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 773 io.mem.storeDebugInfo <> ctrlBlock.io.robio.storeDebugInfo 774 775 io.frontendSfence := fenceio.sfence 776 io.frontendTlbCsr := csrio.tlb 777 io.frontendCsrCtrl := csrio.customCtrl 778 779 io.tlb <> csrio.tlb 780 781 io.csrCustomCtrl := csrio.customCtrl 782 783 io.toTop.cpuHalted := ctrlBlock.io.toTop.cpuHalt 784 785 io.traceCoreInterface <> ctrlBlock.io.traceCoreInterface 786 787 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 788 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 789 790 io.debugRolling := ctrlBlock.io.debugRolling 791 792 if(backendParams.debugEn) { 793 dontTouch(memScheduler.io) 794 dontTouch(dataPath.io.toMemExu) 795 dontTouch(wbDataPath.io.fromMemExu) 796 } 797 798 // reset tree 799 if (p(DebugOptionsKey).ResetGen) { 800 val rightResetTree = ResetGenNode(Seq( 801 ModuleNode(dataPath), 802 ModuleNode(intExuBlock), 803 ModuleNode(fpExuBlock), 804 ModuleNode(vfExuBlock), 805 ModuleNode(bypassNetwork), 806 ModuleNode(wbDataPath) 807 )) 808 val leftResetTree = ResetGenNode(Seq( 809 ModuleNode(pcTargetMem), 810 ModuleNode(intScheduler), 811 ModuleNode(fpScheduler), 812 ModuleNode(vfScheduler), 813 ModuleNode(memScheduler), 814 ModuleNode(og2ForVector), 815 ModuleNode(wbFuBusyTable), 816 ResetGenNode(Seq( 817 ModuleNode(ctrlBlock), 818 // ResetGenNode(Seq( 819 CellNode(io.frontendReset) 820 // )) 821 )) 822 )) 823 ResetGen(leftResetTree, reset, sim = false) 824 ResetGen(rightResetTree, reset, sim = false) 825 } else { 826 io.frontendReset := DontCare 827 } 828 829 // perf events 830 val pfevent = Module(new PFEvent) 831 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 832 val csrevents = pfevent.io.hpmevent.slice(8,16) 833 834 val ctrlBlockPerf = ctrlBlock.getPerfEvents 835 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 836 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 837 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 838 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 839 840 val perfBackend = Seq() 841 // let index = 0 be no event 842 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 843 844 845 if (printEventCoding) { 846 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 847 println("backend perfEvents Set", name, inc, i) 848 } 849 } 850 851 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 852 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 853 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 854 855 val ctrlBlockError = ctrlBlock.getCriticalErrors 856 val intExuBlockError = intExuBlock.getCriticalErrors 857 val criticalErrors = ctrlBlockError ++ intExuBlockError 858 859 if (printCriticalError) { 860 for (((name, error), _) <- criticalErrors.zipWithIndex) { 861 XSError(error, s"critical error: $name \n") 862 } 863 } 864 865 // expand to collect frontend/memblock/L2 critical errors 866 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _) 867 868 io.toTop.cpuCriticalError := csrio.criticalErrorState 869} 870 871class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 872 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 873 val flippedLda = true 874 // params alias 875 private val LoadQueueSize = VirtualLoadQueueSize 876 // In/Out // Todo: split it into one-direction bundle 877 val lsqEnqIO = Flipped(new LsqEnqIO) 878 val robLsqIO = new RobLsqIO 879 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 880 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 881 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 882 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 883 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 884 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 885 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 886 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 887 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 888 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 889 // Input 890 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 891 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 892 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 893 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 894 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 895 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 896 897 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 898 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 899 val memoryViolation = Flipped(ValidIO(new Redirect)) 900 val exceptionAddr = Input(new Bundle { 901 val vaddr = UInt(XLEN.W) 902 val gpaddr = UInt(XLEN.W) 903 val isForVSnonLeafPTE = Bool() 904 }) 905 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 906 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 907 val sqDeqPtr = Input(new SqPtr) 908 val lqDeqPtr = Input(new LqPtr) 909 910 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 911 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 912 913 val lqCanAccept = Input(Bool()) 914 val sqCanAccept = Input(Bool()) 915 916 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 917 val stIssuePtr = Input(new SqPtr()) 918 919 val debugLS = Flipped(Output(new DebugLSIO)) 920 921 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 922 // Output 923 val redirect = ValidIO(new Redirect) // rob flush MemBlock 924 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 925 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 926 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 927 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 928 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 929 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 930 931 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 932 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 933 934 val tlbCsr = Output(new TlbCsrBundle) 935 val csrCtrl = Output(new CustomCSRCtrlIO) 936 val sfence = Output(new SfenceBundle) 937 val isStoreException = Output(Bool()) 938 val isVlsException = Output(Bool()) 939 940 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 941 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 942 issueSta ++ 943 issueHylda ++ issueHysta ++ 944 issueLda ++ 945 issueVldu ++ 946 issueStd 947 }.toSeq 948 949 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 950 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 951 writebackSta ++ 952 writebackHyuLda ++ writebackHyuSta ++ 953 writebackLda ++ 954 writebackVldu ++ 955 writebackStd 956 } 957 958 // store event difftest information 959 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle { 960 val robidx = Input(new RobPtr) 961 val pc = Output(UInt(VAddrBits.W)) 962 }) 963} 964 965class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 966 val hartId = Output(UInt(hartIdLen.W)) 967 val externalInterrupt = Output(new ExternalInterruptIO) 968 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 969 val clintTime = Output(ValidIO(UInt(64.W))) 970} 971 972class BackendToTopBundle extends Bundle { 973 val cpuHalted = Output(Bool()) 974 val cpuCriticalError = Output(Bool()) 975} 976 977class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 978 val fromTop = Flipped(new TopToBackendBundle) 979 980 val toTop = new BackendToTopBundle 981 982 val traceCoreInterface = new TraceCoreInterface 983 984 val fenceio = new FenceIO 985 // Todo: merge these bundles into BackendFrontendIO 986 val frontend = Flipped(new FrontendToCtrlIO) 987 val frontendSfence = Output(new SfenceBundle) 988 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 989 val frontendTlbCsr = Output(new TlbCsrBundle) 990 val frontendReset = Output(Reset()) 991 992 val mem = new BackendMemIO 993 994 val perf = Input(new PerfCounterIO) 995 996 val tlb = Output(new TlbCsrBundle) 997 998 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 999 1000 val debugTopDown = new Bundle { 1001 val fromRob = new RobCoreTopDownIO 1002 val fromCore = new CoreDispatchTopDownIO 1003 } 1004 val debugRolling = new RobDebugRollingIO 1005} 1006