1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.{ParallelOR, XSInfo} 7 8class Rename extends XSModule { 9 val io = IO(new Bundle() { 10 val redirect = Flipped(ValidIO(new Redirect)) 11 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 12 val wbIntResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 13 val wbFpResults = Vec(NRWritePorts, Flipped(ValidIO(new ExuOutput))) 14 val intRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 15 val fpRfReadAddr = Vec(NRReadPorts, Input(UInt(PhyRegIdxWidth.W))) 16 val intPregRdy = Vec(NRReadPorts, Output(Bool())) 17 val fpPregRdy = Vec(NRReadPorts, Output(Bool())) 18 // from decode buffer 19 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 20 // to dispatch1 21 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 22 }) 23 24 val isWalk = ParallelOR(io.roqCommits.map(x => x.valid && x.bits.isWalk)).asBool() 25 26 val debug_exception = io.redirect.valid && io.redirect.bits.isException 27 val debug_walk = isWalk 28 val debug_norm = !(debug_exception || debug_walk) 29 30 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 31 XSInfo( 32 debug_norm, 33 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 34 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 35 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 36 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 37 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 38 p"old_pdest:${out.bits.old_pdest}" + 39 p"out v:${out.valid} r:${out.ready}\n" 40 ) 41 } 42 43 for((x,y) <- io.in.zip(io.out)){ 44 printRenameInfo(x, y) 45 } 46 47 val fpFreeList, intFreeList = Module(new FreeList).io 48 val fpRat = Module(new RenameTable(float = true)).io 49 val intRat = Module(new RenameTable(float = false)).io 50 val fpBusyTable, intBusyTable = Module(new BusyTable).io 51 52 fpFreeList.redirect := DontCare 53 intFreeList.redirect := io.redirect 54 55 val flush = io.redirect.valid && io.redirect.bits.isException 56 fpRat.flush := flush 57 intRat.flush := flush 58 fpBusyTable.flush := flush 59 intBusyTable.flush := flush 60 61 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 62 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 63 } 64 65 val uops = Wire(Vec(RenameWidth, new MicroOp)) 66 67 uops.foreach( uop => { 68// uop.brMask := DontCare 69// uop.brTag := DontCare 70 uop.src1State := DontCare 71 uop.src2State := DontCare 72 uop.src3State := DontCare 73 uop.roqIdx := DontCare 74 }) 75 76 var lastReady = WireInit(true.B) 77 for(i <- 0 until RenameWidth) { 78 uops(i).cf := io.in(i).bits.cf 79 uops(i).ctrl := io.in(i).bits.ctrl 80 uops(i).brTag := io.in(i).bits.brTag 81 82 val inValid = io.in(i).valid && !isWalk 83 84 // alloc a new phy reg 85 val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits) 86 val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits) 87 fpFreeList.allocReqs(i) := needFpDest && lastReady && io.out(i).ready 88 intFreeList.allocReqs(i) := needIntDest && lastReady && io.out(i).ready 89 val fpCanAlloc = fpFreeList.canAlloc(i) 90 val intCanAlloc = intFreeList.canAlloc(i) 91 val this_can_alloc = Mux(needIntDest, intCanAlloc, fpCanAlloc) 92 io.in(i).ready := lastReady && io.out(i).ready && this_can_alloc && !isWalk 93 94 // do checkpoints when a branch inst come 95 for(fl <- Seq(fpFreeList, intFreeList)){ 96 fl.cpReqs(i).valid := inValid 97 fl.cpReqs(i).bits := io.in(i).bits.brTag 98 } 99 100 lastReady = io.in(i).ready 101 102 uops(i).pdest := Mux(needIntDest, 103 intFreeList.pdests(i), 104 Mux( 105 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 106 0.U, fpFreeList.pdests(i) 107 ) 108 ) 109 110 io.out(i).valid := io.in(i).fire() 111 io.out(i).bits := uops(i) 112 113 // write rename table 114 def writeRat(fp: Boolean) = { 115 val rat = if(fp) fpRat else intRat 116 val freeList = if(fp) fpFreeList else intFreeList 117 val busyTable = if(fp) fpBusyTable else intBusyTable 118 // speculative inst write 119 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 120 // walk back write 121 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 122 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 123 124 rat.specWritePorts(i).wen := specWen || walkWen 125 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 126 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 127 128 busyTable.wbPregs(NRWritePorts + i).valid := walkWen 129 busyTable.wbPregs(NRWritePorts + i).bits := io.roqCommits(i).bits.uop.pdest 130 131 XSInfo(walkWen, 132 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" + 133 p" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 134 ) 135 136 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 137 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 138 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 139 140 XSInfo(rat.archWritePorts(i).wen, 141 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 142 p" pdest:${rat.archWritePorts(i).wdata}\n" 143 ) 144 145 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 146 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 147 148 // set phy reg status to busy 149 busyTable.allocPregs(i).valid := specWen 150 busyTable.allocPregs(i).bits := freeList.pdests(i) 151 } 152 153 writeRat(fp = false) 154 writeRat(fp = true) 155 156 // read rename table 157 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 158 val rat = if(fp) fpRat else intRat 159 val srcCnt = lsrcList.size 160 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 161 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 162 for(k <- 0 until srcCnt+1){ 163 val rportIdx = i * (srcCnt+1) + k 164 if(k != srcCnt){ 165 rat.readPorts(rportIdx).addr := lsrcList(k) 166 psrcVec(k) := rat.readPorts(rportIdx).rdata 167 } else { 168 rat.readPorts(rportIdx).addr := ldest 169 old_pdest := rat.readPorts(rportIdx).rdata 170 } 171 } 172 (psrcVec, old_pdest) 173 } 174 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 175 val ldest = uops(i).ctrl.ldest 176 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 177 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 178 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 179 uops(i).psrc2 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 180 uops(i).psrc3 := fpPhySrcVec(2) 181 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 182 } 183 184 185 def updateBusyTable(fp: Boolean) = { 186 val wbResults = if(fp) io.wbFpResults else io.wbIntResults 187 val busyTable = if(fp) fpBusyTable else intBusyTable 188 for((wb, setPhyRegRdy) <- wbResults.zip(busyTable.wbPregs.take(NRWritePorts))){ 189 setPhyRegRdy.valid := wb.valid && needDestReg(fp, wb.bits.uop) 190 setPhyRegRdy.bits := wb.bits.uop.pdest 191 } 192 } 193 194 updateBusyTable(false) 195 updateBusyTable(true) 196 197 intBusyTable.rfReadAddr <> io.intRfReadAddr 198 intBusyTable.pregRdy <> io.intPregRdy 199 fpBusyTable.rfReadAddr <> io.fpRfReadAddr 200 fpBusyTable.pregRdy <> io.fpPregRdy 201} 202