xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision 6e962ad096fc22e07e37e258f79cdf715666e003) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Parameters
9import xiangshan.backend.exu.ExuParameters
10import xiangshan.frontend._
11import xiangshan.mem._
12import utils._
13
14trait HasXSParameter {
15  val XLEN = 64
16  val HasMExtension = true
17  val HasCExtension = true
18  val HasDiv = true
19  val HasIcache = true
20  val HasDcache = true
21  val EnableStoreQueue = false
22  val AddrBits = 64 // AddrBits is used in some cases
23  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
24  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
25  val AddrBytes = AddrBits / 8 // unused
26  val DataBits = XLEN
27  val DataBytes = DataBits / 8
28  val CacheLineSize = 512
29  val SbufferSize = 16
30  val HasFPU = true
31  val FetchWidth = 8
32  val PredictWidth = FetchWidth * 2
33  val EnableBPU = true
34  val EnableBPD = false // enable backing predictor(like Tage) in BPUStage3
35  val EnableRAS = false
36  val HistoryLength = 64
37  val BtbSize = 256
38  // val BtbWays = 4
39  val BtbBanks = PredictWidth
40  // val BtbSets = BtbSize / BtbWays
41  val JbtacSize = 1024
42  val JbtacBanks = 8
43  val RasSize = 16
44  val IBufSize = 64
45  val DecodeWidth = 6
46  val RenameWidth = 6
47  val CommitWidth = 6
48  val BrqSize = 16
49  val IssQueSize = 8
50  val BrTagWidth = log2Up(BrqSize)
51  val NRPhyRegs = 128
52  val PhyRegIdxWidth = log2Up(NRPhyRegs)
53  val exuParameters = ExuParameters(
54    JmpCnt = 1,
55    AluCnt = 4,
56    MulCnt = 1,
57    MduCnt = 1,
58    FmacCnt = 0,
59    FmiscCnt = 0,
60    FmiscDivSqrtCnt = 0,
61    LduCnt = 2,
62    StuCnt = 2
63  )
64  val NRIntReadPorts = 8
65  val NRIntWritePorts = 8
66  val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt
67  val NRFpReadPorts = 14
68  val NRFpWritePorts = 8
69  val MoqSize = 16 // 64
70  val RoqSize = 32
71  val InnerRoqIdxWidth = log2Up(RoqSize)
72  val RoqIdxWidth = InnerRoqIdxWidth + 1
73  val InnerMoqIdxWidth = log2Up(MoqSize)
74  val MoqIdxWidth = InnerMoqIdxWidth + 1
75  val IntDqDeqWidth = 4
76  val FpDqDeqWidth = 4
77  val LsDqDeqWidth = 4
78  val dp1Paremeters = DP1Parameters(
79    IntDqSize = 16,
80    FpDqSize = 16,
81    LsDqSize = 16
82  )
83}
84
85trait HasXSLog { this: Module =>
86  implicit val moduleName: String = this.name
87}
88
89abstract class XSModule extends Module
90  with HasXSParameter
91  with HasExceptionNO
92  with HasXSLog
93
94//remove this trait after impl module logic
95trait NeedImpl { this: Module =>
96  override protected def IO[T <: Data](iodef: T): T = {
97    val io = chisel3.experimental.IO(iodef)
98    io <> DontCare
99    io
100  }
101}
102
103abstract class XSBundle extends Bundle
104  with HasXSParameter
105
106case class XSConfig
107(
108  FPGAPlatform: Boolean = true,
109  EnableDebug: Boolean = true
110)
111
112object AddressSpace extends HasXSParameter {
113  // (start, size)
114  // address out of MMIO will be considered as DRAM
115  def mmio = List(
116    (0x30000000L, 0x10000000L),  // internal devices, such as CLINT and PLIC
117    (0x40000000L, 0x40000000L) // external devices
118  )
119
120  def isMMIO(addr: UInt): Bool = mmio.map(range => {
121    require(isPow2(range._2))
122    val bits = log2Up(range._2)
123    (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
124  }).reduce(_ || _)
125}
126
127
128class XSCore(implicit p: XSConfig) extends XSModule with HasMEMConst {
129  val io = IO(new Bundle {
130    val imem = new SimpleBusC
131    val dmem = new SimpleBusC
132    val mmio = new SimpleBusUC
133    val frontend = Flipped(new SimpleBusUC())
134  })
135
136  io.imem <> DontCare
137
138  val dmemXbar = Module(new SimpleBusCrossbarNto1(n = 2, userBits = DcacheUserBundleWidth))
139
140  val front = Module(new Frontend)
141  val backend = Module(new Backend)
142  val mem = Module(new Memend)
143
144  front.io.backend <> backend.io.frontend
145  mem.io.backend   <> backend.io.mem
146
147  backend.io.memMMU.imem <> DontCare
148
149  val dtlb = TLB(
150    in = mem.io.dmem,
151    mem = dmemXbar.io.in(1),
152    flush = false.B,
153    csrMMU = backend.io.memMMU.dmem
154  )(TLBConfig(name = "dtlb", totalEntry = 64, userBits = DcacheUserBundleWidth))
155  dmemXbar.io.in(0) <> dtlb.io.out
156  // dmemXbar.io.in(1) <> io.frontend
157
158  io.frontend <> DontCare
159
160  io.dmem <> Cache(
161    in = dmemXbar.io.out,
162    mmio = Seq(io.mmio),
163    flush = "b00".U,
164    empty = dtlb.io.cacheEmpty,
165    enable = HasDcache
166  )(CacheConfig(name = "dcache", userBits = DcacheUserBundleWidth))
167
168}
169