xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 0b791572c737d0df2e597dfaaad918b23c40a251) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.IssueQueue
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18
19
20/** Backend Pipeline:
21  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
22  */
23class Backend(implicit val p: XSConfig) extends XSModule
24  with HasExeUnits
25  with NeedImpl {
26  val io = IO(new Bundle {
27    val dmem = new SimpleBusUC(addrBits = VAddrBits)
28    val memMMU = Flipped(new MemMMUIO)
29    val frontend = Flipped(new FrontendToBackendIO)
30  })
31
32
33  val decode = Module(new DecodeStage)
34  val brq = Module(new Brq)
35  val decBuf = Module(new DecodeBuffer)
36  val rename = Module(new Rename)
37  val dispatch = Module(new Dispatch)
38  val roq = Module(new Roq)
39  val intRf = Module(new Regfile(
40    numReadPorts = NRReadPorts,
41    numWirtePorts = NRWritePorts,
42    hasZero = true
43  ))
44  val fpRf = Module(new Regfile(
45    numReadPorts = NRReadPorts,
46    numWirtePorts = NRWritePorts,
47    hasZero = false
48  ))
49
50  // backend redirect, flush pipeline
51  val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect)
52
53  val redirectInfo = Wire(new RedirectInfo)
54  // exception or misprediction
55  redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid
56  redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid
57  redirectInfo.redirect := redirect.bits
58
59  val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) =>
60    def needBypass(cfg: ExuConfig): Boolean = cfg.enableBypass
61
62    val bypassCnt = exeUnits.map(_.config).count(needBypass)
63    def needWakeup(cfg: ExuConfig): Boolean =
64      (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
65
66    val wakeupCnt = exeUnits.map(_.config).count(needWakeup)
67    assert(!(needBypass(eu.config) && !needWakeup(eu.config))) // needBypass but dont needWakeup is not allowed
68    val iq = Module(new IssueQueue(
69      eu.config,
70      wakeupCnt,
71      bypassCnt,
72      eu.config.enableBypass,
73      fifo = eu.config.supportedFuncUnits.contains(FunctionUnit.lsuCfg)
74    ))
75    iq.io.redirect <> redirect
76    iq.io.numExist <> dispatch.io.numExist(i)
77    iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
78    iq.io.enqData <> dispatch.io.enqIQData(i)
79    val wuUnitsOut = exeUnits.filter(e => needWakeup(e.config)).map(_.io.out)
80    for (i <- iq.io.wakeUpPorts.indices) {
81      iq.io.wakeUpPorts(i).bits <> wuUnitsOut(i).bits
82      iq.io.wakeUpPorts(i).valid := wuUnitsOut(i).valid
83    }
84    println(
85      s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" +
86        s" Supported Function:[" +
87        s"${
88          eu.config.supportedFuncUnits.map(
89            fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", "
90          )
91        }]"
92    )
93    eu.io.in <> iq.io.deq
94    eu.io.redirect <> redirect
95    iq
96  })
97
98  val bypassQueues = issueQueues.filter(_.enableBypass)
99  val bypassUnits = exeUnits.filter(_.config.enableBypass)
100  issueQueues.foreach(iq => {
101    for (i <- iq.io.bypassUops.indices) {
102      iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits
103      iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid
104    }
105    iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop)
106  })
107
108  lsuExeUnits.foreach(_.io.dmem <> io.dmem)
109  lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit)
110
111  io.frontend.redirectInfo <> redirectInfo
112  io.frontend.commits <> roq.io.commits
113
114  decode.io.in <> io.frontend.cfVec
115  brq.io.roqRedirect <> roq.io.redirect
116  brq.io.enqReqs <> decode.io.toBrq
117  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
118    x.bits := y.io.out.bits
119    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
120  }
121  decode.io.brTags <> brq.io.brTags
122  decBuf.io.redirect <> redirect
123  decBuf.io.in <> decode.io.out
124
125  rename.io.redirect <> redirect
126  rename.io.roqCommits <> roq.io.commits
127  rename.io.in <> decBuf.io.out
128  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr)
129  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr)
130  rename.io.intPregRdy <> dispatch.io.intPregRdy
131  rename.io.fpPregRdy <> dispatch.io.fpPregRdy
132
133  dispatch.io.redirect <> redirect
134  dispatch.io.fromRename <> rename.io.out
135
136  roq.io.brqRedirect <> brq.io.redirect
137  roq.io.dp1Req <> dispatch.io.toRoq
138  dispatch.io.roqIdxs <> roq.io.roqIdxs
139
140  intRf.io.readPorts <> dispatch.io.readIntRf
141  fpRf.io.readPorts <> dispatch.io.readFpRf
142
143  val exeWbReqs = exeUnits.map(_.io.out)
144
145  val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.config.writeIntRf).map(_._2)
146  val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.config.writeFpRf).map(_._2)
147
148  val wbu = Module(new Wbu(wbIntIdx, wbFpIdx))
149  wbu.io.in <> exeWbReqs
150
151  val wbIntResults = wbu.io.toIntRf
152  val wbFpResults = wbu.io.toFpRf
153
154  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
155    val rfWrite = Wire(new RfWritePort)
156    rfWrite.wen := x.valid
157    rfWrite.addr := x.bits.uop.pdest
158    rfWrite.data := x.bits.data
159    rfWrite
160  }
161
162  intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite)
163  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
164
165  rename.io.wbIntResults <> wbIntResults
166  rename.io.wbFpResults <> wbFpResults
167
168  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
169  roq.io.exeWbResults.last := brq.io.out
170
171
172  // TODO: Remove sink and source
173  val tmp = WireInit(0.U)
174  val sinks = Array[String](
175    "DTLBFINISH",
176    "DTLBPF",
177    "DTLBENABLE",
178    "perfCntCondMdcacheLoss",
179    "perfCntCondMl2cacheLoss",
180    "perfCntCondMdcacheHit",
181    "lsuMMIO",
182    "perfCntCondMl2cacheHit",
183    "perfCntCondMl2cacheReq",
184    "mtip",
185    "perfCntCondMdcacheReq",
186    "meip"
187  )
188  for (s <- sinks) {
189    BoringUtils.addSink(tmp, s)
190  }
191
192  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
193  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
194  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
195  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
196  if (!p.FPGAPlatform) {
197    BoringUtils.addSource(debugArchReg, "difftestRegs")
198  }
199
200}
201