xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 6e962ad096fc22e07e37e258f79cdf715666e003) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.{IssueQueue, ReservationStation}
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18import xiangshan.mem._
19
20
21/** Backend Pipeline:
22  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
23  */
24class Backend(implicit val p: XSConfig) extends XSModule
25  with NeedImpl {
26  val io = IO(new Bundle {
27    // val dmem = new SimpleBusUC(addrBits = VAddrBits)
28    val memMMU = Flipped(new MemMMUIO)
29    val frontend = Flipped(new FrontendToBackendIO)
30    val mem = Flipped(new MemToBackendIO)
31  })
32
33
34  val aluExeUnits = Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
35  val jmpExeUnit = Module(new JmpExeUnit)
36  val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit))
37  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
38  //  val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
39  //  val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
40  //  val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
41  val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits)
42  exeUnits.foreach(_.io.exception := DontCare)
43  exeUnits.foreach(_.io.dmem := DontCare)
44  exeUnits.foreach(_.io.mcommit := DontCare)
45
46  val decode = Module(new DecodeStage)
47  val brq = Module(new Brq)
48  val decBuf = Module(new DecodeBuffer)
49  val rename = Module(new Rename)
50  val dispatch = Module(new Dispatch(exeUnits.map(_.config)))
51  val roq = Module(new Roq)
52  val intRf = Module(new Regfile(
53    numReadPorts = NRIntReadPorts,
54    numWirtePorts = NRIntWritePorts,
55    hasZero = true
56  ))
57  val fpRf = Module(new Regfile(
58    numReadPorts = NRFpReadPorts,
59    numWirtePorts = NRFpWritePorts,
60    hasZero = false
61  ))
62  val memRf = Module(new Regfile(
63    numReadPorts = 2*exuParameters.StuCnt + exuParameters.LduCnt,
64    numWirtePorts = NRIntWritePorts,
65    hasZero = true,
66    isMemRf = true
67  ))
68
69  // backend redirect, flush pipeline
70  val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect)
71
72  io.frontend.redirect <> redirect
73
74
75
76  val memConfigs =
77    Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++
78    Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg)
79
80  val exuConfigs = exeUnits.map(_.config) ++ memConfigs
81
82  val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout
83
84  def needWakeup(cfg: ExuConfig): Boolean =
85    (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
86
87  def needData(a: ExuConfig, b: ExuConfig): Boolean =
88    (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
89
90  val reservedStations = exeUnits.
91    zipWithIndex.
92    map({ case (exu, i) =>
93
94      val cfg = exu.config
95
96      val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2)
97      val bypassCnt = exuConfigs.count(c => c.enableBypass && needData(cfg, c))
98
99      println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt")
100
101      val rs = Module(new ReservationStation(
102        cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, false
103      ))
104      rs.io.redirect <> redirect
105      rs.io.numExist <> dispatch.io.numExist(i)
106      rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
107      rs.io.enqData <> dispatch.io.enqIQData(i)
108      for(
109        (wakeUpPort, exuOut) <-
110        rs.io.wakeUpPorts.zip(wakeUpDateVec)
111      ){
112        wakeUpPort.bits := exuOut.bits
113        wakeUpPort.valid := exuOut.valid
114      }
115
116      exu.io.in <> rs.io.deq
117      exu.io.redirect <> redirect
118      rs
119    })
120
121  for( rs <- reservedStations){
122    rs.io.bypassUops <> reservedStations.
123      filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)).
124      map(_.io.selectedUop)
125
126    val bypassDataVec = exuConfigs.zip(exeWbReqs).
127      filter(x => x._1.enableBypass && needData(rs.exuCfg, x._1)).map(_._2)
128
129    for(i <- bypassDataVec.indices){
130      rs.io.bypassData(i).valid := bypassDataVec(i).valid
131      rs.io.bypassData(i).bits := bypassDataVec(i).bits
132    }
133  }
134
135  val issueQueues = exuConfigs.
136    zipWithIndex.
137    takeRight(exuParameters.LduCnt + exuParameters.StuCnt).
138    map({case (cfg, i) =>
139      val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2)
140      val bypassUopVec = reservedStations.filter(r => r.exuCfg.enableBypass && needData(cfg, r.exuCfg)).map(_.io.selectedUop)
141      val iq = Module(new IssueQueue(
142        cfg, wakeUpDateVec.length, bypassUopVec.length
143      ))
144      println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:${bypassUopVec.length}")
145      iq.io.redirect <> redirect
146      iq.io.enq <> dispatch.io.enqIQCtrl(i)
147      dispatch.io.numExist(i) := iq.io.numExist
148      for(
149        (wakeUpPort, exuOut) <-
150        iq.io.wakeUpPorts.zip(wakeUpDateVec)
151      ){
152        wakeUpPort.bits := exuOut.bits
153        wakeUpPort.valid := exuOut.valid
154      }
155      iq.io.bypassUops <> bypassUopVec
156      iq
157    })
158
159  io.mem.mcommit := roq.io.mcommit
160  io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
161  io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
162  jmpExeUnit.io.exception.valid := roq.io.redirect.valid
163  jmpExeUnit.io.exception.bits := roq.io.exception
164
165  io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo
166  io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo
167
168  decode.io.in <> io.frontend.cfVec
169  brq.io.roqRedirect <> roq.io.redirect
170  brq.io.bcommit := roq.io.bcommit
171  brq.io.enqReqs <> decode.io.toBrq
172  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
173    x.bits := y.io.out.bits
174    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
175  }
176  decode.io.brTags <> brq.io.brTags
177  decBuf.io.redirect <> redirect
178  decBuf.io.in <> decode.io.out
179
180  rename.io.redirect <> redirect
181  rename.io.roqCommits <> roq.io.commits
182  rename.io.in <> decBuf.io.out
183  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr
184  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
185  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr
186  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
187  dispatch.io.redirect <> redirect
188  dispatch.io.fromRename <> rename.io.out
189
190  roq.io.brqRedirect <> brq.io.redirect
191  roq.io.dp1Req <> dispatch.io.toRoq
192  dispatch.io.roqIdxs <> roq.io.roqIdxs
193  io.mem.dp1Req <> dispatch.io.toMoq
194  dispatch.io.moqIdxs <> io.mem.moqIdxs
195
196  intRf.io.readPorts <> dispatch.io.readIntRf
197  fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf)
198  memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf)
199
200  val wbIntIdx = exuConfigs.zipWithIndex.filter(_._1.writeIntRf).map(_._2)
201  val wbFpIdx = exuConfigs.zipWithIndex.filter(_._1.writeFpRf).map(_._2)
202
203  val wbu = Module(new Wbu(wbIntIdx, wbFpIdx))
204  wbu.io.in <> exeWbReqs
205
206  val wbIntResults = wbu.io.toIntRf
207  val wbFpResults = wbu.io.toFpRf
208
209  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
210    val rfWrite = Wire(new RfWritePort)
211    rfWrite.wen := x.valid
212    rfWrite.addr := x.bits.uop.pdest
213    rfWrite.data := x.bits.data
214    rfWrite
215  }
216  val intRfWrite = wbIntResults.map(exuOutToRfWrite)
217  intRf.io.writePorts <> intRfWrite
218  memRf.io.writePorts <> intRfWrite
219  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
220
221  rename.io.wbIntResults <> wbIntResults
222  rename.io.wbFpResults <> wbFpResults
223
224  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
225  roq.io.exeWbResults.last := brq.io.out
226
227
228  // TODO: Remove sink and source
229  val tmp = WireInit(0.U)
230  val sinks = Array[String](
231    "DTLBFINISH",
232    "DTLBPF",
233    "DTLBENABLE",
234    "perfCntCondMdcacheLoss",
235    "perfCntCondMl2cacheLoss",
236    "perfCntCondMdcacheHit",
237    "lsuMMIO",
238    "perfCntCondMl2cacheHit",
239    "perfCntCondMl2cacheReq",
240    "mtip",
241    "perfCntCondMdcacheReq",
242    "meip"
243  )
244  for (s <- sinks) {
245    BoringUtils.addSink(tmp, s)
246  }
247
248  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
249  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
250  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
251  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
252  if (!p.FPGAPlatform) {
253    BoringUtils.addSource(debugArchReg, "difftestRegs")
254  }
255
256}
257