xref: /XiangShan/src/main/scala/xiangshan/backend/Backend.scala (revision 250b716d56ca232a7bd7487a9b89a67dacb0eb31) 
1package xiangshan.backend
2
3import bus.simplebus.SimpleBusUC
4import chisel3._
5import chisel3.util._
6import chisel3.util.experimental.BoringUtils
7import noop.MemMMUIO
8import xiangshan._
9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage}
10import xiangshan.backend.rename.Rename
11import xiangshan.backend.brq.Brq
12import xiangshan.backend.dispatch.Dispatch
13import xiangshan.backend.exu._
14import xiangshan.backend.fu.FunctionUnit
15import xiangshan.backend.issue.{IssueQueue, ReservationStation}
16import xiangshan.backend.regfile.{Regfile, RfWritePort}
17import xiangshan.backend.roq.Roq
18import xiangshan.mem._
19
20
21/** Backend Pipeline:
22  * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
23  */
24class Backend(implicit val p: XSConfig) extends XSModule
25  with NeedImpl {
26  val io = IO(new Bundle {
27    // val dmem = new SimpleBusUC(addrBits = VAddrBits)
28    val memMMU = Flipped(new MemMMUIO)
29    val frontend = Flipped(new FrontendToBackendIO)
30    val mem = Flipped(new MemToBackendIO)
31  })
32
33
34  val aluExeUnits = Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
35  val jmpExeUnit = Module(new JmpExeUnit)
36  val mulExeUnits = Array.tabulate(exuParameters.MulCnt)(_ => Module(new MulExeUnit))
37  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
38  //  val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
39  //  val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
40  //  val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
41  val exeUnits = jmpExeUnit +: (aluExeUnits ++ mulExeUnits ++ mduExeUnits)
42  exeUnits.foreach(_.io.exception := DontCare)
43  exeUnits.foreach(_.io.dmem := DontCare)
44  exeUnits.foreach(_.io.mcommit := DontCare)
45
46  val decode = Module(new DecodeStage)
47  val brq = Module(new Brq)
48  val decBuf = Module(new DecodeBuffer)
49  val rename = Module(new Rename)
50  val dispatch = Module(new Dispatch())
51  val roq = Module(new Roq)
52  val intRf = Module(new Regfile(
53    numReadPorts = NRIntReadPorts,
54    numWirtePorts = NRIntWritePorts,
55    hasZero = true
56  ))
57  val fpRf = Module(new Regfile(
58    numReadPorts = NRFpReadPorts,
59    numWirtePorts = NRFpWritePorts,
60    hasZero = false
61  ))
62  val memRf = Module(new Regfile(
63    numReadPorts = 2*exuParameters.StuCnt + exuParameters.LduCnt,
64    numWirtePorts = NRIntWritePorts,
65    hasZero = true,
66    isMemRf = true
67  ))
68
69  // backend redirect, flush pipeline
70  val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect)
71
72  val redirectInfo = Wire(new RedirectInfo)
73  // exception or misprediction
74  redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid
75  redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid
76  redirectInfo.redirect := redirect.bits
77
78
79
80  val memConfigs =
81    Seq.fill(exuParameters.LduCnt)(Exu.ldExeUnitCfg) ++
82    Seq.fill(exuParameters.StuCnt)(Exu.stExeUnitCfg)
83
84  val exuConfigs = exeUnits.map(_.config) ++ memConfigs
85
86  val exeWbReqs = exeUnits.map(_.io.out) ++ io.mem.ldout ++ io.mem.stout
87
88  def needWakeup(cfg: ExuConfig): Boolean =
89    (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf)
90
91  def needData(a: ExuConfig, b: ExuConfig): Boolean =
92    (a.readIntRf && b.writeIntRf) || (a.readFpRf && b.writeFpRf)
93
94  val reservedStations = exeUnits.
95    zipWithIndex.
96    map({ case (exu, i) =>
97
98      val cfg = exu.config
99
100      val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2)
101      val bypassCnt = exuConfigs.count(c => c.enableBypass && needData(cfg, c))
102
103      println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:$bypassCnt")
104
105      val rs = Module(new ReservationStation(
106        cfg, wakeUpDateVec.length, bypassCnt, cfg.enableBypass, false
107      ))
108      rs.io.redirect <> redirect
109      rs.io.numExist <> dispatch.io.numExist(i)
110      rs.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
111      rs.io.enqData <> dispatch.io.enqIQData(i)
112      for(
113        (wakeUpPort, exuOut) <-
114        rs.io.wakeUpPorts.zip(wakeUpDateVec)
115      ){
116        wakeUpPort.bits := exuOut.bits
117        wakeUpPort.valid := exuOut.valid
118      }
119
120      exu.io.in <> rs.io.deq
121      exu.io.redirect <> redirect
122      rs
123    })
124
125  for( rs <- reservedStations){
126    rs.io.bypassUops <> reservedStations.
127      filter(x => x.enableBypass && needData(rs.exuCfg, x.exuCfg)).
128      map(_.io.selectedUop)
129
130    val bypassDataVec = exuConfigs.zip(exeWbReqs).
131      filter(x => x._1.enableBypass && needData(rs.exuCfg, x._1)).map(_._2)
132
133    for(i <- bypassDataVec.indices){
134      rs.io.bypassData(i).valid := bypassDataVec(i).valid
135      rs.io.bypassData(i).bits := bypassDataVec(i).bits
136    }
137  }
138
139  val issueQueues = exuConfigs.
140    zipWithIndex.
141    takeRight(exuParameters.LduCnt + exuParameters.StuCnt).
142    map({case (cfg, i) =>
143      val wakeUpDateVec = exuConfigs.zip(exeWbReqs).filter(x => needData(cfg, x._1)).map(_._2)
144      val bypassUopVec = reservedStations.filter(r => r.exuCfg.enableBypass && needData(cfg, r.exuCfg)).map(_.io.selectedUop)
145      val iq = Module(new IssueQueue(
146        cfg, wakeUpDateVec.length, bypassUopVec.length
147      ))
148      println(s"exu:${cfg.name} wakeupCnt:${wakeUpDateVec.length} bypassCnt:${bypassUopVec.length}")
149      iq.io.redirect <> redirect
150      iq.io.enq <> dispatch.io.enqIQCtrl(i)
151      dispatch.io.numExist(i) := iq.io.numExist
152      for(
153        (wakeUpPort, exuOut) <-
154        iq.io.wakeUpPorts.zip(wakeUpDateVec)
155      ){
156        wakeUpPort.bits := exuOut.bits
157        wakeUpPort.valid := exuOut.valid
158      }
159      iq.io.bypassUops <> bypassUopVec
160      iq
161    })
162
163  io.mem.mcommit := roq.io.mcommit
164  io.mem.ldin <> issueQueues.filter(_.exuCfg == Exu.ldExeUnitCfg).map(_.io.deq)
165  io.mem.stin <> issueQueues.filter(_.exuCfg == Exu.stExeUnitCfg).map(_.io.deq)
166  jmpExeUnit.io.exception.valid := roq.io.redirect.valid
167  jmpExeUnit.io.exception.bits := roq.io.exception
168
169  io.frontend.redirectInfo <> redirectInfo
170  io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo
171
172  decode.io.in <> io.frontend.cfVec
173  brq.io.roqRedirect <> roq.io.redirect
174  brq.io.bcommit := roq.io.bcommit
175  brq.io.enqReqs <> decode.io.toBrq
176  for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) {
177    x.bits := y.io.out.bits
178    x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
179  }
180  decode.io.brTags <> brq.io.brTags
181  decBuf.io.redirect <> redirect
182  decBuf.io.in <> decode.io.out
183
184  rename.io.redirect <> redirect
185  rename.io.roqCommits <> roq.io.commits
186  rename.io.in <> decBuf.io.out
187  rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) ++ dispatch.io.intMemRegAddr
188  rename.io.intPregRdy <> dispatch.io.intPregRdy ++ dispatch.io.intMemRegRdy
189  rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) ++ dispatch.io.fpMemRegAddr
190  rename.io.fpPregRdy <> dispatch.io.fpPregRdy ++ dispatch.io.fpMemRegRdy
191  dispatch.io.redirect <> redirect
192  dispatch.io.fromRename <> rename.io.out
193
194  roq.io.brqRedirect <> brq.io.redirect
195  roq.io.dp1Req <> dispatch.io.toRoq
196  dispatch.io.roqIdxs <> roq.io.roqIdxs
197  io.mem.dp1Req <> dispatch.io.toMoq
198  dispatch.io.moqIdxs <> io.mem.moqIdxs
199
200  intRf.io.readPorts <> dispatch.io.readIntRf
201  fpRf.io.readPorts <> dispatch.io.readFpRf ++ issueQueues.flatMap(_.io.readFpRf)
202  memRf.io.readPorts <> issueQueues.flatMap(_.io.readIntRf)
203
204  val wbIntIdx = exuConfigs.zipWithIndex.filter(_._1.writeIntRf).map(_._2)
205  val wbFpIdx = exuConfigs.zipWithIndex.filter(_._1.writeFpRf).map(_._2)
206
207  val wbu = Module(new Wbu(wbIntIdx, wbFpIdx))
208  wbu.io.in <> exeWbReqs
209
210  val wbIntResults = wbu.io.toIntRf
211  val wbFpResults = wbu.io.toFpRf
212
213  def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = {
214    val rfWrite = Wire(new RfWritePort)
215    rfWrite.wen := x.valid
216    rfWrite.addr := x.bits.uop.pdest
217    rfWrite.data := x.bits.data
218    rfWrite
219  }
220  val intRfWrite = wbIntResults.map(exuOutToRfWrite)
221  intRf.io.writePorts <> intRfWrite
222  memRf.io.writePorts <> intRfWrite
223  fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite)
224
225  rename.io.wbIntResults <> wbIntResults
226  rename.io.wbFpResults <> wbFpResults
227
228  roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2)
229  roq.io.exeWbResults.last := brq.io.out
230
231
232  // TODO: Remove sink and source
233  val tmp = WireInit(0.U)
234  val sinks = Array[String](
235    "DTLBFINISH",
236    "DTLBPF",
237    "DTLBENABLE",
238    "perfCntCondMdcacheLoss",
239    "perfCntCondMl2cacheLoss",
240    "perfCntCondMdcacheHit",
241    "lsuMMIO",
242    "perfCntCondMl2cacheHit",
243    "perfCntCondMl2cacheReq",
244    "mtip",
245    "perfCntCondMdcacheReq",
246    "meip"
247  )
248  for (s <- sinks) {
249    BoringUtils.addSink(tmp, s)
250  }
251
252  val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
253  BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG")
254  BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG")
255  val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
256  if (!p.FPGAPlatform) {
257    BoringUtils.addSource(debugArchReg, "difftestRegs")
258  }
259
260}
261