xref: /XiangShan/src/main/scala/xiangshan/XSCore.scala (revision b9fd18920ff32da90dcdccd2b29c490bab87f0eb) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7import xiangshan.backend._
8import xiangshan.backend.dispatch.DP1Parameters
9import xiangshan.backend.exu.ExuParameters
10import xiangshan.frontend.Frontend
11import utils._
12
13trait HasXSParameter {
14  val XLEN = 64
15  val HasMExtension = true
16  val HasCExtension = true
17  val HasDiv = true
18  val HasIcache = true
19  val HasDcache = true
20  val EnableStoreQueue = false
21  val AddrBits = 64 // AddrBits is used in some cases
22  val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
23  val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
24  val AddrBytes = AddrBits / 8 // unused
25  val DataBits = XLEN
26  val DataBytes = DataBits / 8
27  val HasFPU = true
28  val FetchWidth = 8
29  val IBufSize = 64
30  val DecodeWidth = 6
31  val RenameWidth = 6
32  val CommitWidth = 6
33  val BrqSize = 16
34  val IssQueSize = 8
35  val BrTagWidth = log2Up(BrqSize)
36  val NRPhyRegs = 128
37  val PhyRegIdxWidth = log2Up(NRPhyRegs)
38  val NRReadPorts = 14
39  val NRWritePorts = 8
40  val RoqSize = 32
41  val InnerRoqIdxWidth = log2Up(RoqSize)
42  val RoqIdxWidth = InnerRoqIdxWidth + 1
43  val IntDqDeqWidth = 4
44  val FpDqDeqWidth = 4
45  val LsDqDeqWidth = 4
46  val dp1Paremeters = DP1Parameters(
47    IntDqSize = 16,
48    FpDqSize = 16,
49    LsDqSize = 16
50  )
51  val exuParameters = ExuParameters(
52    JmpCnt = 1,
53    AluCnt = 4,
54    MulCnt = 1,
55    MduCnt = 1,
56    FmacCnt = 0,
57    FmiscCnt = 0,
58    FmiscDivSqrtCnt = 0,
59    LduCnt = 0,
60    StuCnt = 1
61  )
62}
63
64trait HasXSLog { this: Module =>
65  implicit val moduleName: String = this.name
66}
67
68abstract class XSModule extends Module
69  with HasXSParameter
70  with HasExceptionNO
71  with HasXSLog
72
73//remove this trait after impl module logic
74trait NeedImpl { this: Module =>
75  override protected def IO[T <: Data](iodef: T): T = {
76    val io = chisel3.experimental.IO(iodef)
77    io <> DontCare
78    io
79  }
80}
81
82abstract class XSBundle extends Bundle
83  with HasXSParameter
84
85case class XSConfig
86(
87  FPGAPlatform: Boolean = true,
88  EnableDebug: Boolean = true
89)
90
91object AddressSpace extends HasXSParameter {
92  // (start, size)
93  // address out of MMIO will be considered as DRAM
94  def mmio = List(
95    (0x30000000L, 0x10000000L),  // internal devices, such as CLINT and PLIC
96    (0x40000000L, 0x40000000L) // external devices
97  )
98
99  def isMMIO(addr: UInt): Bool = mmio.map(range => {
100    require(isPow2(range._2))
101    val bits = log2Up(range._2)
102    (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U
103  }).reduce(_ || _)
104}
105
106
107class XSCore(implicit p: XSConfig) extends XSModule {
108  val io = IO(new Bundle {
109    val imem = new SimpleBusC
110    val dmem = new SimpleBusC
111    val mmio = new SimpleBusUC
112    val frontend = Flipped(new SimpleBusUC())
113  })
114
115  io.imem <> DontCare
116
117  val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
118
119  val front = Module(new Frontend)
120  val backend = Module(new Backend)
121
122  front.io.backend <> backend.io.frontend
123
124  backend.io.memMMU.imem <> DontCare
125
126  val dtlb = TLB(
127    in = backend.io.dmem,
128    mem = dmemXbar.io.in(1),
129    flush = false.B,
130    csrMMU = backend.io.memMMU.dmem
131  )(TLBConfig(name = "dtlb", totalEntry = 64))
132  dmemXbar.io.in(0) <> dtlb.io.out
133  dmemXbar.io.in(2) <> io.frontend
134
135  io.dmem <> Cache(
136    in = dmemXbar.io.out,
137    mmio = Seq(io.mmio),
138    flush = "b00".U,
139    empty = dtlb.io.cacheEmpty,
140    enable = HasDcache
141  )(CacheConfig(name = "dcache"))
142
143  XSDebug("(req valid, ready | resp valid, ready) \n")
144  XSDebug("c-mem(%x %x %x| %x %x) c-coh(%x %x %x| %x %x) cache (%x %x %x| %x %x) tlb (%x %x %x| %x %x)\n",
145    io.dmem.mem.req.valid,
146    io.dmem.mem.req.ready,
147    io.dmem.mem.req.bits.addr,
148    io.dmem.mem.resp.valid,
149    io.dmem.mem.resp.ready,
150    io.dmem.coh.req.valid,
151    io.dmem.coh.req.ready,
152    io.dmem.coh.req.bits.addr,
153    io.dmem.coh.resp.valid,
154    io.dmem.coh.resp.ready,
155    dmemXbar.io.out.req.valid,
156    dmemXbar.io.out.req.ready,
157    dmemXbar.io.out.req.bits.addr,
158    dmemXbar.io.out.resp.valid,
159    dmemXbar.io.out.resp.ready,
160    backend.io.dmem.req.valid,
161    backend.io.dmem.req.ready,
162    backend.io.dmem.req.bits.addr,
163    backend.io.dmem.resp.valid,
164    backend.io.dmem.resp.ready
165  )
166}
167