1package xiangshan.backend 2 3import bus.simplebus.SimpleBusUC 4import chisel3._ 5import chisel3.util._ 6import chisel3.util.experimental.BoringUtils 7import noop.MemMMUIO 8import xiangshan._ 9import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 10import xiangshan.backend.rename.Rename 11import xiangshan.backend.brq.Brq 12import xiangshan.backend.dispatch.Dispatch 13import xiangshan.backend.exu._ 14import xiangshan.backend.fu.FunctionUnit 15import xiangshan.backend.issue.IssueQueue 16import xiangshan.backend.regfile.{Regfile, RfWritePort} 17import xiangshan.backend.roq.Roq 18 19 20/** Backend Pipeline: 21 * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe 22 */ 23class Backend(implicit val p: XSConfig) extends XSModule 24 with HasExeUnits 25 with NeedImpl { 26 val io = IO(new Bundle { 27 val dmem = new SimpleBusUC(addrBits = VAddrBits) 28 val memMMU = Flipped(new MemMMUIO) 29 val frontend = Flipped(new FrontendToBackendIO) 30 }) 31 32 33 val decode = Module(new DecodeStage) 34 val brq = Module(new Brq) 35 val decBuf = Module(new DecodeBuffer) 36 val rename = Module(new Rename) 37 val dispatch = Module(new Dispatch) 38 val roq = Module(new Roq) 39 val intRf = Module(new Regfile( 40 numReadPorts = NRReadPorts, 41 numWirtePorts = NRWritePorts, 42 hasZero = true 43 )) 44 val fpRf = Module(new Regfile( 45 numReadPorts = NRReadPorts, 46 numWirtePorts = NRWritePorts, 47 hasZero = false 48 )) 49 50 // backend redirect, flush pipeline 51 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect, brq.io.redirect) 52 53 val redirectInfo = Wire(new RedirectInfo) 54 // exception or misprediction 55 redirectInfo.valid := roq.io.redirect.valid || brq.io.out.valid 56 redirectInfo.misPred := !roq.io.redirect.valid && brq.io.redirect.valid 57 redirectInfo.redirect := redirect.bits 58 59 val issueQueues = exeUnits.zipWithIndex.map({ case (eu, i) => 60 def needBypass(cfg: ExuConfig): Boolean = cfg.enableBypass 61 62 val bypassCnt = if(eu.config.enableBypass) exeUnits.map(_.config).count(needBypass) else 0 63 def needWakeup(cfg: ExuConfig): Boolean = 64 (cfg.readIntRf && cfg.writeIntRf) || (cfg.readFpRf && cfg.writeFpRf) 65 66 val wakeupCnt = exeUnits.map(_.config).count(needWakeup) 67 assert(!(needBypass(eu.config) && !needWakeup(eu.config))) // needBypass but dont needWakeup is not allowed 68 val iq = Module(new IssueQueue( 69 eu.config, 70 wakeupCnt, 71 bypassCnt, 72 fifo = eu.config.supportedFuncUnits.contains(FunctionUnit.lsuCfg) 73 )) 74 iq.io.redirect <> redirect 75 iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i) 76 iq.io.enqData <> dispatch.io.enqIQData(i) 77 val wuUnitsOut = exeUnits.filter(e => needWakeup(e.config)).map(_.io.out) 78 for (i <- iq.io.wakeUpPorts.indices) { 79 iq.io.wakeUpPorts(i).bits <> wuUnitsOut(i).bits 80 iq.io.wakeUpPorts(i).valid := wuUnitsOut(i).valid 81 } 82 println( 83 s"[$i] ${eu.name} Queue wakeupCnt:$wakeupCnt bypassCnt:$bypassCnt" + 84 s" Supported Function:[" + 85 s"${ 86 eu.config.supportedFuncUnits.map( 87 fu => FuType.functionNameMap(fu.fuType.litValue())).mkString(", " 88 ) 89 }]" 90 ) 91 eu.io.in <> iq.io.deq 92 eu.io.redirect <> redirect 93 iq 94 }) 95 96 val bypassQueues = issueQueues.filter(_.bypassCnt > 0) 97 val bypassUnits = exeUnits.filter(_.config.enableBypass) 98 bypassQueues.foreach(iq => { 99 for (i <- iq.io.bypassUops.indices) { 100 iq.io.bypassData(i).bits := bypassUnits(i).io.out.bits 101 iq.io.bypassData(i).valid := bypassUnits(i).io.out.valid 102 } 103 iq.io.bypassUops <> bypassQueues.map(_.io.selectedUop) 104 }) 105 106 lsuExeUnits.foreach(_.io.dmem <> io.dmem) 107 lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit) 108 109 io.frontend.redirectInfo <> redirectInfo 110 io.frontend.commits <> roq.io.commits 111 112 decode.io.in <> io.frontend.cfVec 113 brq.io.roqRedirect <> roq.io.redirect 114 brq.io.enqReqs <> decode.io.toBrq 115 for ((x, y) <- brq.io.exuRedirect.zip(exeUnits.filter(_.config.hasRedirect))) { 116 x.bits := y.io.out.bits 117 x.valid := y.io.out.fire() && y.io.out.bits.redirectValid 118 } 119 decode.io.brTags <> brq.io.brTags 120 decBuf.io.redirect <> redirect 121 decBuf.io.in <> decode.io.out 122 123 rename.io.redirect <> redirect 124 rename.io.roqCommits <> roq.io.commits 125 rename.io.in <> decBuf.io.out 126 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 127 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 128 rename.io.intPregRdy <> dispatch.io.intPregRdy 129 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 130 131 dispatch.io.redirect <> redirect 132 dispatch.io.fromRename <> rename.io.out 133 134 roq.io.brqRedirect <> brq.io.redirect 135 roq.io.dp1Req <> dispatch.io.toRoq 136 dispatch.io.roqIdxs <> roq.io.roqIdxs 137 138 intRf.io.readPorts <> dispatch.io.readIntRf 139 fpRf.io.readPorts <> dispatch.io.readFpRf 140 141 val exeWbReqs = exeUnits.map(_.io.out) 142 143 val wbIntIdx = exeUnits.zipWithIndex.filter(_._1.config.writeIntRf).map(_._2) 144 val wbFpIdx = exeUnits.zipWithIndex.filter(_._1.config.writeFpRf).map(_._2) 145 146 val wbu = Module(new Wbu(wbIntIdx, wbFpIdx)) 147 wbu.io.in <> exeWbReqs 148 149 val wbIntResults = wbu.io.toIntRf 150 val wbFpResults = wbu.io.toFpRf 151 152 def exuOutToRfWrite(x: Valid[ExuOutput]): RfWritePort = { 153 val rfWrite = Wire(new RfWritePort) 154 rfWrite.wen := x.valid 155 rfWrite.addr := x.bits.uop.pdest 156 rfWrite.data := x.bits.data 157 rfWrite 158 } 159 160 intRf.io.writePorts <> wbIntResults.map(exuOutToRfWrite) 161 fpRf.io.writePorts <> wbFpResults.map(exuOutToRfWrite) 162 163 rename.io.wbIntResults <> wbIntResults 164 rename.io.wbFpResults <> wbFpResults 165 166 roq.io.exeWbResults.take(exeWbReqs.length).zip(wbu.io.toRoq).foreach(x => x._1 := x._2) 167 roq.io.exeWbResults.last := brq.io.out 168 169 170 // TODO: Remove sink and source 171 val tmp = WireInit(0.U) 172 val sinks = Array[String]( 173 "DTLBFINISH", 174 "DTLBPF", 175 "DTLBENABLE", 176 "perfCntCondMdcacheLoss", 177 "perfCntCondMl2cacheLoss", 178 "perfCntCondMdcacheHit", 179 "lsuMMIO", 180 "perfCntCondMl2cacheHit", 181 "perfCntCondMl2cacheReq", 182 "mtip", 183 "perfCntCondMdcacheReq", 184 "meip" 185 ) 186 for (s <- sinks) { 187 BoringUtils.addSink(tmp, s) 188 } 189 190 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 191 BoringUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG") 192 BoringUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG") 193 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 194 if (!p.FPGAPlatform) { 195 BoringUtils.addSource(debugArchReg, "difftestRegs") 196 } 197 198} 199