xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala (revision c7cacdf5f5f745af067b0644c417a196d5ed0f8e) 
1package xiangshan.backend.fu
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import xiangshan.utils._
7import xiangshan.backend._
8import xiangshan.backend.fu.FunctionUnit._
9
10class Jump extends FunctionUnit(jmpCfg){
11  val io = IO(new ExuIO)
12
13  override def toString: String = "Bru"
14
15  val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop)
16
17  val redirectHit = uop.brTag.needFlush(io.redirect)
18  val valid = iovalid && !redirectHit
19
20  val isCSR = BRUOpType.isCSR(func)
21  val isFMV = BRUOpType.isFMV(func)
22  val isMOU = BRUOpType.isMOU(func)
23  val isJUMP = BRUOpType.isJUMP(func)
24
25  // JUMP
26  val isRVC = uop.cf.isRVC
27  val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U)
28  val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
29
30  io.out.bits.redirectValid := valid && isJUMP
31  io.out.bits.redirect.target := target
32  io.out.bits.redirect.brTag := uop.brTag
33  io.out.bits.redirect.isException := false.B
34  io.out.bits.redirect.roqIdx := uop.roqIdx
35  io.out.bits.redirect.freelistAllocPtr := uop.freelistAllocPtr
36
37  // Output
38  val resCSR = WireInit(0.U(XLEN.W)) // TODO: implement it
39  val resFMV = WireInit(0.U(XLEN.W)) // TODO: implement it
40  val resMOU = WireInit(0.U(XLEN.W)) // TODO: implement it
41  val resJMP = pcDelaySlot
42  val res = ParallelMux(
43    VecInit(isCSR,  isFMV,  isMOU,  isJUMP) zip
44      VecInit(resCSR, resFMV, resMOU, resJMP)
45  )
46
47  io.in.ready := io.out.ready
48  io.out.valid := valid // TODO: CSR/MOU/FMV may need change it
49  io.out.bits.uop <> io.in.bits.uop
50  io.out.bits.data := res
51
52  // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
53  XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x\n",
54    io.in.valid, io.in.ready, io.out.valid, io.out.ready, io.redirect.valid, io.redirect.bits.isException, redirectHit, io.redirect.bits.brTag.value)
55  XSDebug(io.in.valid && isCSR, "src1:%x offset:%x func:%b type:CSR pc:%x\n", src1, offset, func, pc)
56  XSDebug(io.in.valid && isFMV, "src1:%x offset:%x func:%b type:FMV pc:%x\n", src1, offset, func, pc)
57  XSDebug(io.in.valid && isMOU, "src1:%x offset:%x func:%b type:MOU pc:%x\n", src1, offset, func, pc)
58  XSDebug(io.in.valid && isJUMP, "src1:%x offset:%x func:%b type:JUMP pc:%x\n", src1, offset, func, pc)
59  XSDebug(io.in.valid, "Res:%x` CsrRes:%x FMV:%x Mou:%x Jmp:%x\n", res, resCSR, resFMV, resMOU, resJMP)
60}
61