| /nrf52832-nimble/nordic/nrfx/drivers/include/ |
| H A D | nrfx_ppi.h | 39 * @defgroup nrfx_ppi PPI allocator
42 * @brief Programmable Peripheral Interconnect (PPI) allocator.
58 …NELS_MASK ((uint32_t)0xFFFFFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available …
59 …K ((uint32_t)0x000FFFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available …
61 …NELS_MASK ((uint32_t)0xFFF0FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< All PPI channels available …
62 …K ((uint32_t)0x0000FFFFuL & ~(NRFX_PPI_CHANNELS_USED)) /**< Programmable PPI channels available …
65 …K (((1uL << PPI_GROUP_NUM) - 1) & ~(NRFX_PPI_GROUPS_USED)) /**< All PPI groups available to…
68 * @brief Function for uninitializing the PPI module.
75 * @brief Function for allocating a PPI channel.
76 * @details This function allocates the first unused PPI channel.
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| H A D | nrfx_spim.h | 270 * flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use
280 * up a number of transfers that will be triggered externally (for example by PPI). An example is
283 * transfer is set up, a set of transfers can be triggered by PPI that will read, for example,
347 … In that case, the transfer is not started by the driver, but it must be started externally by PPI.
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| H A D | nrfx_twim.h | 318 …ing the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by …
320 …sfers. You can set up a number of transfers that will be triggered externally (for example by PPI).
322 …* After the transfer is set up, a set of transfers can be triggered by PPI that will read, for e…
373 … In that case, the transfer is not started by the driver, but it must be started externally by PPI.
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| H A D | nrfx_pwm.h | 239 * triggering a task (using PPI for instance). The function will then return
266 * triggering a task (using PPI for instance). The function will then return
397 * be used in PPI module.
408 * be used in PPI module.
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| H A D | nrfx_rtc.h | 284 …* This function asserts if the output pointer is NULL. The task address can be used by the PPI mod…
296 …* This function asserts if the output pointer is NULL. The event address can be used by the PPI mo…
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| H A D | nrfx_gpiote.h | 209 * @details The output pin can be controlled by the CPU or by PPI. The initial
210 * configuration specifies which mode is used. If PPI mode is used, the driver
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| H A D | nrfx_adc.h | 229 * nrfx_adc_sample function or by PPI using the @ref NRF_ADC_TASK_START task.
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| H A D | nrfx_saadc.h | 247 * the SAMPLE task. It can be triggered manually by the @ref nrfx_saadc_sample function or by PPI
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| H A D | nrfx_timer.h | 258 * Use this function to read channel values when PPI is used for capturing.
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| /nrf52832-nimble/nordic/nrfx/hal/ |
| H A D | nrf_ppi.h | 42 * @defgroup nrf_ppi_hal PPI HAL
45 * @brief Hardware access layer for managing the Programmable Peripheral Interconnect (PPI)
53 * @brief PPI channels.
95 * @brief PPI channel groups.
111 * @brief Definition of which PPI channels belong to a group.
121 * @brief Definition if a PPI channel is enabled.
131 * @brief PPI tasks.
154 * @brief Function for enabling a given PPI channel.
164 * @brief Function for disabling a given PPI channel.
173 * @brief Function for checking if a given PPI channel is enabled.
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| H A D | nrf_rng.h | 114 * This function can be used by the PPI module.
130 * This function can be used by the PPI module.
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| H A D | nrf_clock.h | 206 * @details This function can be used by the PPI module.
223 * @details This function can be used by the PPI module.
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| /nrf52832-nimble/nordic/nrfx/mdk/ |
| H A D | nrf51_to_nrf52810.h | 145 /* PPI */
146 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
156 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
190 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
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| H A D | nrf51_to_nrf52840.h | 191 /* PPI */
192 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
202 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
236 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
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| H A D | nrf51_deprecated.h | 131 /* PPI */
132 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
141 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
174 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
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| H A D | nrf51_to_nrf52.h | 576 /* PPI */
577 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
587 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
621 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
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| H A D | nrf51_bitfields.h | 2406 /* Bit 31 : PPI region configuration. */
2407 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
2408 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
3260 /* Peripheral: PPI */
3261 /* Description: PPI controller. */
3266 /* Bit 31 : Enable PPI channel 31. */
3272 /* Bit 30 : Enable PPI channel 30. */
3278 /* Bit 29 : Enable PPI channel 29. */
3284 /* Bit 28 : Enable PPI channel 28. */
3290 /* Bit 27 : Enable PPI channel 27. */
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| H A D | nrf51.svd | 1631 <name>PPI</name>
1632 <description>PPI region configuration.</description>
9286 <description>Configures event enable routing to PPI for each RTC event.</description>
9395 …<description>Enable events routing to PPI. The reading of this register gives the value of EVTEN.<…
9400 <description>Enable routing to PPI of TICK event.</description>
9426 <description>Enable routing to PPI of OVRFLW event.</description>
9452 <description>Enable routing to PPI of COMPARE[0] event.</description>
9478 <description>Enable routing to PPI of COMPARE[1] event.</description>
9504 <description>Enable routing to PPI of COMPARE[2] event.</description>
9530 <description>Enable routing to PPI of COMPARE[3] event.</description>
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| H A D | nrf51.h | 181 * @brief PPI_CH [CH] (PPI Channel.)
719 … EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each
721 …__IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. Th…
723 …__IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. T…
1071 /* ================ PPI …
1076 * @brief PPI controller. (PPI)
1079 typedef struct { /*!< (@ 0x4001F000) PPI Structure …
1086 …__IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. …
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| /nrf52832-nimble/nordic/nrfx/ |
| H A D | CHANGELOG.md | 58 - Added functions for modifying only the event endpoint or only the task endpoint in the PPI HAL.
73 - Extended HALs for GPIO, PPI, SAADC, and USBD.
81 - Fixed logging in the PPI driver.
103 - Corrected assertions in the TIMER driver to make it usable in debug version with PPI.
138 - HAL for: ADC, CLOCK, COMP, ECB, EGU, GPIO, GPIOTE, I2S, LPCOMP, NVMC, PDM, POWER, PPI, PWM, QDEC,…
140 - Allocators for: PPI, SWI/EGU.
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| /nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/nrf52/src/ |
| H A D | ble_phy.c | 42 * NOTE: This code uses a couple of PPI channels so care should be taken when
43 * using PPI somewhere else.
568 /* Enable PPI */ in ble_phy_set_start_time()
603 /* Enable PPI */ in ble_phy_set_start_now()
621 * Function is used to set PPI so that we can time out waiting for a reception
692 /* Enable wait for response PPI */ in ble_phy_wfr_enable()
1013 * same as the limit when we need to have TX scheduled (i.e. TIMER0 and PPI in ble_phy_rx_end_isr()
1304 /* CH[20] and PPI CH[21] are on to trigger TASKS_TXEN or TASKS_RXEN */ in ble_phy_dbg_time_setup()
1430 * PPI setup. in ble_phy_init()
1503 /* PPI to start radio automatically shall be set here */ in ble_phy_rx()
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| /nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/nrf51/src/ |
| H A D | ble_phy.c | 374 /* Enable PPI */ in ble_phy_set_start_time()
384 * Function is used to set PPI so that we can time out waiting for a reception
422 /* Enable wait for response PPI */ in ble_phy_wfr_enable()
893 * PPI setup. in ble_phy_init()
1057 /* Enable PPI to automatically start TXEN */ in ble_phy_tx_set_start_time()
1097 /* Enable PPI to automatically start RXEN */ in ble_phy_rx_set_start_time()
1124 * XXX: Although we may not have to do this here, I clear all the PPI in ble_phy_tx()
1360 * ble phy disable irq and ppi
1392 * PPI and sets state to idle.
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| /nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/nrf52/ |
| H A D | syscfg.yml | 38 to high state when radio is enabled using PPI channels
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| /nrf52832-nimble/nordic/nrfx/templates/ |
| H A D | nrfx_glue.h | 255 * @brief Bitmask defining PPI channels reserved to be used outside of nrfx.
260 * @brief Bitmask defining PPI groups reserved to be used outside of nrfx.
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| /nrf52832-nimble/nordic/nrfx/drivers/src/ |
| H A D | nrfx_pwm.c | 50 // a playback is started via PPI, a specific EGU instance is used to generate
251 // it is not safe to do it directly via PPI. in start_playback()
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