1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRF_PPI_H__
33*150812a8SEvalZero #define NRF_PPI_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero
37*150812a8SEvalZero #ifdef __cplusplus
38*150812a8SEvalZero extern "C" {
39*150812a8SEvalZero #endif
40*150812a8SEvalZero
41*150812a8SEvalZero /**
42*150812a8SEvalZero * @defgroup nrf_ppi_hal PPI HAL
43*150812a8SEvalZero * @{
44*150812a8SEvalZero * @ingroup nrf_ppi
45*150812a8SEvalZero * @brief Hardware access layer for managing the Programmable Peripheral Interconnect (PPI)
46*150812a8SEvalZero * channels.
47*150812a8SEvalZero */
48*150812a8SEvalZero
49*150812a8SEvalZero #define NRF_PPI_TASK_SET (1UL)
50*150812a8SEvalZero
51*150812a8SEvalZero /**
52*150812a8SEvalZero * @enum nrf_ppi_channel_t
53*150812a8SEvalZero * @brief PPI channels.
54*150812a8SEvalZero */
55*150812a8SEvalZero typedef enum
56*150812a8SEvalZero {
57*150812a8SEvalZero NRF_PPI_CHANNEL0 = PPI_CHEN_CH0_Pos, /**< Channel 0. */
58*150812a8SEvalZero NRF_PPI_CHANNEL1 = PPI_CHEN_CH1_Pos, /**< Channel 1. */
59*150812a8SEvalZero NRF_PPI_CHANNEL2 = PPI_CHEN_CH2_Pos, /**< Channel 2. */
60*150812a8SEvalZero NRF_PPI_CHANNEL3 = PPI_CHEN_CH3_Pos, /**< Channel 3. */
61*150812a8SEvalZero NRF_PPI_CHANNEL4 = PPI_CHEN_CH4_Pos, /**< Channel 4. */
62*150812a8SEvalZero NRF_PPI_CHANNEL5 = PPI_CHEN_CH5_Pos, /**< Channel 5. */
63*150812a8SEvalZero NRF_PPI_CHANNEL6 = PPI_CHEN_CH6_Pos, /**< Channel 6. */
64*150812a8SEvalZero NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
65*150812a8SEvalZero NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
66*150812a8SEvalZero NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
67*150812a8SEvalZero NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
68*150812a8SEvalZero NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
69*150812a8SEvalZero NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
70*150812a8SEvalZero NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
71*150812a8SEvalZero NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
72*150812a8SEvalZero NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
73*150812a8SEvalZero #if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__)
74*150812a8SEvalZero NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
75*150812a8SEvalZero NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
76*150812a8SEvalZero NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
77*150812a8SEvalZero NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
78*150812a8SEvalZero #endif
79*150812a8SEvalZero NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
80*150812a8SEvalZero NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
81*150812a8SEvalZero NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
82*150812a8SEvalZero NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
83*150812a8SEvalZero NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
84*150812a8SEvalZero NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
85*150812a8SEvalZero NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
86*150812a8SEvalZero NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
87*150812a8SEvalZero NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
88*150812a8SEvalZero NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
89*150812a8SEvalZero NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
90*150812a8SEvalZero NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos /**< Channel 31. */
91*150812a8SEvalZero } nrf_ppi_channel_t;
92*150812a8SEvalZero
93*150812a8SEvalZero /**
94*150812a8SEvalZero * @enum nrf_ppi_channel_group_t
95*150812a8SEvalZero * @brief PPI channel groups.
96*150812a8SEvalZero */
97*150812a8SEvalZero typedef enum
98*150812a8SEvalZero {
99*150812a8SEvalZero NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
100*150812a8SEvalZero NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
101*150812a8SEvalZero NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
102*150812a8SEvalZero NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
103*150812a8SEvalZero #if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
104*150812a8SEvalZero NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
105*150812a8SEvalZero NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
106*150812a8SEvalZero #endif
107*150812a8SEvalZero } nrf_ppi_channel_group_t;
108*150812a8SEvalZero
109*150812a8SEvalZero /**
110*150812a8SEvalZero * @enum nrf_ppi_channel_include_t
111*150812a8SEvalZero * @brief Definition of which PPI channels belong to a group.
112*150812a8SEvalZero */
113*150812a8SEvalZero typedef enum
114*150812a8SEvalZero {
115*150812a8SEvalZero NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
116*150812a8SEvalZero NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included /**< Channel included in a group. */
117*150812a8SEvalZero } nrf_ppi_channel_include_t;
118*150812a8SEvalZero
119*150812a8SEvalZero /**
120*150812a8SEvalZero * @enum nrf_ppi_channel_enable_t
121*150812a8SEvalZero * @brief Definition if a PPI channel is enabled.
122*150812a8SEvalZero */
123*150812a8SEvalZero typedef enum
124*150812a8SEvalZero {
125*150812a8SEvalZero NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
126*150812a8SEvalZero NRF_PPI_CHANNEL_ENABLED = PPI_CHEN_CH0_Enabled /**< Channel enabled. */
127*150812a8SEvalZero } nrf_ppi_channel_enable_t;
128*150812a8SEvalZero
129*150812a8SEvalZero /**
130*150812a8SEvalZero * @enum nrf_ppi_task_t
131*150812a8SEvalZero * @brief PPI tasks.
132*150812a8SEvalZero */
133*150812a8SEvalZero typedef enum
134*150812a8SEvalZero {
135*150812a8SEvalZero /*lint -save -e30 -esym(628,__INTADDR__)*/
136*150812a8SEvalZero NRF_PPI_TASK_CHG0_EN = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN), /**< Task for enabling channel group 0 */
137*150812a8SEvalZero NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
138*150812a8SEvalZero NRF_PPI_TASK_CHG1_EN = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN), /**< Task for enabling channel group 1 */
139*150812a8SEvalZero NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
140*150812a8SEvalZero NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */
141*150812a8SEvalZero NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
142*150812a8SEvalZero NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */
143*150812a8SEvalZero NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
144*150812a8SEvalZero #if (PPI_GROUP_NUM > 4) || defined(__NRFX_DOXYGEN__)
145*150812a8SEvalZero NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */
146*150812a8SEvalZero NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
147*150812a8SEvalZero NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */
148*150812a8SEvalZero NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */
149*150812a8SEvalZero #endif
150*150812a8SEvalZero /*lint -restore*/
151*150812a8SEvalZero } nrf_ppi_task_t;
152*150812a8SEvalZero
153*150812a8SEvalZero /**
154*150812a8SEvalZero * @brief Function for enabling a given PPI channel.
155*150812a8SEvalZero *
156*150812a8SEvalZero * @details This function enables only one channel.
157*150812a8SEvalZero *
158*150812a8SEvalZero * @param[in] channel Channel to enable.
159*150812a8SEvalZero *
160*150812a8SEvalZero * */
161*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel);
162*150812a8SEvalZero
163*150812a8SEvalZero /**
164*150812a8SEvalZero * @brief Function for disabling a given PPI channel.
165*150812a8SEvalZero *
166*150812a8SEvalZero * @details This function disables only one channel.
167*150812a8SEvalZero *
168*150812a8SEvalZero * @param[in] channel Channel to disable.
169*150812a8SEvalZero */
170*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel);
171*150812a8SEvalZero
172*150812a8SEvalZero /**
173*150812a8SEvalZero * @brief Function for checking if a given PPI channel is enabled.
174*150812a8SEvalZero *
175*150812a8SEvalZero * @details This function checks only one channel.
176*150812a8SEvalZero *
177*150812a8SEvalZero * @param[in] channel Channel to check.
178*150812a8SEvalZero *
179*150812a8SEvalZero * @retval NRF_PPI_CHANNEL_ENABLED If the channel is enabled.
180*150812a8SEvalZero * @retval NRF_PPI_CHANNEL_DISABLED If the channel is not enabled.
181*150812a8SEvalZero *
182*150812a8SEvalZero */
183*150812a8SEvalZero __STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel);
184*150812a8SEvalZero
185*150812a8SEvalZero /**
186*150812a8SEvalZero * @brief Function for disabling all PPI channels.
187*150812a8SEvalZero */
188*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_disable_all(void);
189*150812a8SEvalZero
190*150812a8SEvalZero /**
191*150812a8SEvalZero * @brief Function for enabling multiple PPI channels.
192*150812a8SEvalZero *
193*150812a8SEvalZero * @param[in] mask Channel mask.
194*150812a8SEvalZero */
195*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_enable(uint32_t mask);
196*150812a8SEvalZero
197*150812a8SEvalZero /**
198*150812a8SEvalZero * @brief Function for disabling multiple PPI channels.
199*150812a8SEvalZero *
200*150812a8SEvalZero * @param[in] mask Channel mask.
201*150812a8SEvalZero */
202*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask);
203*150812a8SEvalZero
204*150812a8SEvalZero /**
205*150812a8SEvalZero * @brief Function for setting up event and task endpoints for a given PPI channel.
206*150812a8SEvalZero *
207*150812a8SEvalZero * @param[in] eep Event register address.
208*150812a8SEvalZero *
209*150812a8SEvalZero * @param[in] tep Task register address.
210*150812a8SEvalZero *
211*150812a8SEvalZero * @param[in] channel Channel to which the given endpoints are assigned.
212*150812a8SEvalZero */
213*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
214*150812a8SEvalZero uint32_t eep,
215*150812a8SEvalZero uint32_t tep);
216*150812a8SEvalZero
217*150812a8SEvalZero /**
218*150812a8SEvalZero * @brief Function for setting up the event endpoint for a given PPI channel.
219*150812a8SEvalZero *
220*150812a8SEvalZero * @param[in] eep Event register address.
221*150812a8SEvalZero * @param[in] channel Channel to which the given endpoint is assigned.
222*150812a8SEvalZero */
223*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,
224*150812a8SEvalZero uint32_t eep);
225*150812a8SEvalZero
226*150812a8SEvalZero /**
227*150812a8SEvalZero * @brief Function for setting up the task endpoint for a given PPI channel.
228*150812a8SEvalZero *
229*150812a8SEvalZero * @param[in] tep Task register address.
230*150812a8SEvalZero * @param[in] channel Channel to which the given endpoint is assigned.
231*150812a8SEvalZero */
232*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,
233*150812a8SEvalZero uint32_t tep);
234*150812a8SEvalZero
235*150812a8SEvalZero
236*150812a8SEvalZero #if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__NRFX_DOXYGEN__)
237*150812a8SEvalZero /**
238*150812a8SEvalZero * @brief Function for setting up task endpoint for a given PPI fork.
239*150812a8SEvalZero *
240*150812a8SEvalZero * @param[in] fork_tep Task register address.
241*150812a8SEvalZero *
242*150812a8SEvalZero * @param[in] channel Channel to which the given fork endpoint is assigned.
243*150812a8SEvalZero */
244*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
245*150812a8SEvalZero uint32_t fork_tep);
246*150812a8SEvalZero
247*150812a8SEvalZero /**
248*150812a8SEvalZero * @brief Function for setting up event and task endpoints for a given PPI channel and fork.
249*150812a8SEvalZero *
250*150812a8SEvalZero * @param[in] eep Event register address.
251*150812a8SEvalZero *
252*150812a8SEvalZero * @param[in] tep Task register address.
253*150812a8SEvalZero *
254*150812a8SEvalZero * @param[in] fork_tep Fork task register address (register value).
255*150812a8SEvalZero *
256*150812a8SEvalZero * @param[in] channel Channel to which the given endpoints are assigned.
257*150812a8SEvalZero */
258*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
259*150812a8SEvalZero uint32_t eep,
260*150812a8SEvalZero uint32_t tep,
261*150812a8SEvalZero uint32_t fork_tep);
262*150812a8SEvalZero #endif
263*150812a8SEvalZero
264*150812a8SEvalZero /**
265*150812a8SEvalZero * @brief Function for including a PPI channel in a channel group.
266*150812a8SEvalZero *
267*150812a8SEvalZero * @details This function adds only one channel to the group.
268*150812a8SEvalZero *
269*150812a8SEvalZero * @param[in] channel Channel to be included in the group.
270*150812a8SEvalZero *
271*150812a8SEvalZero * @param[in] channel_group Channel group.
272*150812a8SEvalZero *
273*150812a8SEvalZero */
274*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
275*150812a8SEvalZero nrf_ppi_channel_group_t channel_group);
276*150812a8SEvalZero
277*150812a8SEvalZero /**
278*150812a8SEvalZero * @brief Function for including multiple PPI channels in a channel group.
279*150812a8SEvalZero *
280*150812a8SEvalZero * @details This function adds all specified channels to the group.
281*150812a8SEvalZero *
282*150812a8SEvalZero * @param[in] channel_mask Channels to be included in the group.
283*150812a8SEvalZero *
284*150812a8SEvalZero * @param[in] channel_group Channel group.
285*150812a8SEvalZero *
286*150812a8SEvalZero */
287*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask,
288*150812a8SEvalZero nrf_ppi_channel_group_t channel_group);
289*150812a8SEvalZero
290*150812a8SEvalZero /**
291*150812a8SEvalZero * @brief Function for removing a PPI channel from a channel group.
292*150812a8SEvalZero *
293*150812a8SEvalZero * @details This function removes only one channel from the group.
294*150812a8SEvalZero *
295*150812a8SEvalZero * @param[in] channel Channel to be removed from the group.
296*150812a8SEvalZero *
297*150812a8SEvalZero * @param[in] channel_group Channel group.
298*150812a8SEvalZero */
299*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
300*150812a8SEvalZero nrf_ppi_channel_group_t channel_group);
301*150812a8SEvalZero
302*150812a8SEvalZero /**
303*150812a8SEvalZero * @brief Function for removing multiple PPI channels from a channel group.
304*150812a8SEvalZero *
305*150812a8SEvalZero * @details This function removes all specified channels from the group.
306*150812a8SEvalZero *
307*150812a8SEvalZero * @param[in] channel_mask Channels to be removed from the group.
308*150812a8SEvalZero *
309*150812a8SEvalZero * @param[in] channel_group Channel group.
310*150812a8SEvalZero */
311*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask,
312*150812a8SEvalZero nrf_ppi_channel_group_t channel_group);
313*150812a8SEvalZero
314*150812a8SEvalZero /**
315*150812a8SEvalZero * @brief Function for removing all PPI channels from a channel group.
316*150812a8SEvalZero *
317*150812a8SEvalZero * @param[in] group Channel group.
318*150812a8SEvalZero *
319*150812a8SEvalZero */
320*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group);
321*150812a8SEvalZero
322*150812a8SEvalZero /**
323*150812a8SEvalZero * @brief Function for enabling a channel group.
324*150812a8SEvalZero *
325*150812a8SEvalZero * @param[in] group Channel group.
326*150812a8SEvalZero *
327*150812a8SEvalZero */
328*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group);
329*150812a8SEvalZero
330*150812a8SEvalZero /**
331*150812a8SEvalZero * @brief Function for disabling a channel group.
332*150812a8SEvalZero *
333*150812a8SEvalZero * @param[in] group Channel group.
334*150812a8SEvalZero *
335*150812a8SEvalZero */
336*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group);
337*150812a8SEvalZero
338*150812a8SEvalZero /**
339*150812a8SEvalZero * @brief Function for setting a PPI task.
340*150812a8SEvalZero *
341*150812a8SEvalZero * @param[in] ppi_task PPI task to set.
342*150812a8SEvalZero */
343*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task);
344*150812a8SEvalZero
345*150812a8SEvalZero /**
346*150812a8SEvalZero * @brief Function for returning the address of a specific PPI task register.
347*150812a8SEvalZero *
348*150812a8SEvalZero * @param[in] ppi_task PPI task.
349*150812a8SEvalZero */
350*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task);
351*150812a8SEvalZero
352*150812a8SEvalZero /**
353*150812a8SEvalZero * @brief Function for returning the PPI enable task address of a specific group.
354*150812a8SEvalZero *
355*150812a8SEvalZero * @param[in] group PPI group.
356*150812a8SEvalZero */
357*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group);
358*150812a8SEvalZero
359*150812a8SEvalZero /**
360*150812a8SEvalZero * @brief Function for returning the PPI disable task address of a specific group.
361*150812a8SEvalZero *
362*150812a8SEvalZero * @param[in] group PPI group.
363*150812a8SEvalZero */
364*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group);
365*150812a8SEvalZero
366*150812a8SEvalZero
367*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
368*150812a8SEvalZero
nrf_ppi_channel_enable(nrf_ppi_channel_t channel)369*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel)
370*150812a8SEvalZero {
371*150812a8SEvalZero NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
372*150812a8SEvalZero }
373*150812a8SEvalZero
nrf_ppi_channel_disable(nrf_ppi_channel_t channel)374*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel)
375*150812a8SEvalZero {
376*150812a8SEvalZero NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
377*150812a8SEvalZero }
378*150812a8SEvalZero
nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)379*150812a8SEvalZero __STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)
380*150812a8SEvalZero {
381*150812a8SEvalZero if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
382*150812a8SEvalZero {
383*150812a8SEvalZero return NRF_PPI_CHANNEL_ENABLED;
384*150812a8SEvalZero }
385*150812a8SEvalZero else
386*150812a8SEvalZero {
387*150812a8SEvalZero return NRF_PPI_CHANNEL_DISABLED;
388*150812a8SEvalZero }
389*150812a8SEvalZero }
390*150812a8SEvalZero
nrf_ppi_channel_disable_all(void)391*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_disable_all(void)
392*150812a8SEvalZero {
393*150812a8SEvalZero NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
394*150812a8SEvalZero }
395*150812a8SEvalZero
nrf_ppi_channels_enable(uint32_t mask)396*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_enable(uint32_t mask)
397*150812a8SEvalZero {
398*150812a8SEvalZero NRF_PPI->CHENSET = mask;
399*150812a8SEvalZero }
400*150812a8SEvalZero
nrf_ppi_channels_disable(uint32_t mask)401*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
402*150812a8SEvalZero {
403*150812a8SEvalZero NRF_PPI->CHENCLR = mask;
404*150812a8SEvalZero }
405*150812a8SEvalZero
nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,uint32_t eep,uint32_t tep)406*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
407*150812a8SEvalZero uint32_t eep,
408*150812a8SEvalZero uint32_t tep)
409*150812a8SEvalZero {
410*150812a8SEvalZero NRF_PPI->CH[(uint32_t) channel].EEP = eep;
411*150812a8SEvalZero NRF_PPI->CH[(uint32_t) channel].TEP = tep;
412*150812a8SEvalZero }
413*150812a8SEvalZero
nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,uint32_t eep)414*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,
415*150812a8SEvalZero uint32_t eep)
416*150812a8SEvalZero {
417*150812a8SEvalZero NRF_PPI->CH[(uint32_t) channel].EEP = eep;
418*150812a8SEvalZero }
419*150812a8SEvalZero
nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,uint32_t tep)420*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,
421*150812a8SEvalZero uint32_t tep)
422*150812a8SEvalZero {
423*150812a8SEvalZero NRF_PPI->CH[(uint32_t) channel].TEP = tep;
424*150812a8SEvalZero }
425*150812a8SEvalZero
426*150812a8SEvalZero #if defined(PPI_FEATURE_FORKS_PRESENT)
427*150812a8SEvalZero
nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,uint32_t fork_tep)428*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
429*150812a8SEvalZero uint32_t fork_tep)
430*150812a8SEvalZero {
431*150812a8SEvalZero NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
432*150812a8SEvalZero }
433*150812a8SEvalZero
nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,uint32_t eep,uint32_t tep,uint32_t fork_tep)434*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
435*150812a8SEvalZero uint32_t eep,
436*150812a8SEvalZero uint32_t tep,
437*150812a8SEvalZero uint32_t fork_tep)
438*150812a8SEvalZero {
439*150812a8SEvalZero nrf_ppi_channel_endpoint_setup(channel, eep, tep);
440*150812a8SEvalZero nrf_ppi_fork_endpoint_setup(channel, fork_tep);
441*150812a8SEvalZero }
442*150812a8SEvalZero #endif
443*150812a8SEvalZero
nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,nrf_ppi_channel_group_t channel_group)444*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t channel,
445*150812a8SEvalZero nrf_ppi_channel_group_t channel_group)
446*150812a8SEvalZero {
447*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] =
448*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t) channel));
449*150812a8SEvalZero }
450*150812a8SEvalZero
nrf_ppi_channels_include_in_group(uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)451*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t channel_mask,
452*150812a8SEvalZero nrf_ppi_channel_group_t channel_group)
453*150812a8SEvalZero {
454*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] =
455*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask);
456*150812a8SEvalZero }
457*150812a8SEvalZero
nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,nrf_ppi_channel_group_t channel_group)458*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t channel,
459*150812a8SEvalZero nrf_ppi_channel_group_t channel_group)
460*150812a8SEvalZero {
461*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] =
462*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
463*150812a8SEvalZero }
464*150812a8SEvalZero
nrf_ppi_channels_remove_from_group(uint32_t channel_mask,nrf_ppi_channel_group_t channel_group)465*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t channel_mask,
466*150812a8SEvalZero nrf_ppi_channel_group_t channel_group)
467*150812a8SEvalZero {
468*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] =
469*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask);
470*150812a8SEvalZero }
471*150812a8SEvalZero
nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)472*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
473*150812a8SEvalZero {
474*150812a8SEvalZero NRF_PPI->CHG[(uint32_t) group] = 0;
475*150812a8SEvalZero }
476*150812a8SEvalZero
nrf_ppi_group_enable(nrf_ppi_channel_group_t group)477*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
478*150812a8SEvalZero {
479*150812a8SEvalZero NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
480*150812a8SEvalZero }
481*150812a8SEvalZero
nrf_ppi_group_disable(nrf_ppi_channel_group_t group)482*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
483*150812a8SEvalZero {
484*150812a8SEvalZero NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
485*150812a8SEvalZero }
486*150812a8SEvalZero
nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)487*150812a8SEvalZero __STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
488*150812a8SEvalZero {
489*150812a8SEvalZero *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
490*150812a8SEvalZero }
491*150812a8SEvalZero
nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)492*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
493*150812a8SEvalZero {
494*150812a8SEvalZero return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task);
495*150812a8SEvalZero }
496*150812a8SEvalZero
nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)497*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)
498*150812a8SEvalZero {
499*150812a8SEvalZero return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN;
500*150812a8SEvalZero }
501*150812a8SEvalZero
nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)502*150812a8SEvalZero __STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)
503*150812a8SEvalZero {
504*150812a8SEvalZero return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
505*150812a8SEvalZero }
506*150812a8SEvalZero
507*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
508*150812a8SEvalZero
509*150812a8SEvalZero /** @} */
510*150812a8SEvalZero
511*150812a8SEvalZero #ifdef __cplusplus
512*150812a8SEvalZero }
513*150812a8SEvalZero #endif
514*150812a8SEvalZero
515*150812a8SEvalZero #endif // NRF_PPI_H__
516