Lines Matching full:ppi

2406 /* Bit 31 : PPI region configuration. */
2407 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
2408 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
3260 /* Peripheral: PPI */
3261 /* Description: PPI controller. */
3266 /* Bit 31 : Enable PPI channel 31. */
3272 /* Bit 30 : Enable PPI channel 30. */
3278 /* Bit 29 : Enable PPI channel 29. */
3284 /* Bit 28 : Enable PPI channel 28. */
3290 /* Bit 27 : Enable PPI channel 27. */
3296 /* Bit 26 : Enable PPI channel 26. */
3302 /* Bit 25 : Enable PPI channel 25. */
3308 /* Bit 24 : Enable PPI channel 24. */
3314 /* Bit 23 : Enable PPI channel 23. */
3320 /* Bit 22 : Enable PPI channel 22. */
3326 /* Bit 21 : Enable PPI channel 21. */
3332 /* Bit 20 : Enable PPI channel 20. */
3338 /* Bit 15 : Enable PPI channel 15. */
3344 /* Bit 14 : Enable PPI channel 14. */
3350 /* Bit 13 : Enable PPI channel 13. */
3356 /* Bit 12 : Enable PPI channel 12. */
3362 /* Bit 11 : Enable PPI channel 11. */
3368 /* Bit 10 : Enable PPI channel 10. */
3374 /* Bit 9 : Enable PPI channel 9. */
3380 /* Bit 8 : Enable PPI channel 8. */
3386 /* Bit 7 : Enable PPI channel 7. */
3392 /* Bit 6 : Enable PPI channel 6. */
3398 /* Bit 5 : Enable PPI channel 5. */
3404 /* Bit 4 : Enable PPI channel 4. */
3410 /* Bit 3 : Enable PPI channel 3. */
3416 /* Bit 2 : Enable PPI channel 2. */
3422 /* Bit 1 : Enable PPI channel 1. */
3428 /* Bit 0 : Enable PPI channel 0. */
3437 /* Bit 31 : Enable PPI channel 31. */
3444 /* Bit 30 : Enable PPI channel 30. */
3451 /* Bit 29 : Enable PPI channel 29. */
3458 /* Bit 28 : Enable PPI channel 28. */
3465 /* Bit 27 : Enable PPI channel 27. */
3472 /* Bit 26 : Enable PPI channel 26. */
3479 /* Bit 25 : Enable PPI channel 25. */
3486 /* Bit 24 : Enable PPI channel 24. */
3493 /* Bit 23 : Enable PPI channel 23. */
3500 /* Bit 22 : Enable PPI channel 22. */
3507 /* Bit 21 : Enable PPI channel 21. */
3514 /* Bit 20 : Enable PPI channel 20. */
3521 /* Bit 15 : Enable PPI channel 15. */
3528 /* Bit 14 : Enable PPI channel 14. */
3535 /* Bit 13 : Enable PPI channel 13. */
3542 /* Bit 12 : Enable PPI channel 12. */
3549 /* Bit 11 : Enable PPI channel 11. */
3556 /* Bit 10 : Enable PPI channel 10. */
3563 /* Bit 9 : Enable PPI channel 9. */
3570 /* Bit 8 : Enable PPI channel 8. */
3577 /* Bit 7 : Enable PPI channel 7. */
3584 /* Bit 6 : Enable PPI channel 6. */
3591 /* Bit 5 : Enable PPI channel 5. */
3598 /* Bit 4 : Enable PPI channel 4. */
3605 /* Bit 3 : Enable PPI channel 3. */
3612 /* Bit 2 : Enable PPI channel 2. */
3619 /* Bit 1 : Enable PPI channel 1. */
3626 /* Bit 0 : Enable PPI channel 0. */
3636 /* Bit 31 : Disable PPI channel 31. */
3643 /* Bit 30 : Disable PPI channel 30. */
3650 /* Bit 29 : Disable PPI channel 29. */
3657 /* Bit 28 : Disable PPI channel 28. */
3664 /* Bit 27 : Disable PPI channel 27. */
3671 /* Bit 26 : Disable PPI channel 26. */
3678 /* Bit 25 : Disable PPI channel 25. */
3685 /* Bit 24 : Disable PPI channel 24. */
3692 /* Bit 23 : Disable PPI channel 23. */
3699 /* Bit 22 : Disable PPI channel 22. */
3706 /* Bit 21 : Disable PPI channel 21. */
3713 /* Bit 20 : Disable PPI channel 20. */
3720 /* Bit 15 : Disable PPI channel 15. */
3727 /* Bit 14 : Disable PPI channel 14. */
3734 /* Bit 13 : Disable PPI channel 13. */
3741 /* Bit 12 : Disable PPI channel 12. */
3748 /* Bit 11 : Disable PPI channel 11. */
3755 /* Bit 10 : Disable PPI channel 10. */
3762 /* Bit 9 : Disable PPI channel 9. */
3769 /* Bit 8 : Disable PPI channel 8. */
3776 /* Bit 7 : Disable PPI channel 7. */
3783 /* Bit 6 : Disable PPI channel 6. */
3790 /* Bit 5 : Disable PPI channel 5. */
3797 /* Bit 4 : Disable PPI channel 4. */
3804 /* Bit 3 : Disable PPI channel 3. */
3811 /* Bit 2 : Disable PPI channel 2. */
3818 /* Bit 1 : Disable PPI channel 1. */
3825 /* Bit 0 : Disable PPI channel 0. */
4928 /* Description: Configures event enable routing to PPI for each RTC event. */
4967 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN…
4969 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
4976 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
4983 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
4990 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
4997 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
5004 /* Bit 0 : Enable routing to PPI of TICK event. */
5012 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTE…
5014 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
5021 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
5028 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
5035 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
5042 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
5049 /* Bit 0 : Disable routing to PPI of TICK event. */