1*150812a8SEvalZero /* 2*150812a8SEvalZero * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3*150812a8SEvalZero * 4*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without 5*150812a8SEvalZero * modification, are permitted provided that the following conditions are met: 6*150812a8SEvalZero * 7*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this 8*150812a8SEvalZero * list of conditions and the following disclaimer. 9*150812a8SEvalZero * 10*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright 11*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the 12*150812a8SEvalZero * documentation and/or other materials provided with the distribution. 13*150812a8SEvalZero * 14*150812a8SEvalZero * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this 16*150812a8SEvalZero * software without specific prior written permission. 17*150812a8SEvalZero * 18*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE. 29*150812a8SEvalZero * 30*150812a8SEvalZero * @file nrf51.h 31*150812a8SEvalZero * @brief CMSIS HeaderFile 32*150812a8SEvalZero * @version 522 33*150812a8SEvalZero * @date 03. December 2018 34*150812a8SEvalZero * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 35*150812a8SEvalZero * from File 'nrf51.svd', 36*150812a8SEvalZero * last modified on Monday, 03.12.2018 10:18:20 37*150812a8SEvalZero */ 38*150812a8SEvalZero 39*150812a8SEvalZero 40*150812a8SEvalZero 41*150812a8SEvalZero /** @addtogroup Nordic Semiconductor 42*150812a8SEvalZero * @{ 43*150812a8SEvalZero */ 44*150812a8SEvalZero 45*150812a8SEvalZero 46*150812a8SEvalZero /** @addtogroup nrf51 47*150812a8SEvalZero * @{ 48*150812a8SEvalZero */ 49*150812a8SEvalZero 50*150812a8SEvalZero 51*150812a8SEvalZero #ifndef NRF51_H 52*150812a8SEvalZero #define NRF51_H 53*150812a8SEvalZero 54*150812a8SEvalZero #ifdef __cplusplus 55*150812a8SEvalZero extern "C" { 56*150812a8SEvalZero #endif 57*150812a8SEvalZero 58*150812a8SEvalZero 59*150812a8SEvalZero /** @addtogroup Configuration_of_CMSIS 60*150812a8SEvalZero * @{ 61*150812a8SEvalZero */ 62*150812a8SEvalZero 63*150812a8SEvalZero 64*150812a8SEvalZero 65*150812a8SEvalZero /* =========================================================================================================================== */ 66*150812a8SEvalZero /* ================ Interrupt Number Definition ================ */ 67*150812a8SEvalZero /* =========================================================================================================================== */ 68*150812a8SEvalZero 69*150812a8SEvalZero typedef enum { 70*150812a8SEvalZero /* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ 71*150812a8SEvalZero Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72*150812a8SEvalZero NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73*150812a8SEvalZero HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74*150812a8SEvalZero SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 75*150812a8SEvalZero PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 76*150812a8SEvalZero SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 77*150812a8SEvalZero /* =========================================== nrf51 Specific Interrupt Numbers ============================================ */ 78*150812a8SEvalZero POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 79*150812a8SEvalZero RADIO_IRQn = 1, /*!< 1 RADIO */ 80*150812a8SEvalZero UART0_IRQn = 2, /*!< 2 UART0 */ 81*150812a8SEvalZero SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 82*150812a8SEvalZero SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 83*150812a8SEvalZero GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 84*150812a8SEvalZero ADC_IRQn = 7, /*!< 7 ADC */ 85*150812a8SEvalZero TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 86*150812a8SEvalZero TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 87*150812a8SEvalZero TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 88*150812a8SEvalZero RTC0_IRQn = 11, /*!< 11 RTC0 */ 89*150812a8SEvalZero TEMP_IRQn = 12, /*!< 12 TEMP */ 90*150812a8SEvalZero RNG_IRQn = 13, /*!< 13 RNG */ 91*150812a8SEvalZero ECB_IRQn = 14, /*!< 14 ECB */ 92*150812a8SEvalZero CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 93*150812a8SEvalZero WDT_IRQn = 16, /*!< 16 WDT */ 94*150812a8SEvalZero RTC1_IRQn = 17, /*!< 17 RTC1 */ 95*150812a8SEvalZero QDEC_IRQn = 18, /*!< 18 QDEC */ 96*150812a8SEvalZero LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 97*150812a8SEvalZero SWI0_IRQn = 20, /*!< 20 SWI0 */ 98*150812a8SEvalZero SWI1_IRQn = 21, /*!< 21 SWI1 */ 99*150812a8SEvalZero SWI2_IRQn = 22, /*!< 22 SWI2 */ 100*150812a8SEvalZero SWI3_IRQn = 23, /*!< 23 SWI3 */ 101*150812a8SEvalZero SWI4_IRQn = 24, /*!< 24 SWI4 */ 102*150812a8SEvalZero SWI5_IRQn = 25 /*!< 25 SWI5 */ 103*150812a8SEvalZero } IRQn_Type; 104*150812a8SEvalZero 105*150812a8SEvalZero 106*150812a8SEvalZero 107*150812a8SEvalZero /* =========================================================================================================================== */ 108*150812a8SEvalZero /* ================ Processor and Core Peripheral Section ================ */ 109*150812a8SEvalZero /* =========================================================================================================================== */ 110*150812a8SEvalZero 111*150812a8SEvalZero /* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ 112*150812a8SEvalZero #define __CM0_REV 0x0301U /*!< CM0 Core Revision */ 113*150812a8SEvalZero #define __DSP_PRESENT 0 /*!< DSP present or not */ 114*150812a8SEvalZero #define __MPU_PRESENT 0 /*!< MPU present or not */ 115*150812a8SEvalZero #define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 116*150812a8SEvalZero #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 117*150812a8SEvalZero #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 118*150812a8SEvalZero 119*150812a8SEvalZero 120*150812a8SEvalZero /** @} */ /* End of group Configuration_of_CMSIS */ 121*150812a8SEvalZero 122*150812a8SEvalZero #include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ 123*150812a8SEvalZero #include "system_nrf51.h" /*!< nrf51 System */ 124*150812a8SEvalZero 125*150812a8SEvalZero #ifndef __IM /*!< Fallback for older CMSIS versions */ 126*150812a8SEvalZero #define __IM __I 127*150812a8SEvalZero #endif 128*150812a8SEvalZero #ifndef __OM /*!< Fallback for older CMSIS versions */ 129*150812a8SEvalZero #define __OM __O 130*150812a8SEvalZero #endif 131*150812a8SEvalZero #ifndef __IOM /*!< Fallback for older CMSIS versions */ 132*150812a8SEvalZero #define __IOM __IO 133*150812a8SEvalZero #endif 134*150812a8SEvalZero 135*150812a8SEvalZero 136*150812a8SEvalZero /* ======================================== Start of section using anonymous unions ======================================== */ 137*150812a8SEvalZero #if defined (__CC_ARM) 138*150812a8SEvalZero #pragma push 139*150812a8SEvalZero #pragma anon_unions 140*150812a8SEvalZero #elif defined (__ICCARM__) 141*150812a8SEvalZero #pragma language=extended 142*150812a8SEvalZero #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 143*150812a8SEvalZero #pragma clang diagnostic push 144*150812a8SEvalZero #pragma clang diagnostic ignored "-Wc11-extensions" 145*150812a8SEvalZero #pragma clang diagnostic ignored "-Wreserved-id-macro" 146*150812a8SEvalZero #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 147*150812a8SEvalZero #pragma clang diagnostic ignored "-Wnested-anon-types" 148*150812a8SEvalZero #elif defined (__GNUC__) 149*150812a8SEvalZero /* anonymous unions are enabled by default */ 150*150812a8SEvalZero #elif defined (__TMS470__) 151*150812a8SEvalZero /* anonymous unions are enabled by default */ 152*150812a8SEvalZero #elif defined (__TASKING__) 153*150812a8SEvalZero #pragma warning 586 154*150812a8SEvalZero #elif defined (__CSMC__) 155*150812a8SEvalZero /* anonymous unions are enabled by default */ 156*150812a8SEvalZero #else 157*150812a8SEvalZero #warning Not supported compiler type 158*150812a8SEvalZero #endif 159*150812a8SEvalZero 160*150812a8SEvalZero 161*150812a8SEvalZero /* =========================================================================================================================== */ 162*150812a8SEvalZero /* ================ Device Specific Cluster Section ================ */ 163*150812a8SEvalZero /* =========================================================================================================================== */ 164*150812a8SEvalZero 165*150812a8SEvalZero 166*150812a8SEvalZero /** @addtogroup Device_Peripheral_clusters 167*150812a8SEvalZero * @{ 168*150812a8SEvalZero */ 169*150812a8SEvalZero 170*150812a8SEvalZero 171*150812a8SEvalZero /** 172*150812a8SEvalZero * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks.) 173*150812a8SEvalZero */ 174*150812a8SEvalZero typedef struct { 175*150812a8SEvalZero __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. */ 176*150812a8SEvalZero __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. */ 177*150812a8SEvalZero } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 178*150812a8SEvalZero 179*150812a8SEvalZero 180*150812a8SEvalZero /** 181*150812a8SEvalZero * @brief PPI_CH [CH] (PPI Channel.) 182*150812a8SEvalZero */ 183*150812a8SEvalZero typedef struct { 184*150812a8SEvalZero __IOM uint32_t EEP; /*!< (@ 0x00000000) Channel event end-point. */ 185*150812a8SEvalZero __IOM uint32_t TEP; /*!< (@ 0x00000004) Channel task end-point. */ 186*150812a8SEvalZero } PPI_CH_Type; /*!< Size = 8 (0x8) */ 187*150812a8SEvalZero 188*150812a8SEvalZero 189*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_clusters */ 190*150812a8SEvalZero 191*150812a8SEvalZero 192*150812a8SEvalZero /* =========================================================================================================================== */ 193*150812a8SEvalZero /* ================ Device Specific Peripheral Section ================ */ 194*150812a8SEvalZero /* =========================================================================================================================== */ 195*150812a8SEvalZero 196*150812a8SEvalZero 197*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripherals 198*150812a8SEvalZero * @{ 199*150812a8SEvalZero */ 200*150812a8SEvalZero 201*150812a8SEvalZero 202*150812a8SEvalZero 203*150812a8SEvalZero /* =========================================================================================================================== */ 204*150812a8SEvalZero /* ================ POWER ================ */ 205*150812a8SEvalZero /* =========================================================================================================================== */ 206*150812a8SEvalZero 207*150812a8SEvalZero 208*150812a8SEvalZero /** 209*150812a8SEvalZero * @brief Power Control. (POWER) 210*150812a8SEvalZero */ 211*150812a8SEvalZero 212*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) POWER Structure */ 213*150812a8SEvalZero __IM uint32_t RESERVED[30]; 214*150812a8SEvalZero __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ 215*150812a8SEvalZero __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency). */ 216*150812a8SEvalZero __IM uint32_t RESERVED1[34]; 217*150812a8SEvalZero __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning. */ 218*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 219*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 220*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 221*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 222*150812a8SEvalZero __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason. */ 223*150812a8SEvalZero __IM uint32_t RESERVED4[9]; 224*150812a8SEvalZero __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Ram status register. */ 225*150812a8SEvalZero __IM uint32_t RESERVED5[53]; 226*150812a8SEvalZero __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System off register. */ 227*150812a8SEvalZero __IM uint32_t RESERVED6[3]; 228*150812a8SEvalZero __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure configuration. */ 229*150812a8SEvalZero __IM uint32_t RESERVED7[2]; 230*150812a8SEvalZero __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register. This register 231*150812a8SEvalZero is a retained register. */ 232*150812a8SEvalZero __IM uint32_t RESERVED8; 233*150812a8SEvalZero __IOM uint32_t RAMON; /*!< (@ 0x00000524) Ram on/off. */ 234*150812a8SEvalZero __IM uint32_t RESERVED9[7]; 235*150812a8SEvalZero __IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configuration register. 236*150812a8SEvalZero This register is a retained register. */ 237*150812a8SEvalZero __IM uint32_t RESERVED10[3]; 238*150812a8SEvalZero __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Ram on/off. */ 239*150812a8SEvalZero __IM uint32_t RESERVED11[8]; 240*150812a8SEvalZero __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DCDC converter enable configuration register. */ 241*150812a8SEvalZero __IM uint32_t RESERVED12[291]; 242*150812a8SEvalZero __IOM uint32_t DCDCFORCE; /*!< (@ 0x00000A08) DCDC power-up force register. */ 243*150812a8SEvalZero } NRF_POWER_Type; /*!< Size = 2572 (0xa0c) */ 244*150812a8SEvalZero 245*150812a8SEvalZero 246*150812a8SEvalZero 247*150812a8SEvalZero /* =========================================================================================================================== */ 248*150812a8SEvalZero /* ================ CLOCK ================ */ 249*150812a8SEvalZero /* =========================================================================================================================== */ 250*150812a8SEvalZero 251*150812a8SEvalZero 252*150812a8SEvalZero /** 253*150812a8SEvalZero * @brief Clock control. (CLOCK) 254*150812a8SEvalZero */ 255*150812a8SEvalZero 256*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 257*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK clock source. */ 258*150812a8SEvalZero __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK clock source. */ 259*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK clock source. */ 260*150812a8SEvalZero __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK clock source. */ 261*150812a8SEvalZero __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFCLK RC oscillator. */ 262*150812a8SEvalZero __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer. */ 263*150812a8SEvalZero __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer. */ 264*150812a8SEvalZero __IM uint32_t RESERVED[57]; 265*150812a8SEvalZero __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started. */ 266*150812a8SEvalZero __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK oscillator started. */ 267*150812a8SEvalZero __IM uint32_t RESERVED1; 268*150812a8SEvalZero __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator completed. */ 269*150812a8SEvalZero __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout. */ 270*150812a8SEvalZero __IM uint32_t RESERVED2[124]; 271*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 272*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 273*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 274*150812a8SEvalZero __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Task HFCLKSTART trigger status. */ 275*150812a8SEvalZero __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) High frequency clock status. */ 276*150812a8SEvalZero __IM uint32_t RESERVED4; 277*150812a8SEvalZero __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Task LFCLKSTART triggered status. */ 278*150812a8SEvalZero __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Low frequency clock status. */ 279*150812a8SEvalZero __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Clock source for the LFCLK clock, set when task 280*150812a8SEvalZero LKCLKSTART is triggered. */ 281*150812a8SEvalZero __IM uint32_t RESERVED5[62]; 282*150812a8SEvalZero __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK clock. */ 283*150812a8SEvalZero __IM uint32_t RESERVED6[7]; 284*150812a8SEvalZero __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval. */ 285*150812a8SEvalZero __IM uint32_t RESERVED7[5]; 286*150812a8SEvalZero __IOM uint32_t XTALFREQ; /*!< (@ 0x00000550) Crystal frequency. */ 287*150812a8SEvalZero } NRF_CLOCK_Type; /*!< Size = 1364 (0x554) */ 288*150812a8SEvalZero 289*150812a8SEvalZero 290*150812a8SEvalZero 291*150812a8SEvalZero /* =========================================================================================================================== */ 292*150812a8SEvalZero /* ================ MPU ================ */ 293*150812a8SEvalZero /* =========================================================================================================================== */ 294*150812a8SEvalZero 295*150812a8SEvalZero 296*150812a8SEvalZero /** 297*150812a8SEvalZero * @brief Memory Protection Unit. (MPU) 298*150812a8SEvalZero */ 299*150812a8SEvalZero 300*150812a8SEvalZero typedef struct { /*!< (@ 0x40000000) MPU Structure */ 301*150812a8SEvalZero __IM uint32_t RESERVED[330]; 302*150812a8SEvalZero __IOM uint32_t PERR0; /*!< (@ 0x00000528) Configuration of peripherals in mpu regions. */ 303*150812a8SEvalZero __IOM uint32_t RLENR0; /*!< (@ 0x0000052C) Length of RAM region 0. */ 304*150812a8SEvalZero __IM uint32_t RESERVED1[52]; 305*150812a8SEvalZero __IOM uint32_t PROTENSET0; /*!< (@ 0x00000600) Erase and write protection bit enable set register. */ 306*150812a8SEvalZero __IOM uint32_t PROTENSET1; /*!< (@ 0x00000604) Erase and write protection bit enable set register. */ 307*150812a8SEvalZero __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protection mechanism 308*150812a8SEvalZero in debug mode. */ 309*150812a8SEvalZero __IOM uint32_t PROTBLOCKSIZE; /*!< (@ 0x0000060C) Erase and write protection block size. */ 310*150812a8SEvalZero } NRF_MPU_Type; /*!< Size = 1552 (0x610) */ 311*150812a8SEvalZero 312*150812a8SEvalZero 313*150812a8SEvalZero 314*150812a8SEvalZero /* =========================================================================================================================== */ 315*150812a8SEvalZero /* ================ RADIO ================ */ 316*150812a8SEvalZero /* =========================================================================================================================== */ 317*150812a8SEvalZero 318*150812a8SEvalZero 319*150812a8SEvalZero /** 320*150812a8SEvalZero * @brief The radio. (RADIO) 321*150812a8SEvalZero */ 322*150812a8SEvalZero 323*150812a8SEvalZero typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 324*150812a8SEvalZero __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable radio in TX mode. */ 325*150812a8SEvalZero __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable radio in RX mode. */ 326*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start radio. */ 327*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop radio. */ 328*150812a8SEvalZero __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable radio. */ 329*150812a8SEvalZero __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sample of the receive 330*150812a8SEvalZero signal strength. */ 331*150812a8SEvalZero __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement. */ 332*150812a8SEvalZero __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter. */ 333*150812a8SEvalZero __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter. */ 334*150812a8SEvalZero __IM uint32_t RESERVED[55]; 335*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) Ready event. */ 336*150812a8SEvalZero __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address event. */ 337*150812a8SEvalZero __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Payload event. */ 338*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) End event. */ 339*150812a8SEvalZero __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) Disable event. */ 340*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 341*150812a8SEvalZero packet. */ 342*150812a8SEvalZero __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 343*150812a8SEvalZero received packet. */ 344*150812a8SEvalZero __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of the receive signal strength complete. 345*150812a8SEvalZero A new RSSI sample is ready for readout at 346*150812a8SEvalZero the RSSISAMPLE register. */ 347*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 348*150812a8SEvalZero __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value specified 349*150812a8SEvalZero in BCC register. */ 350*150812a8SEvalZero __IM uint32_t RESERVED2[53]; 351*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the radio. */ 352*150812a8SEvalZero __IM uint32_t RESERVED3[64]; 353*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 354*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 355*150812a8SEvalZero __IM uint32_t RESERVED4[61]; 356*150812a8SEvalZero __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status of received packet. */ 357*150812a8SEvalZero __IM uint32_t RESERVED5; 358*150812a8SEvalZero __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address. */ 359*150812a8SEvalZero __IM uint32_t RXCRC; /*!< (@ 0x0000040C) Received CRC. */ 360*150812a8SEvalZero __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index. */ 361*150812a8SEvalZero __IM uint32_t RESERVED6[60]; 362*150812a8SEvalZero __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer. Decision point: START task. */ 363*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency. */ 364*150812a8SEvalZero __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power. */ 365*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation. */ 366*150812a8SEvalZero __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration 0. */ 367*150812a8SEvalZero __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration 1. */ 368*150812a8SEvalZero __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Radio base address 0. Decision point: START task. */ 369*150812a8SEvalZero __IOM uint32_t BASE1; /*!< (@ 0x00000520) Radio base address 1. Decision point: START task. */ 370*150812a8SEvalZero __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0 to 3. */ 371*150812a8SEvalZero __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4 to 7. */ 372*150812a8SEvalZero __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select. */ 373*150812a8SEvalZero __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select. */ 374*150812a8SEvalZero __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration. */ 375*150812a8SEvalZero __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial. */ 376*150812a8SEvalZero __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value. */ 377*150812a8SEvalZero __IOM uint32_t TEST; /*!< (@ 0x00000540) Test features enable register. */ 378*150812a8SEvalZero __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in microseconds. */ 379*150812a8SEvalZero __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample. */ 380*150812a8SEvalZero __IM uint32_t RESERVED7; 381*150812a8SEvalZero __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state. */ 382*150812a8SEvalZero __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value. */ 383*150812a8SEvalZero __IM uint32_t RESERVED8[2]; 384*150812a8SEvalZero __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare. */ 385*150812a8SEvalZero __IM uint32_t RESERVED9[39]; 386*150812a8SEvalZero __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Device address base segment. */ 387*150812a8SEvalZero __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Device address prefix. */ 388*150812a8SEvalZero __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration. */ 389*150812a8SEvalZero __IM uint32_t RESERVED10[56]; 390*150812a8SEvalZero __IOM uint32_t OVERRIDE0; /*!< (@ 0x00000724) Trim value override register 0. */ 391*150812a8SEvalZero __IOM uint32_t OVERRIDE1; /*!< (@ 0x00000728) Trim value override register 1. */ 392*150812a8SEvalZero __IOM uint32_t OVERRIDE2; /*!< (@ 0x0000072C) Trim value override register 2. */ 393*150812a8SEvalZero __IOM uint32_t OVERRIDE3; /*!< (@ 0x00000730) Trim value override register 3. */ 394*150812a8SEvalZero __IOM uint32_t OVERRIDE4; /*!< (@ 0x00000734) Trim value override register 4. */ 395*150812a8SEvalZero __IM uint32_t RESERVED11[561]; 396*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 397*150812a8SEvalZero } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 398*150812a8SEvalZero 399*150812a8SEvalZero 400*150812a8SEvalZero 401*150812a8SEvalZero /* =========================================================================================================================== */ 402*150812a8SEvalZero /* ================ UART0 ================ */ 403*150812a8SEvalZero /* =========================================================================================================================== */ 404*150812a8SEvalZero 405*150812a8SEvalZero 406*150812a8SEvalZero /** 407*150812a8SEvalZero * @brief Universal Asynchronous Receiver/Transmitter. (UART0) 408*150812a8SEvalZero */ 409*150812a8SEvalZero 410*150812a8SEvalZero typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 411*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver. */ 412*150812a8SEvalZero __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver. */ 413*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter. */ 414*150812a8SEvalZero __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter. */ 415*150812a8SEvalZero __IM uint32_t RESERVED[3]; 416*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART. */ 417*150812a8SEvalZero __IM uint32_t RESERVED1[56]; 418*150812a8SEvalZero __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS activated. */ 419*150812a8SEvalZero __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS deactivated. */ 420*150812a8SEvalZero __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD. */ 421*150812a8SEvalZero __IM uint32_t RESERVED2[4]; 422*150812a8SEvalZero __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD. */ 423*150812a8SEvalZero __IM uint32_t RESERVED3; 424*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected. */ 425*150812a8SEvalZero __IM uint32_t RESERVED4[7]; 426*150812a8SEvalZero __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout. */ 427*150812a8SEvalZero __IM uint32_t RESERVED5[46]; 428*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for UART. */ 429*150812a8SEvalZero __IM uint32_t RESERVED6[64]; 430*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 431*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 432*150812a8SEvalZero __IM uint32_t RESERVED7[93]; 433*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field to 1 to clear 434*150812a8SEvalZero error. */ 435*150812a8SEvalZero __IM uint32_t RESERVED8[31]; 436*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART and acquire IOs. */ 437*150812a8SEvalZero __IM uint32_t RESERVED9; 438*150812a8SEvalZero __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS. */ 439*150812a8SEvalZero __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD. */ 440*150812a8SEvalZero __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS. */ 441*150812a8SEvalZero __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD. */ 442*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. On read action the buffer pointer 443*150812a8SEvalZero is displaced. Once read the character is 444*150812a8SEvalZero consumed. If read when no character available, 445*150812a8SEvalZero the UART will stop working. */ 446*150812a8SEvalZero __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register. */ 447*150812a8SEvalZero __IM uint32_t RESERVED10; 448*150812a8SEvalZero __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) UART Baudrate. */ 449*150812a8SEvalZero __IM uint32_t RESERVED11[17]; 450*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control 451*150812a8SEvalZero register. */ 452*150812a8SEvalZero __IM uint32_t RESERVED12[675]; 453*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 454*150812a8SEvalZero } NRF_UART_Type; /*!< Size = 4096 (0x1000) */ 455*150812a8SEvalZero 456*150812a8SEvalZero 457*150812a8SEvalZero 458*150812a8SEvalZero /* =========================================================================================================================== */ 459*150812a8SEvalZero /* ================ SPI0 ================ */ 460*150812a8SEvalZero /* =========================================================================================================================== */ 461*150812a8SEvalZero 462*150812a8SEvalZero 463*150812a8SEvalZero /** 464*150812a8SEvalZero * @brief SPI master 0. (SPI0) 465*150812a8SEvalZero */ 466*150812a8SEvalZero 467*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 468*150812a8SEvalZero __IM uint32_t RESERVED[66]; 469*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received. */ 470*150812a8SEvalZero __IM uint32_t RESERVED1[126]; 471*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 472*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 473*150812a8SEvalZero __IM uint32_t RESERVED2[125]; 474*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI. */ 475*150812a8SEvalZero __IM uint32_t RESERVED3; 476*150812a8SEvalZero __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ 477*150812a8SEvalZero __IOM uint32_t PSELMOSI; /*!< (@ 0x0000050C) Pin select for MOSI. */ 478*150812a8SEvalZero __IOM uint32_t PSELMISO; /*!< (@ 0x00000510) Pin select for MISO. */ 479*150812a8SEvalZero __IM uint32_t RESERVED4; 480*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RX data. */ 481*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data. */ 482*150812a8SEvalZero __IM uint32_t RESERVED5; 483*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ 484*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 485*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ 486*150812a8SEvalZero __IM uint32_t RESERVED7[681]; 487*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 488*150812a8SEvalZero } NRF_SPI_Type; /*!< Size = 4096 (0x1000) */ 489*150812a8SEvalZero 490*150812a8SEvalZero 491*150812a8SEvalZero 492*150812a8SEvalZero /* =========================================================================================================================== */ 493*150812a8SEvalZero /* ================ TWI0 ================ */ 494*150812a8SEvalZero /* =========================================================================================================================== */ 495*150812a8SEvalZero 496*150812a8SEvalZero 497*150812a8SEvalZero /** 498*150812a8SEvalZero * @brief Two-wire interface master 0. (TWI0) 499*150812a8SEvalZero */ 500*150812a8SEvalZero 501*150812a8SEvalZero typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 502*150812a8SEvalZero __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start 2-Wire master receive sequence. */ 503*150812a8SEvalZero __IM uint32_t RESERVED; 504*150812a8SEvalZero __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start 2-Wire master transmit sequence. */ 505*150812a8SEvalZero __IM uint32_t RESERVED1[2]; 506*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop 2-Wire transaction. */ 507*150812a8SEvalZero __IM uint32_t RESERVED2; 508*150812a8SEvalZero __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend 2-Wire transaction. */ 509*150812a8SEvalZero __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume 2-Wire transaction. */ 510*150812a8SEvalZero __IM uint32_t RESERVED3[56]; 511*150812a8SEvalZero __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Two-wire stopped. */ 512*150812a8SEvalZero __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) Two-wire ready to deliver new RXD byte received. */ 513*150812a8SEvalZero __IM uint32_t RESERVED4[4]; 514*150812a8SEvalZero __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) Two-wire finished sending last TXD byte. */ 515*150812a8SEvalZero __IM uint32_t RESERVED5; 516*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Two-wire error detected. */ 517*150812a8SEvalZero __IM uint32_t RESERVED6[4]; 518*150812a8SEvalZero __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) Two-wire byte boundary. */ 519*150812a8SEvalZero __IM uint32_t RESERVED7[3]; 520*150812a8SEvalZero __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Two-wire suspended. */ 521*150812a8SEvalZero __IM uint32_t RESERVED8[45]; 522*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for TWI. */ 523*150812a8SEvalZero __IM uint32_t RESERVED9[64]; 524*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 525*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 526*150812a8SEvalZero __IM uint32_t RESERVED10[110]; 527*150812a8SEvalZero __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write error field to 1 528*150812a8SEvalZero to clear error. */ 529*150812a8SEvalZero __IM uint32_t RESERVED11[14]; 530*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable two-wire master. */ 531*150812a8SEvalZero __IM uint32_t RESERVED12; 532*150812a8SEvalZero __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL. */ 533*150812a8SEvalZero __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA. */ 534*150812a8SEvalZero __IM uint32_t RESERVED13[2]; 535*150812a8SEvalZero __IM uint32_t RXD; /*!< (@ 0x00000518) RX data register. */ 536*150812a8SEvalZero __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data register. */ 537*150812a8SEvalZero __IM uint32_t RESERVED14; 538*150812a8SEvalZero __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) Two-wire frequency. */ 539*150812a8SEvalZero __IM uint32_t RESERVED15[24]; 540*150812a8SEvalZero __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the two-wire transfer. */ 541*150812a8SEvalZero __IM uint32_t RESERVED16[668]; 542*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 543*150812a8SEvalZero } NRF_TWI_Type; /*!< Size = 4096 (0x1000) */ 544*150812a8SEvalZero 545*150812a8SEvalZero 546*150812a8SEvalZero 547*150812a8SEvalZero /* =========================================================================================================================== */ 548*150812a8SEvalZero /* ================ SPIS1 ================ */ 549*150812a8SEvalZero /* =========================================================================================================================== */ 550*150812a8SEvalZero 551*150812a8SEvalZero 552*150812a8SEvalZero /** 553*150812a8SEvalZero * @brief SPI slave 1. (SPIS1) 554*150812a8SEvalZero */ 555*150812a8SEvalZero 556*150812a8SEvalZero typedef struct { /*!< (@ 0x40004000) SPIS1 Structure */ 557*150812a8SEvalZero __IM uint32_t RESERVED[9]; 558*150812a8SEvalZero __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore. */ 559*150812a8SEvalZero __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore. */ 560*150812a8SEvalZero __IM uint32_t RESERVED1[54]; 561*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed. */ 562*150812a8SEvalZero __IM uint32_t RESERVED2[2]; 563*150812a8SEvalZero __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 564*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 565*150812a8SEvalZero __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired. */ 566*150812a8SEvalZero __IM uint32_t RESERVED4[53]; 567*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for SPIS. */ 568*150812a8SEvalZero __IM uint32_t RESERVED5[64]; 569*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 570*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 571*150812a8SEvalZero __IM uint32_t RESERVED6[61]; 572*150812a8SEvalZero __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status. */ 573*150812a8SEvalZero __IM uint32_t RESERVED7[15]; 574*150812a8SEvalZero __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction. */ 575*150812a8SEvalZero __IM uint32_t RESERVED8[47]; 576*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIS. */ 577*150812a8SEvalZero __IM uint32_t RESERVED9; 578*150812a8SEvalZero __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ 579*150812a8SEvalZero __IOM uint32_t PSELMISO; /*!< (@ 0x0000050C) Pin select for MISO. */ 580*150812a8SEvalZero __IOM uint32_t PSELMOSI; /*!< (@ 0x00000510) Pin select for MOSI. */ 581*150812a8SEvalZero __IOM uint32_t PSELCSN; /*!< (@ 0x00000514) Pin select for CSN. */ 582*150812a8SEvalZero __IM uint32_t RESERVED10[7]; 583*150812a8SEvalZero __IOM uint32_t RXDPTR; /*!< (@ 0x00000534) RX data pointer. */ 584*150812a8SEvalZero __IOM uint32_t MAXRX; /*!< (@ 0x00000538) Maximum number of bytes in the receive buffer. */ 585*150812a8SEvalZero __IM uint32_t AMOUNTRX; /*!< (@ 0x0000053C) Number of bytes received in last granted transaction. */ 586*150812a8SEvalZero __IM uint32_t RESERVED11; 587*150812a8SEvalZero __IOM uint32_t TXDPTR; /*!< (@ 0x00000544) TX data pointer. */ 588*150812a8SEvalZero __IOM uint32_t MAXTX; /*!< (@ 0x00000548) Maximum number of bytes in the transmit buffer. */ 589*150812a8SEvalZero __IM uint32_t AMOUNTTX; /*!< (@ 0x0000054C) Number of bytes transmitted in last granted transaction. */ 590*150812a8SEvalZero __IM uint32_t RESERVED12; 591*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ 592*150812a8SEvalZero __IM uint32_t RESERVED13; 593*150812a8SEvalZero __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. */ 594*150812a8SEvalZero __IM uint32_t RESERVED14[24]; 595*150812a8SEvalZero __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. */ 596*150812a8SEvalZero __IM uint32_t RESERVED15[654]; 597*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 598*150812a8SEvalZero } NRF_SPIS_Type; /*!< Size = 4096 (0x1000) */ 599*150812a8SEvalZero 600*150812a8SEvalZero 601*150812a8SEvalZero 602*150812a8SEvalZero /* =========================================================================================================================== */ 603*150812a8SEvalZero /* ================ GPIOTE ================ */ 604*150812a8SEvalZero /* =========================================================================================================================== */ 605*150812a8SEvalZero 606*150812a8SEvalZero 607*150812a8SEvalZero /** 608*150812a8SEvalZero * @brief GPIO tasks and events. (GPIOTE) 609*150812a8SEvalZero */ 610*150812a8SEvalZero 611*150812a8SEvalZero typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 612*150812a8SEvalZero __OM uint32_t TASKS_OUT[4]; /*!< (@ 0x00000000) Tasks asssociated with GPIOTE channels. */ 613*150812a8SEvalZero __IM uint32_t RESERVED[60]; 614*150812a8SEvalZero __IOM uint32_t EVENTS_IN[4]; /*!< (@ 0x00000100) Tasks asssociated with GPIOTE channels. */ 615*150812a8SEvalZero __IM uint32_t RESERVED1[27]; 616*150812a8SEvalZero __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple pins. */ 617*150812a8SEvalZero __IM uint32_t RESERVED2[97]; 618*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 619*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 620*150812a8SEvalZero __IM uint32_t RESERVED3[129]; 621*150812a8SEvalZero __IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers. */ 622*150812a8SEvalZero __IM uint32_t RESERVED4[695]; 623*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 624*150812a8SEvalZero } NRF_GPIOTE_Type; /*!< Size = 4096 (0x1000) */ 625*150812a8SEvalZero 626*150812a8SEvalZero 627*150812a8SEvalZero 628*150812a8SEvalZero /* =========================================================================================================================== */ 629*150812a8SEvalZero /* ================ ADC ================ */ 630*150812a8SEvalZero /* =========================================================================================================================== */ 631*150812a8SEvalZero 632*150812a8SEvalZero 633*150812a8SEvalZero /** 634*150812a8SEvalZero * @brief Analog to digital converter. (ADC) 635*150812a8SEvalZero */ 636*150812a8SEvalZero 637*150812a8SEvalZero typedef struct { /*!< (@ 0x40007000) ADC Structure */ 638*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start an ADC conversion. */ 639*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop ADC. */ 640*150812a8SEvalZero __IM uint32_t RESERVED[62]; 641*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ADC conversion complete. */ 642*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 643*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 644*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 645*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 646*150812a8SEvalZero __IM uint32_t BUSY; /*!< (@ 0x00000400) ADC busy register. */ 647*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 648*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) ADC enable. */ 649*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. */ 650*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000508) Result of ADC conversion. */ 651*150812a8SEvalZero __IM uint32_t RESERVED4[700]; 652*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 653*150812a8SEvalZero } NRF_ADC_Type; /*!< Size = 4096 (0x1000) */ 654*150812a8SEvalZero 655*150812a8SEvalZero 656*150812a8SEvalZero 657*150812a8SEvalZero /* =========================================================================================================================== */ 658*150812a8SEvalZero /* ================ TIMER0 ================ */ 659*150812a8SEvalZero /* =========================================================================================================================== */ 660*150812a8SEvalZero 661*150812a8SEvalZero 662*150812a8SEvalZero /** 663*150812a8SEvalZero * @brief Timer 0. (TIMER0) 664*150812a8SEvalZero */ 665*150812a8SEvalZero 666*150812a8SEvalZero typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 667*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer. */ 668*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer. */ 669*150812a8SEvalZero __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (In counter mode). */ 670*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear timer. */ 671*150812a8SEvalZero __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shutdown timer. */ 672*150812a8SEvalZero __IM uint32_t RESERVED[11]; 673*150812a8SEvalZero __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Capture Timer value to CC[n] registers. */ 674*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 675*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ 676*150812a8SEvalZero __IM uint32_t RESERVED2[44]; 677*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for Timer. */ 678*150812a8SEvalZero __IM uint32_t RESERVED3[64]; 679*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 680*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 681*150812a8SEvalZero __IM uint32_t RESERVED4[126]; 682*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer Mode selection. */ 683*150812a8SEvalZero __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Sets timer behaviour. */ 684*150812a8SEvalZero __IM uint32_t RESERVED5; 685*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) 4-bit prescaler to source clock frequency (max 686*150812a8SEvalZero value 9). Source clock frequency is divided 687*150812a8SEvalZero by 2^SCALE. */ 688*150812a8SEvalZero __IM uint32_t RESERVED6[11]; 689*150812a8SEvalZero __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ 690*150812a8SEvalZero __IM uint32_t RESERVED7[683]; 691*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 692*150812a8SEvalZero } NRF_TIMER_Type; /*!< Size = 4096 (0x1000) */ 693*150812a8SEvalZero 694*150812a8SEvalZero 695*150812a8SEvalZero 696*150812a8SEvalZero /* =========================================================================================================================== */ 697*150812a8SEvalZero /* ================ RTC0 ================ */ 698*150812a8SEvalZero /* =========================================================================================================================== */ 699*150812a8SEvalZero 700*150812a8SEvalZero 701*150812a8SEvalZero /** 702*150812a8SEvalZero * @brief Real time counter 0. (RTC0) 703*150812a8SEvalZero */ 704*150812a8SEvalZero 705*150812a8SEvalZero typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 706*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC Counter. */ 707*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC Counter. */ 708*150812a8SEvalZero __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC Counter. */ 709*150812a8SEvalZero __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFFFF0. */ 710*150812a8SEvalZero __IM uint32_t RESERVED[60]; 711*150812a8SEvalZero __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment. */ 712*150812a8SEvalZero __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow. */ 713*150812a8SEvalZero __IM uint32_t RESERVED1[14]; 714*150812a8SEvalZero __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ 715*150812a8SEvalZero __IM uint32_t RESERVED2[109]; 716*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 717*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 718*150812a8SEvalZero __IM uint32_t RESERVED3[13]; 719*150812a8SEvalZero __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each 720*150812a8SEvalZero RTC event. */ 721*150812a8SEvalZero __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. The reading of 722*150812a8SEvalZero this register gives the value of EVTEN. */ 723*150812a8SEvalZero __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. The reading of 724*150812a8SEvalZero this register gives the value of EVTEN. */ 725*150812a8SEvalZero __IM uint32_t RESERVED4[110]; 726*150812a8SEvalZero __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value. */ 727*150812a8SEvalZero __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 728*150812a8SEvalZero Must be written when RTC is STOPed. */ 729*150812a8SEvalZero __IM uint32_t RESERVED5[13]; 730*150812a8SEvalZero __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ 731*150812a8SEvalZero __IM uint32_t RESERVED6[683]; 732*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 733*150812a8SEvalZero } NRF_RTC_Type; /*!< Size = 4096 (0x1000) */ 734*150812a8SEvalZero 735*150812a8SEvalZero 736*150812a8SEvalZero 737*150812a8SEvalZero /* =========================================================================================================================== */ 738*150812a8SEvalZero /* ================ TEMP ================ */ 739*150812a8SEvalZero /* =========================================================================================================================== */ 740*150812a8SEvalZero 741*150812a8SEvalZero 742*150812a8SEvalZero /** 743*150812a8SEvalZero * @brief Temperature Sensor. (TEMP) 744*150812a8SEvalZero */ 745*150812a8SEvalZero 746*150812a8SEvalZero typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 747*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement. */ 748*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement. */ 749*150812a8SEvalZero __IM uint32_t RESERVED[62]; 750*150812a8SEvalZero __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready 751*150812a8SEvalZero event. */ 752*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 753*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 754*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 755*150812a8SEvalZero __IM uint32_t RESERVED2[127]; 756*150812a8SEvalZero __IM int32_t TEMP; /*!< (@ 0x00000508) Die temperature in degC, 2's complement format, 757*150812a8SEvalZero 0.25 degC pecision. */ 758*150812a8SEvalZero __IM uint32_t RESERVED3[700]; 759*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 760*150812a8SEvalZero } NRF_TEMP_Type; /*!< Size = 4096 (0x1000) */ 761*150812a8SEvalZero 762*150812a8SEvalZero 763*150812a8SEvalZero 764*150812a8SEvalZero /* =========================================================================================================================== */ 765*150812a8SEvalZero /* ================ RNG ================ */ 766*150812a8SEvalZero /* =========================================================================================================================== */ 767*150812a8SEvalZero 768*150812a8SEvalZero 769*150812a8SEvalZero /** 770*150812a8SEvalZero * @brief Random Number Generator. (RNG) 771*150812a8SEvalZero */ 772*150812a8SEvalZero 773*150812a8SEvalZero typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 774*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the random number generator. */ 775*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the random number generator. */ 776*150812a8SEvalZero __IM uint32_t RESERVED[62]; 777*150812a8SEvalZero __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) New random number generated and written to VALUE 778*150812a8SEvalZero register. */ 779*150812a8SEvalZero __IM uint32_t RESERVED1[63]; 780*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the RNG. */ 781*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 782*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register */ 783*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register */ 784*150812a8SEvalZero __IM uint32_t RESERVED3[126]; 785*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ 786*150812a8SEvalZero __IM uint32_t VALUE; /*!< (@ 0x00000508) RNG random number. */ 787*150812a8SEvalZero __IM uint32_t RESERVED4[700]; 788*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 789*150812a8SEvalZero } NRF_RNG_Type; /*!< Size = 4096 (0x1000) */ 790*150812a8SEvalZero 791*150812a8SEvalZero 792*150812a8SEvalZero 793*150812a8SEvalZero /* =========================================================================================================================== */ 794*150812a8SEvalZero /* ================ ECB ================ */ 795*150812a8SEvalZero /* =========================================================================================================================== */ 796*150812a8SEvalZero 797*150812a8SEvalZero 798*150812a8SEvalZero /** 799*150812a8SEvalZero * @brief AES ECB Mode Encryption. (ECB) 800*150812a8SEvalZero */ 801*150812a8SEvalZero 802*150812a8SEvalZero typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 803*150812a8SEvalZero __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a crypto operation 804*150812a8SEvalZero is running, this will not initiate a new 805*150812a8SEvalZero encryption and the ERRORECB event will be 806*150812a8SEvalZero triggered. */ 807*150812a8SEvalZero __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If a crypto operation 808*150812a8SEvalZero is running, this will will trigger the ERRORECB 809*150812a8SEvalZero event. */ 810*150812a8SEvalZero __IM uint32_t RESERVED[62]; 811*150812a8SEvalZero __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete. */ 812*150812a8SEvalZero __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted due to a STOPECB task 813*150812a8SEvalZero or due to an error. */ 814*150812a8SEvalZero __IM uint32_t RESERVED1[127]; 815*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 816*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 817*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 818*150812a8SEvalZero __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointer. */ 819*150812a8SEvalZero __IM uint32_t RESERVED3[701]; 820*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 821*150812a8SEvalZero } NRF_ECB_Type; /*!< Size = 4096 (0x1000) */ 822*150812a8SEvalZero 823*150812a8SEvalZero 824*150812a8SEvalZero 825*150812a8SEvalZero /* =========================================================================================================================== */ 826*150812a8SEvalZero /* ================ AAR ================ */ 827*150812a8SEvalZero /* =========================================================================================================================== */ 828*150812a8SEvalZero 829*150812a8SEvalZero 830*150812a8SEvalZero /** 831*150812a8SEvalZero * @brief Accelerated Address Resolver. (AAR) 832*150812a8SEvalZero */ 833*150812a8SEvalZero 834*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 835*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 836*150812a8SEvalZero in the IRK data structure. */ 837*150812a8SEvalZero __IM uint32_t RESERVED; 838*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses. */ 839*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 840*150812a8SEvalZero __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure completed. */ 841*150812a8SEvalZero __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved. */ 842*150812a8SEvalZero __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved. */ 843*150812a8SEvalZero __IM uint32_t RESERVED2[126]; 844*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 845*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 846*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 847*150812a8SEvalZero __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status. */ 848*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 849*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR. */ 850*150812a8SEvalZero __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of Identity root Keys in the IRK data 851*150812a8SEvalZero structure. */ 852*150812a8SEvalZero __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to the IRK data structure. */ 853*150812a8SEvalZero __IM uint32_t RESERVED5; 854*150812a8SEvalZero __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address (6 bytes). */ 855*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary 856*150812a8SEvalZero storage during resolution. A minimum of 857*150812a8SEvalZero 3 bytes must be reserved. */ 858*150812a8SEvalZero __IM uint32_t RESERVED6[697]; 859*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 860*150812a8SEvalZero } NRF_AAR_Type; /*!< Size = 4096 (0x1000) */ 861*150812a8SEvalZero 862*150812a8SEvalZero 863*150812a8SEvalZero 864*150812a8SEvalZero /* =========================================================================================================================== */ 865*150812a8SEvalZero /* ================ CCM ================ */ 866*150812a8SEvalZero /* =========================================================================================================================== */ 867*150812a8SEvalZero 868*150812a8SEvalZero 869*150812a8SEvalZero /** 870*150812a8SEvalZero * @brief AES CCM Mode Encryption. (CCM) 871*150812a8SEvalZero */ 872*150812a8SEvalZero 873*150812a8SEvalZero typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 874*150812a8SEvalZero __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 875*150812a8SEvalZero will stop by itself when completed. */ 876*150812a8SEvalZero __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This operation will stop 877*150812a8SEvalZero by itself when completed. */ 878*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encrypt/decrypt. */ 879*150812a8SEvalZero __IM uint32_t RESERVED[61]; 880*150812a8SEvalZero __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation completed. */ 881*150812a8SEvalZero __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt completed. */ 882*150812a8SEvalZero __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Error happened. */ 883*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 884*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the CCM. */ 885*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 886*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 887*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 888*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 889*150812a8SEvalZero __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) CCM RX MIC check result. */ 890*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 891*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) CCM enable. */ 892*150812a8SEvalZero __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode. */ 893*150812a8SEvalZero __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to a data structure holding AES key and 894*150812a8SEvalZero NONCE vector. */ 895*150812a8SEvalZero __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Pointer to the input packet. */ 896*150812a8SEvalZero __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Pointer to the output packet. */ 897*150812a8SEvalZero __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary 898*150812a8SEvalZero storage during resolution. A minimum of 899*150812a8SEvalZero 43 bytes must be reserved. */ 900*150812a8SEvalZero __IM uint32_t RESERVED5[697]; 901*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 902*150812a8SEvalZero } NRF_CCM_Type; /*!< Size = 4096 (0x1000) */ 903*150812a8SEvalZero 904*150812a8SEvalZero 905*150812a8SEvalZero 906*150812a8SEvalZero /* =========================================================================================================================== */ 907*150812a8SEvalZero /* ================ WDT ================ */ 908*150812a8SEvalZero /* =========================================================================================================================== */ 909*150812a8SEvalZero 910*150812a8SEvalZero 911*150812a8SEvalZero /** 912*150812a8SEvalZero * @brief Watchdog Timer. (WDT) 913*150812a8SEvalZero */ 914*150812a8SEvalZero 915*150812a8SEvalZero typedef struct { /*!< (@ 0x40010000) WDT Structure */ 916*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog. */ 917*150812a8SEvalZero __IM uint32_t RESERVED[63]; 918*150812a8SEvalZero __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout. */ 919*150812a8SEvalZero __IM uint32_t RESERVED1[128]; 920*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 921*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 922*150812a8SEvalZero __IM uint32_t RESERVED2[61]; 923*150812a8SEvalZero __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Watchdog running status. */ 924*150812a8SEvalZero __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status. */ 925*150812a8SEvalZero __IM uint32_t RESERVED3[63]; 926*150812a8SEvalZero __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value in number of 32kiHz clock 927*150812a8SEvalZero cycles. */ 928*150812a8SEvalZero __IOM uint32_t RREN; /*!< (@ 0x00000508) Reload request enable. */ 929*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. */ 930*150812a8SEvalZero __IM uint32_t RESERVED4[60]; 931*150812a8SEvalZero __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload requests registers. */ 932*150812a8SEvalZero __IM uint32_t RESERVED5[631]; 933*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 934*150812a8SEvalZero } NRF_WDT_Type; /*!< Size = 4096 (0x1000) */ 935*150812a8SEvalZero 936*150812a8SEvalZero 937*150812a8SEvalZero 938*150812a8SEvalZero /* =========================================================================================================================== */ 939*150812a8SEvalZero /* ================ QDEC ================ */ 940*150812a8SEvalZero /* =========================================================================================================================== */ 941*150812a8SEvalZero 942*150812a8SEvalZero 943*150812a8SEvalZero /** 944*150812a8SEvalZero * @brief Rotary decoder. (QDEC) 945*150812a8SEvalZero */ 946*150812a8SEvalZero 947*150812a8SEvalZero typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 948*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the quadrature decoder. */ 949*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the quadrature decoder. */ 950*150812a8SEvalZero __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Transfers the content from ACC registers to ACCREAD 951*150812a8SEvalZero registers, and clears the ACC registers. */ 952*150812a8SEvalZero __IM uint32_t RESERVED[61]; 953*150812a8SEvalZero __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) A new sample is written to the sample register. */ 954*150812a8SEvalZero __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) REPORTPER number of samples accumulated in ACC 955*150812a8SEvalZero register, and ACC register different than 956*150812a8SEvalZero zero. */ 957*150812a8SEvalZero __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow. */ 958*150812a8SEvalZero __IM uint32_t RESERVED1[61]; 959*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the QDEC. */ 960*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 961*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 962*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 963*150812a8SEvalZero __IM uint32_t RESERVED3[125]; 964*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the QDEC. */ 965*150812a8SEvalZero __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity. */ 966*150812a8SEvalZero __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period. */ 967*150812a8SEvalZero __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value. */ 968*150812a8SEvalZero __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to generate an EVENT_REPORTRDY. */ 969*150812a8SEvalZero __IM int32_t ACC; /*!< (@ 0x00000514) Accumulated valid transitions register. */ 970*150812a8SEvalZero __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of ACC register. Value generated by 971*150812a8SEvalZero the TASKS_READCLEACC task. */ 972*150812a8SEvalZero __IOM uint32_t PSELLED; /*!< (@ 0x0000051C) Pin select for LED output. */ 973*150812a8SEvalZero __IOM uint32_t PSELA; /*!< (@ 0x00000520) Pin select for phase A input. */ 974*150812a8SEvalZero __IOM uint32_t PSELB; /*!< (@ 0x00000524) Pin select for phase B input. */ 975*150812a8SEvalZero __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable debouncer input filters. */ 976*150812a8SEvalZero __IM uint32_t RESERVED4[5]; 977*150812a8SEvalZero __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time LED is switched ON before the sample. */ 978*150812a8SEvalZero __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Accumulated double (error) transitions register. */ 979*150812a8SEvalZero __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of ACCDBL register. Value generated 980*150812a8SEvalZero by the TASKS_READCLEACC task. */ 981*150812a8SEvalZero __IM uint32_t RESERVED5[684]; 982*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 983*150812a8SEvalZero } NRF_QDEC_Type; /*!< Size = 4096 (0x1000) */ 984*150812a8SEvalZero 985*150812a8SEvalZero 986*150812a8SEvalZero 987*150812a8SEvalZero /* =========================================================================================================================== */ 988*150812a8SEvalZero /* ================ LPCOMP ================ */ 989*150812a8SEvalZero /* =========================================================================================================================== */ 990*150812a8SEvalZero 991*150812a8SEvalZero 992*150812a8SEvalZero /** 993*150812a8SEvalZero * @brief Low power comparator. (LPCOMP) 994*150812a8SEvalZero */ 995*150812a8SEvalZero 996*150812a8SEvalZero typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 997*150812a8SEvalZero __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the comparator. */ 998*150812a8SEvalZero __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the comparator. */ 999*150812a8SEvalZero __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. */ 1000*150812a8SEvalZero __IM uint32_t RESERVED[61]; 1001*150812a8SEvalZero __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid. */ 1002*150812a8SEvalZero __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Input voltage crossed the threshold going down. */ 1003*150812a8SEvalZero __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Input voltage crossed the threshold going up. */ 1004*150812a8SEvalZero __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Input voltage crossed the threshold in any direction. */ 1005*150812a8SEvalZero __IM uint32_t RESERVED1[60]; 1006*150812a8SEvalZero __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the LPCOMP. */ 1007*150812a8SEvalZero __IM uint32_t RESERVED2[64]; 1008*150812a8SEvalZero __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ 1009*150812a8SEvalZero __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ 1010*150812a8SEvalZero __IM uint32_t RESERVED3[61]; 1011*150812a8SEvalZero __IM uint32_t RESULT; /*!< (@ 0x00000400) Result of last compare. */ 1012*150812a8SEvalZero __IM uint32_t RESERVED4[63]; 1013*150812a8SEvalZero __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the LPCOMP. */ 1014*150812a8SEvalZero __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select. */ 1015*150812a8SEvalZero __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select. */ 1016*150812a8SEvalZero __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select. */ 1017*150812a8SEvalZero __IM uint32_t RESERVED5[4]; 1018*150812a8SEvalZero __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration. */ 1019*150812a8SEvalZero __IM uint32_t RESERVED6[694]; 1020*150812a8SEvalZero __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ 1021*150812a8SEvalZero } NRF_LPCOMP_Type; /*!< Size = 4096 (0x1000) */ 1022*150812a8SEvalZero 1023*150812a8SEvalZero 1024*150812a8SEvalZero 1025*150812a8SEvalZero /* =========================================================================================================================== */ 1026*150812a8SEvalZero /* ================ SWI ================ */ 1027*150812a8SEvalZero /* =========================================================================================================================== */ 1028*150812a8SEvalZero 1029*150812a8SEvalZero 1030*150812a8SEvalZero /** 1031*150812a8SEvalZero * @brief SW Interrupts. (SWI) 1032*150812a8SEvalZero */ 1033*150812a8SEvalZero 1034*150812a8SEvalZero typedef struct { /*!< (@ 0x40014000) SWI Structure */ 1035*150812a8SEvalZero __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1036*150812a8SEvalZero } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1037*150812a8SEvalZero 1038*150812a8SEvalZero 1039*150812a8SEvalZero 1040*150812a8SEvalZero /* =========================================================================================================================== */ 1041*150812a8SEvalZero /* ================ NVMC ================ */ 1042*150812a8SEvalZero /* =========================================================================================================================== */ 1043*150812a8SEvalZero 1044*150812a8SEvalZero 1045*150812a8SEvalZero /** 1046*150812a8SEvalZero * @brief Non Volatile Memory Controller. (NVMC) 1047*150812a8SEvalZero */ 1048*150812a8SEvalZero 1049*150812a8SEvalZero typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1050*150812a8SEvalZero __IM uint32_t RESERVED[256]; 1051*150812a8SEvalZero __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag. */ 1052*150812a8SEvalZero __IM uint32_t RESERVED1[64]; 1053*150812a8SEvalZero __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ 1054*150812a8SEvalZero 1055*150812a8SEvalZero union { 1056*150812a8SEvalZero __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile 1057*150812a8SEvalZero memory page. */ 1058*150812a8SEvalZero __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile 1059*150812a8SEvalZero memory page. */ 1060*150812a8SEvalZero }; 1061*150812a8SEvalZero __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory. */ 1062*150812a8SEvalZero __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Register for erasing a protected non-volatile 1063*150812a8SEvalZero memory page. */ 1064*150812a8SEvalZero __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for start erasing User Information Congfiguration 1065*150812a8SEvalZero Registers. */ 1066*150812a8SEvalZero } NRF_NVMC_Type; /*!< Size = 1304 (0x518) */ 1067*150812a8SEvalZero 1068*150812a8SEvalZero 1069*150812a8SEvalZero 1070*150812a8SEvalZero /* =========================================================================================================================== */ 1071*150812a8SEvalZero /* ================ PPI ================ */ 1072*150812a8SEvalZero /* =========================================================================================================================== */ 1073*150812a8SEvalZero 1074*150812a8SEvalZero 1075*150812a8SEvalZero /** 1076*150812a8SEvalZero * @brief PPI controller. (PPI) 1077*150812a8SEvalZero */ 1078*150812a8SEvalZero 1079*150812a8SEvalZero typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1080*150812a8SEvalZero __IOM PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks. */ 1081*150812a8SEvalZero __IM uint32_t RESERVED[312]; 1082*150812a8SEvalZero __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable. */ 1083*150812a8SEvalZero __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set. */ 1084*150812a8SEvalZero __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear. */ 1085*150812a8SEvalZero __IM uint32_t RESERVED1; 1086*150812a8SEvalZero __IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. */ 1087*150812a8SEvalZero __IM uint32_t RESERVED2[156]; 1088*150812a8SEvalZero __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group configuration. */ 1089*150812a8SEvalZero } NRF_PPI_Type; /*!< Size = 2064 (0x810) */ 1090*150812a8SEvalZero 1091*150812a8SEvalZero 1092*150812a8SEvalZero 1093*150812a8SEvalZero /* =========================================================================================================================== */ 1094*150812a8SEvalZero /* ================ FICR ================ */ 1095*150812a8SEvalZero /* =========================================================================================================================== */ 1096*150812a8SEvalZero 1097*150812a8SEvalZero 1098*150812a8SEvalZero /** 1099*150812a8SEvalZero * @brief Factory Information Configuration. (FICR) 1100*150812a8SEvalZero */ 1101*150812a8SEvalZero 1102*150812a8SEvalZero typedef struct { /*!< (@ 0x10000000) FICR Structure */ 1103*150812a8SEvalZero __IM uint32_t RESERVED[4]; 1104*150812a8SEvalZero __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size in bytes. */ 1105*150812a8SEvalZero __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size in pages. */ 1106*150812a8SEvalZero __IM uint32_t RESERVED1[4]; 1107*150812a8SEvalZero __IM uint32_t CLENR0; /*!< (@ 0x00000028) Length of code region 0 in bytes. */ 1108*150812a8SEvalZero __IM uint32_t PPFC; /*!< (@ 0x0000002C) Pre-programmed factory code present. */ 1109*150812a8SEvalZero __IM uint32_t RESERVED2; 1110*150812a8SEvalZero __IM uint32_t NUMRAMBLOCK; /*!< (@ 0x00000034) Number of individualy controllable RAM blocks. */ 1111*150812a8SEvalZero 1112*150812a8SEvalZero union { 1113*150812a8SEvalZero __IM uint32_t SIZERAMBLOCKS; /*!< (@ 0x00000038) Size of RAM blocks in bytes. */ 1114*150812a8SEvalZero __IM uint32_t SIZERAMBLOCK[4]; /*!< (@ 0x00000038) Deprecated array of size of RAM block in bytes. 1115*150812a8SEvalZero This name is kept for backward compatinility 1116*150812a8SEvalZero purposes. Use SIZERAMBLOCKS instead. */ 1117*150812a8SEvalZero }; 1118*150812a8SEvalZero __IM uint32_t RESERVED3[5]; 1119*150812a8SEvalZero __IM uint32_t CONFIGID; /*!< (@ 0x0000005C) Configuration identifier. */ 1120*150812a8SEvalZero __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Device identifier. */ 1121*150812a8SEvalZero __IM uint32_t RESERVED4[6]; 1122*150812a8SEvalZero __IM uint32_t ER[4]; /*!< (@ 0x00000080) Encryption root. */ 1123*150812a8SEvalZero __IM uint32_t IR[4]; /*!< (@ 0x00000090) Identity root. */ 1124*150812a8SEvalZero __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type. */ 1125*150812a8SEvalZero __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Device address. */ 1126*150812a8SEvalZero __IM uint32_t OVERRIDEEN; /*!< (@ 0x000000AC) Radio calibration override enable. */ 1127*150812a8SEvalZero __IM uint32_t NRF_1MBIT[5]; /*!< (@ 0x000000B0) Override values for the OVERRIDEn registers in 1128*150812a8SEvalZero RADIO for NRF_1Mbit mode. */ 1129*150812a8SEvalZero __IM uint32_t RESERVED5[10]; 1130*150812a8SEvalZero __IM uint32_t BLE_1MBIT[5]; /*!< (@ 0x000000EC) Override values for the OVERRIDEn registers in 1131*150812a8SEvalZero RADIO for BLE_1Mbit mode. */ 1132*150812a8SEvalZero } NRF_FICR_Type; /*!< Size = 256 (0x100) */ 1133*150812a8SEvalZero 1134*150812a8SEvalZero 1135*150812a8SEvalZero 1136*150812a8SEvalZero /* =========================================================================================================================== */ 1137*150812a8SEvalZero /* ================ UICR ================ */ 1138*150812a8SEvalZero /* =========================================================================================================================== */ 1139*150812a8SEvalZero 1140*150812a8SEvalZero 1141*150812a8SEvalZero /** 1142*150812a8SEvalZero * @brief User Information Configuration. (UICR) 1143*150812a8SEvalZero */ 1144*150812a8SEvalZero 1145*150812a8SEvalZero typedef struct { /*!< (@ 0x10001000) UICR Structure */ 1146*150812a8SEvalZero __IOM uint32_t CLENR0; /*!< (@ 0x00000000) Length of code region 0. */ 1147*150812a8SEvalZero __IOM uint32_t RBPCONF; /*!< (@ 0x00000004) Readback protection configuration. */ 1148*150812a8SEvalZero __IOM uint32_t XTALFREQ; /*!< (@ 0x00000008) Reset value for CLOCK XTALFREQ register. */ 1149*150812a8SEvalZero __IM uint32_t RESERVED; 1150*150812a8SEvalZero __IM uint32_t FWID; /*!< (@ 0x00000010) Firmware ID. */ 1151*150812a8SEvalZero 1152*150812a8SEvalZero union { 1153*150812a8SEvalZero __IOM uint32_t BOOTLOADERADDR; /*!< (@ 0x00000014) Bootloader start address. */ 1154*150812a8SEvalZero __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Reserved for Nordic firmware design. */ 1155*150812a8SEvalZero }; 1156*150812a8SEvalZero __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Reserved for Nordic hardware design. */ 1157*150812a8SEvalZero __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Reserved for customer. */ 1158*150812a8SEvalZero } NRF_UICR_Type; /*!< Size = 256 (0x100) */ 1159*150812a8SEvalZero 1160*150812a8SEvalZero 1161*150812a8SEvalZero 1162*150812a8SEvalZero /* =========================================================================================================================== */ 1163*150812a8SEvalZero /* ================ GPIO ================ */ 1164*150812a8SEvalZero /* =========================================================================================================================== */ 1165*150812a8SEvalZero 1166*150812a8SEvalZero 1167*150812a8SEvalZero /** 1168*150812a8SEvalZero * @brief General purpose input and output. (GPIO) 1169*150812a8SEvalZero */ 1170*150812a8SEvalZero 1171*150812a8SEvalZero typedef struct { /*!< (@ 0x50000000) GPIO Structure */ 1172*150812a8SEvalZero __IM uint32_t RESERVED[321]; 1173*150812a8SEvalZero __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port. */ 1174*150812a8SEvalZero __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port. */ 1175*150812a8SEvalZero __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port. */ 1176*150812a8SEvalZero __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port. */ 1177*150812a8SEvalZero __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins. */ 1178*150812a8SEvalZero __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register. */ 1179*150812a8SEvalZero __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register. */ 1180*150812a8SEvalZero __IM uint32_t RESERVED1[120]; 1181*150812a8SEvalZero __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Configuration of GPIO pins. */ 1182*150812a8SEvalZero } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 1183*150812a8SEvalZero 1184*150812a8SEvalZero 1185*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripherals */ 1186*150812a8SEvalZero 1187*150812a8SEvalZero 1188*150812a8SEvalZero /* =========================================================================================================================== */ 1189*150812a8SEvalZero /* ================ Device Specific Peripheral Address Map ================ */ 1190*150812a8SEvalZero /* =========================================================================================================================== */ 1191*150812a8SEvalZero 1192*150812a8SEvalZero 1193*150812a8SEvalZero /** @addtogroup Device_Peripheral_peripheralAddr 1194*150812a8SEvalZero * @{ 1195*150812a8SEvalZero */ 1196*150812a8SEvalZero 1197*150812a8SEvalZero #define NRF_POWER_BASE 0x40000000UL 1198*150812a8SEvalZero #define NRF_CLOCK_BASE 0x40000000UL 1199*150812a8SEvalZero #define NRF_MPU_BASE 0x40000000UL 1200*150812a8SEvalZero #define NRF_RADIO_BASE 0x40001000UL 1201*150812a8SEvalZero #define NRF_UART0_BASE 0x40002000UL 1202*150812a8SEvalZero #define NRF_SPI0_BASE 0x40003000UL 1203*150812a8SEvalZero #define NRF_TWI0_BASE 0x40003000UL 1204*150812a8SEvalZero #define NRF_SPI1_BASE 0x40004000UL 1205*150812a8SEvalZero #define NRF_TWI1_BASE 0x40004000UL 1206*150812a8SEvalZero #define NRF_SPIS1_BASE 0x40004000UL 1207*150812a8SEvalZero #define NRF_GPIOTE_BASE 0x40006000UL 1208*150812a8SEvalZero #define NRF_ADC_BASE 0x40007000UL 1209*150812a8SEvalZero #define NRF_TIMER0_BASE 0x40008000UL 1210*150812a8SEvalZero #define NRF_TIMER1_BASE 0x40009000UL 1211*150812a8SEvalZero #define NRF_TIMER2_BASE 0x4000A000UL 1212*150812a8SEvalZero #define NRF_RTC0_BASE 0x4000B000UL 1213*150812a8SEvalZero #define NRF_TEMP_BASE 0x4000C000UL 1214*150812a8SEvalZero #define NRF_RNG_BASE 0x4000D000UL 1215*150812a8SEvalZero #define NRF_ECB_BASE 0x4000E000UL 1216*150812a8SEvalZero #define NRF_AAR_BASE 0x4000F000UL 1217*150812a8SEvalZero #define NRF_CCM_BASE 0x4000F000UL 1218*150812a8SEvalZero #define NRF_WDT_BASE 0x40010000UL 1219*150812a8SEvalZero #define NRF_RTC1_BASE 0x40011000UL 1220*150812a8SEvalZero #define NRF_QDEC_BASE 0x40012000UL 1221*150812a8SEvalZero #define NRF_LPCOMP_BASE 0x40013000UL 1222*150812a8SEvalZero #define NRF_SWI_BASE 0x40014000UL 1223*150812a8SEvalZero #define NRF_NVMC_BASE 0x4001E000UL 1224*150812a8SEvalZero #define NRF_PPI_BASE 0x4001F000UL 1225*150812a8SEvalZero #define NRF_FICR_BASE 0x10000000UL 1226*150812a8SEvalZero #define NRF_UICR_BASE 0x10001000UL 1227*150812a8SEvalZero #define NRF_GPIO_BASE 0x50000000UL 1228*150812a8SEvalZero 1229*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1230*150812a8SEvalZero 1231*150812a8SEvalZero 1232*150812a8SEvalZero /* =========================================================================================================================== */ 1233*150812a8SEvalZero /* ================ Peripheral declaration ================ */ 1234*150812a8SEvalZero /* =========================================================================================================================== */ 1235*150812a8SEvalZero 1236*150812a8SEvalZero 1237*150812a8SEvalZero /** @addtogroup Device_Peripheral_declaration 1238*150812a8SEvalZero * @{ 1239*150812a8SEvalZero */ 1240*150812a8SEvalZero 1241*150812a8SEvalZero #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1242*150812a8SEvalZero #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1243*150812a8SEvalZero #define NRF_MPU ((NRF_MPU_Type*) NRF_MPU_BASE) 1244*150812a8SEvalZero #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1245*150812a8SEvalZero #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 1246*150812a8SEvalZero #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 1247*150812a8SEvalZero #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 1248*150812a8SEvalZero #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 1249*150812a8SEvalZero #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 1250*150812a8SEvalZero #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 1251*150812a8SEvalZero #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1252*150812a8SEvalZero #define NRF_ADC ((NRF_ADC_Type*) NRF_ADC_BASE) 1253*150812a8SEvalZero #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1254*150812a8SEvalZero #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1255*150812a8SEvalZero #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1256*150812a8SEvalZero #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1257*150812a8SEvalZero #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1258*150812a8SEvalZero #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1259*150812a8SEvalZero #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1260*150812a8SEvalZero #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1261*150812a8SEvalZero #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1262*150812a8SEvalZero #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1263*150812a8SEvalZero #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1264*150812a8SEvalZero #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1265*150812a8SEvalZero #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 1266*150812a8SEvalZero #define NRF_SWI ((NRF_SWI_Type*) NRF_SWI_BASE) 1267*150812a8SEvalZero #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1268*150812a8SEvalZero #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1269*150812a8SEvalZero #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1270*150812a8SEvalZero #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1271*150812a8SEvalZero #define NRF_GPIO ((NRF_GPIO_Type*) NRF_GPIO_BASE) 1272*150812a8SEvalZero 1273*150812a8SEvalZero /** @} */ /* End of group Device_Peripheral_declaration */ 1274*150812a8SEvalZero 1275*150812a8SEvalZero 1276*150812a8SEvalZero /* ========================================= End of section using anonymous unions ========================================= */ 1277*150812a8SEvalZero #if defined (__CC_ARM) 1278*150812a8SEvalZero #pragma pop 1279*150812a8SEvalZero #elif defined (__ICCARM__) 1280*150812a8SEvalZero /* leave anonymous unions enabled */ 1281*150812a8SEvalZero #elif (__ARMCC_VERSION >= 6010050) 1282*150812a8SEvalZero #pragma clang diagnostic pop 1283*150812a8SEvalZero #elif defined (__GNUC__) 1284*150812a8SEvalZero /* anonymous unions are enabled by default */ 1285*150812a8SEvalZero #elif defined (__TMS470__) 1286*150812a8SEvalZero /* anonymous unions are enabled by default */ 1287*150812a8SEvalZero #elif defined (__TASKING__) 1288*150812a8SEvalZero #pragma warning restore 1289*150812a8SEvalZero #elif defined (__CSMC__) 1290*150812a8SEvalZero /* anonymous unions are enabled by default */ 1291*150812a8SEvalZero #endif 1292*150812a8SEvalZero 1293*150812a8SEvalZero 1294*150812a8SEvalZero #ifdef __cplusplus 1295*150812a8SEvalZero } 1296*150812a8SEvalZero #endif 1297*150812a8SEvalZero 1298*150812a8SEvalZero #endif /* NRF51_H */ 1299*150812a8SEvalZero 1300*150812a8SEvalZero 1301*150812a8SEvalZero /** @} */ /* End of group nrf51 */ 1302*150812a8SEvalZero 1303*150812a8SEvalZero /** @} */ /* End of group Nordic Semiconductor */ 1304