1*150812a8SEvalZero /*
2*150812a8SEvalZero * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
3*150812a8SEvalZero * All rights reserved.
4*150812a8SEvalZero *
5*150812a8SEvalZero * Redistribution and use in source and binary forms, with or without
6*150812a8SEvalZero * modification, are permitted provided that the following conditions are met:
7*150812a8SEvalZero *
8*150812a8SEvalZero * 1. Redistributions of source code must retain the above copyright notice, this
9*150812a8SEvalZero * list of conditions and the following disclaimer.
10*150812a8SEvalZero *
11*150812a8SEvalZero * 2. Redistributions in binary form must reproduce the above copyright
12*150812a8SEvalZero * notice, this list of conditions and the following disclaimer in the
13*150812a8SEvalZero * documentation and/or other materials provided with the distribution.
14*150812a8SEvalZero *
15*150812a8SEvalZero * 3. Neither the name of the copyright holder nor the names of its
16*150812a8SEvalZero * contributors may be used to endorse or promote products derived from this
17*150812a8SEvalZero * software without specific prior written permission.
18*150812a8SEvalZero *
19*150812a8SEvalZero * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20*150812a8SEvalZero * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21*150812a8SEvalZero * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22*150812a8SEvalZero * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23*150812a8SEvalZero * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24*150812a8SEvalZero * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25*150812a8SEvalZero * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26*150812a8SEvalZero * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27*150812a8SEvalZero * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28*150812a8SEvalZero * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29*150812a8SEvalZero * POSSIBILITY OF SUCH DAMAGE.
30*150812a8SEvalZero */
31*150812a8SEvalZero
32*150812a8SEvalZero #ifndef NRFX_PWM_H__
33*150812a8SEvalZero #define NRFX_PWM_H__
34*150812a8SEvalZero
35*150812a8SEvalZero #include <nrfx.h>
36*150812a8SEvalZero #include <hal/nrf_pwm.h>
37*150812a8SEvalZero
38*150812a8SEvalZero #ifdef __cplusplus
39*150812a8SEvalZero extern "C" {
40*150812a8SEvalZero #endif
41*150812a8SEvalZero
42*150812a8SEvalZero /**
43*150812a8SEvalZero * @defgroup nrfx_pwm PWM driver
44*150812a8SEvalZero * @{
45*150812a8SEvalZero * @ingroup nrf_pwm
46*150812a8SEvalZero * @brief Pulse Width Modulation (PWM) peripheral driver.
47*150812a8SEvalZero */
48*150812a8SEvalZero
49*150812a8SEvalZero /**
50*150812a8SEvalZero * @brief PWM driver instance data structure.
51*150812a8SEvalZero */
52*150812a8SEvalZero typedef struct
53*150812a8SEvalZero {
54*150812a8SEvalZero NRF_PWM_Type * p_registers; ///< Pointer to the structure with PWM peripheral instance registers.
55*150812a8SEvalZero uint8_t drv_inst_idx; ///< Driver instance index.
56*150812a8SEvalZero } nrfx_pwm_t;
57*150812a8SEvalZero
58*150812a8SEvalZero /**
59*150812a8SEvalZero * @brief Macro for creating a PWM driver instance.
60*150812a8SEvalZero */
61*150812a8SEvalZero #define NRFX_PWM_INSTANCE(id) \
62*150812a8SEvalZero { \
63*150812a8SEvalZero .p_registers = NRFX_CONCAT_2(NRF_PWM, id), \
64*150812a8SEvalZero .drv_inst_idx = NRFX_CONCAT_3(NRFX_PWM, id, _INST_IDX), \
65*150812a8SEvalZero }
66*150812a8SEvalZero
67*150812a8SEvalZero enum {
68*150812a8SEvalZero #if NRFX_CHECK(NRFX_PWM0_ENABLED)
69*150812a8SEvalZero NRFX_PWM0_INST_IDX,
70*150812a8SEvalZero #endif
71*150812a8SEvalZero #if NRFX_CHECK(NRFX_PWM1_ENABLED)
72*150812a8SEvalZero NRFX_PWM1_INST_IDX,
73*150812a8SEvalZero #endif
74*150812a8SEvalZero #if NRFX_CHECK(NRFX_PWM2_ENABLED)
75*150812a8SEvalZero NRFX_PWM2_INST_IDX,
76*150812a8SEvalZero #endif
77*150812a8SEvalZero #if NRFX_CHECK(NRFX_PWM3_ENABLED)
78*150812a8SEvalZero NRFX_PWM3_INST_IDX,
79*150812a8SEvalZero #endif
80*150812a8SEvalZero NRFX_PWM_ENABLED_COUNT
81*150812a8SEvalZero };
82*150812a8SEvalZero
83*150812a8SEvalZero /**
84*150812a8SEvalZero * @brief This value can be provided instead of a pin number for any channel
85*150812a8SEvalZero * to specify that its output is not used and therefore does not need
86*150812a8SEvalZero * to be connected to a pin.
87*150812a8SEvalZero */
88*150812a8SEvalZero #define NRFX_PWM_PIN_NOT_USED 0xFF
89*150812a8SEvalZero
90*150812a8SEvalZero /**
91*150812a8SEvalZero * @brief This value can be added to a pin number to inverse its polarity
92*150812a8SEvalZero * (set idle state = 1).
93*150812a8SEvalZero */
94*150812a8SEvalZero #define NRFX_PWM_PIN_INVERTED 0x80
95*150812a8SEvalZero
96*150812a8SEvalZero /**
97*150812a8SEvalZero * @brief PWM driver configuration structure.
98*150812a8SEvalZero */
99*150812a8SEvalZero typedef struct
100*150812a8SEvalZero {
101*150812a8SEvalZero uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional).
102*150812a8SEvalZero /**< Use @ref NRFX_PWM_PIN_NOT_USED
103*150812a8SEvalZero * if a given output channel is not needed. */
104*150812a8SEvalZero uint8_t irq_priority; ///< Interrupt priority.
105*150812a8SEvalZero nrf_pwm_clk_t base_clock; ///< Base clock frequency.
106*150812a8SEvalZero nrf_pwm_mode_t count_mode; ///< Operating mode of the pulse generator counter.
107*150812a8SEvalZero uint16_t top_value; ///< Value up to which the pulse generator counter counts.
108*150812a8SEvalZero nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM.
109*150812a8SEvalZero nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence.
110*150812a8SEvalZero } nrfx_pwm_config_t;
111*150812a8SEvalZero
112*150812a8SEvalZero /**
113*150812a8SEvalZero * @brief PWM driver default configuration.
114*150812a8SEvalZero */
115*150812a8SEvalZero #define NRFX_PWM_DEFAULT_CONFIG \
116*150812a8SEvalZero { \
117*150812a8SEvalZero .output_pins = { NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN, \
118*150812a8SEvalZero NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN, \
119*150812a8SEvalZero NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN, \
120*150812a8SEvalZero NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN }, \
121*150812a8SEvalZero .irq_priority = NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY, \
122*150812a8SEvalZero .base_clock = (nrf_pwm_clk_t)NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK, \
123*150812a8SEvalZero .count_mode = (nrf_pwm_mode_t)NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE, \
124*150812a8SEvalZero .top_value = NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE, \
125*150812a8SEvalZero .load_mode = (nrf_pwm_dec_load_t)NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE, \
126*150812a8SEvalZero .step_mode = (nrf_pwm_dec_step_t)NRFX_PWM_DEFAULT_CONFIG_STEP_MODE, \
127*150812a8SEvalZero }
128*150812a8SEvalZero
129*150812a8SEvalZero
130*150812a8SEvalZero /**
131*150812a8SEvalZero * @brief PWM flags providing additional playback options.
132*150812a8SEvalZero */
133*150812a8SEvalZero typedef enum
134*150812a8SEvalZero {
135*150812a8SEvalZero NRFX_PWM_FLAG_STOP = 0x01, /**< When the requested playback is finished,
136*150812a8SEvalZero the peripheral should be stopped.
137*150812a8SEvalZero @note The STOP task is triggered when
138*150812a8SEvalZero the last value of the final sequence is
139*150812a8SEvalZero loaded from RAM, and the peripheral stops
140*150812a8SEvalZero at the end of the current PWM period.
141*150812a8SEvalZero For sequences with configured repeating
142*150812a8SEvalZero of duty cycle values, this might result in
143*150812a8SEvalZero less than the requested number of repeats
144*150812a8SEvalZero of the last value. */
145*150812a8SEvalZero NRFX_PWM_FLAG_LOOP = 0x02, /**< When the requested playback is finished,
146*150812a8SEvalZero it should be started from the beginning.
147*150812a8SEvalZero This flag is ignored if used together
148*150812a8SEvalZero with @ref NRFX_PWM_FLAG_STOP.
149*150812a8SEvalZero @note The playback restart is done via a
150*150812a8SEvalZero shortcut configured in the PWM peripheral.
151*150812a8SEvalZero This shortcut triggers the proper starting
152*150812a8SEvalZero task when the final value of previous
153*150812a8SEvalZero playback is read from RAM and applied to
154*150812a8SEvalZero the pulse generator counter.
155*150812a8SEvalZero When this mechanism is used together with
156*150812a8SEvalZero the @ref NRF_PWM_STEP_TRIGGERED mode,
157*150812a8SEvalZero the playback restart will occur right
158*150812a8SEvalZero after switching to the final value (this
159*150812a8SEvalZero final value will be played only once). */
160*150812a8SEvalZero NRFX_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler should be
161*150812a8SEvalZero called when the last value
162*150812a8SEvalZero from sequence 0 is loaded. */
163*150812a8SEvalZero NRFX_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler should be
164*150812a8SEvalZero called when the last value
165*150812a8SEvalZero from sequence 1 is loaded. */
166*150812a8SEvalZero NRFX_PWM_FLAG_NO_EVT_FINISHED = 0x10, /**< The playback finished event
167*150812a8SEvalZero (enabled by default) should be
168*150812a8SEvalZero suppressed. */
169*150812a8SEvalZero NRFX_PWM_FLAG_START_VIA_TASK = 0x80, /**< The playback should not be
170*150812a8SEvalZero started directly by the called
171*150812a8SEvalZero function. Instead, the function
172*150812a8SEvalZero should only prepare it and
173*150812a8SEvalZero return the address of the task
174*150812a8SEvalZero to be triggered to start the
175*150812a8SEvalZero playback. */
176*150812a8SEvalZero } nrfx_pwm_flag_t;
177*150812a8SEvalZero
178*150812a8SEvalZero
179*150812a8SEvalZero /**
180*150812a8SEvalZero * @brief PWM driver event type.
181*150812a8SEvalZero */
182*150812a8SEvalZero typedef enum
183*150812a8SEvalZero {
184*150812a8SEvalZero NRFX_PWM_EVT_FINISHED, ///< Sequence playback finished.
185*150812a8SEvalZero NRFX_PWM_EVT_END_SEQ0, /**< End of sequence 0 reached. Its data can be
186*150812a8SEvalZero safely modified now. */
187*150812a8SEvalZero NRFX_PWM_EVT_END_SEQ1, /**< End of sequence 1 reached. Its data can be
188*150812a8SEvalZero safely modified now. */
189*150812a8SEvalZero NRFX_PWM_EVT_STOPPED, ///< The PWM peripheral has been stopped.
190*150812a8SEvalZero } nrfx_pwm_evt_type_t;
191*150812a8SEvalZero
192*150812a8SEvalZero /**
193*150812a8SEvalZero * @brief PWM driver event handler type.
194*150812a8SEvalZero */
195*150812a8SEvalZero typedef void (* nrfx_pwm_handler_t)(nrfx_pwm_evt_type_t event_type);
196*150812a8SEvalZero
197*150812a8SEvalZero
198*150812a8SEvalZero /**
199*150812a8SEvalZero * @brief Function for initializing the PWM driver.
200*150812a8SEvalZero *
201*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
202*150812a8SEvalZero * @param[in] p_config Pointer to the structure with initial configuration.
203*150812a8SEvalZero *
204*150812a8SEvalZero * @param[in] handler Event handler provided by the user. If NULL is passed
205*150812a8SEvalZero * instead, event notifications are not done and PWM
206*150812a8SEvalZero * interrupts are disabled.
207*150812a8SEvalZero *
208*150812a8SEvalZero * @retval NRFX_SUCCESS If initialization was successful.
209*150812a8SEvalZero * @retval NRFX_ERROR_INVALID_STATE If the driver was already initialized.
210*150812a8SEvalZero */
211*150812a8SEvalZero nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * const p_instance,
212*150812a8SEvalZero nrfx_pwm_config_t const * p_config,
213*150812a8SEvalZero nrfx_pwm_handler_t handler);
214*150812a8SEvalZero
215*150812a8SEvalZero /**
216*150812a8SEvalZero * @brief Function for uninitializing the PWM driver.
217*150812a8SEvalZero *
218*150812a8SEvalZero * If any sequence playback is in progress, it is stopped immediately.
219*150812a8SEvalZero *
220*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
221*150812a8SEvalZero */
222*150812a8SEvalZero void nrfx_pwm_uninit(nrfx_pwm_t const * const p_instance);
223*150812a8SEvalZero
224*150812a8SEvalZero /**
225*150812a8SEvalZero * @brief Function for starting a single sequence playback.
226*150812a8SEvalZero *
227*150812a8SEvalZero * To take advantage of the looping mechanism in the PWM peripheral, both
228*150812a8SEvalZero * sequences must be used (single sequence can be played back only once by
229*150812a8SEvalZero * the peripheral). Therefore, the provided sequence is internally set and
230*150812a8SEvalZero * played back as both sequence 0 and sequence 1. Consequently, if end of
231*150812a8SEvalZero * sequence notifications are required, events for both sequences should be
232*150812a8SEvalZero * used (that means that both the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ0 flag
233*150812a8SEvalZero * and the @ref NRFX_PWM_FLAG_SIGNAL_END_SEQ1 flag should be specified and
234*150812a8SEvalZero * the @ref NRFX_PWM_EVT_END_SEQ0 event and the @ref NRFX_PWM_EVT_END_SEQ1
235*150812a8SEvalZero * event should be handled in the same way).
236*150812a8SEvalZero *
237*150812a8SEvalZero * Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback
238*150812a8SEvalZero * to be only prepared by this function, and you want to start it later by
239*150812a8SEvalZero * triggering a task (using PPI for instance). The function will then return
240*150812a8SEvalZero * the address of the task to be triggered.
241*150812a8SEvalZero *
242*150812a8SEvalZero * @note The array containing the duty cycle values for the specified sequence
243*150812a8SEvalZero * must be in RAM and cannot be allocated on stack.
244*150812a8SEvalZero * For detailed information, see @ref nrf_pwm_sequence_t.
245*150812a8SEvalZero *
246*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
247*150812a8SEvalZero * @param[in] p_sequence Sequence to be played back.
248*150812a8SEvalZero * @param[in] playback_count Number of playbacks to be performed (must not be 0).
249*150812a8SEvalZero * @param[in] flags Additional options. Pass any combination of
250*150812a8SEvalZero * @ref nrfx_pwm_flag_t "playback flags", or 0
251*150812a8SEvalZero * for default settings.
252*150812a8SEvalZero *
253*150812a8SEvalZero * @return Address of the task to be triggered to start the playback if the @ref
254*150812a8SEvalZero * NRFX_PWM_FLAG_START_VIA_TASK flag was used, 0 otherwise.
255*150812a8SEvalZero */
256*150812a8SEvalZero uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * const p_instance,
257*150812a8SEvalZero nrf_pwm_sequence_t const * p_sequence,
258*150812a8SEvalZero uint16_t playback_count,
259*150812a8SEvalZero uint32_t flags);
260*150812a8SEvalZero
261*150812a8SEvalZero /**
262*150812a8SEvalZero * @brief Function for starting a two-sequence playback.
263*150812a8SEvalZero *
264*150812a8SEvalZero * Use the @ref NRFX_PWM_FLAG_START_VIA_TASK flag if you want the playback
265*150812a8SEvalZero * to be only prepared by this function, and you want to start it later by
266*150812a8SEvalZero * triggering a task (using PPI for instance). The function will then return
267*150812a8SEvalZero * the address of the task to be triggered.
268*150812a8SEvalZero *
269*150812a8SEvalZero * @note The array containing the duty cycle values for the specified sequence
270*150812a8SEvalZero * must be in RAM and cannot be allocated on stack.
271*150812a8SEvalZero * For detailed information, see @ref nrf_pwm_sequence_t.
272*150812a8SEvalZero *
273*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
274*150812a8SEvalZero * @param[in] p_sequence_0 First sequence to be played back.
275*150812a8SEvalZero * @param[in] p_sequence_1 Second sequence to be played back.
276*150812a8SEvalZero * @param[in] playback_count Number of playbacks to be performed (must not be 0).
277*150812a8SEvalZero * @param[in] flags Additional options. Pass any combination of
278*150812a8SEvalZero * @ref nrfx_pwm_flag_t "playback flags", or 0
279*150812a8SEvalZero * for default settings.
280*150812a8SEvalZero *
281*150812a8SEvalZero * @return Address of the task to be triggered to start the playback if the @ref
282*150812a8SEvalZero * NRFX_PWM_FLAG_START_VIA_TASK flag was used, 0 otherwise.
283*150812a8SEvalZero */
284*150812a8SEvalZero uint32_t nrfx_pwm_complex_playback(nrfx_pwm_t const * const p_instance,
285*150812a8SEvalZero nrf_pwm_sequence_t const * p_sequence_0,
286*150812a8SEvalZero nrf_pwm_sequence_t const * p_sequence_1,
287*150812a8SEvalZero uint16_t playback_count,
288*150812a8SEvalZero uint32_t flags);
289*150812a8SEvalZero
290*150812a8SEvalZero /**
291*150812a8SEvalZero * @brief Function for advancing the active sequence.
292*150812a8SEvalZero *
293*150812a8SEvalZero * This function only applies to @ref NRF_PWM_STEP_TRIGGERED mode.
294*150812a8SEvalZero *
295*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
296*150812a8SEvalZero */
297*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance);
298*150812a8SEvalZero
299*150812a8SEvalZero /**
300*150812a8SEvalZero * @brief Function for stopping the sequence playback.
301*150812a8SEvalZero *
302*150812a8SEvalZero * The playback is stopped at the end of the current PWM period.
303*150812a8SEvalZero * This means that if the active sequence is configured to repeat each duty
304*150812a8SEvalZero * cycle value for a certain number of PWM periods, the last played value
305*150812a8SEvalZero * might appear on the output less times than requested.
306*150812a8SEvalZero *
307*150812a8SEvalZero * @note This function can be instructed to wait until the playback is stopped
308*150812a8SEvalZero * (by setting @p wait_until_stopped to true). Note that, depending on
309*150812a8SEvalZero * the length of the PMW period, this might take a significant amount of
310*150812a8SEvalZero * time. Alternatively, the @ref nrfx_pwm_is_stopped function can be
311*150812a8SEvalZero * used to poll the status, or the @ref NRFX_PWM_EVT_STOPPED event can
312*150812a8SEvalZero * be used to get the notification when the playback is stopped, provided
313*150812a8SEvalZero * the event handler is defined.
314*150812a8SEvalZero *
315*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
316*150812a8SEvalZero * @param[in] wait_until_stopped If true, the function will not return until
317*150812a8SEvalZero * the playback is stopped.
318*150812a8SEvalZero *
319*150812a8SEvalZero * @retval true If the PWM peripheral is stopped.
320*150812a8SEvalZero * @retval false If the PWM peripheral is not stopped.
321*150812a8SEvalZero */
322*150812a8SEvalZero bool nrfx_pwm_stop(nrfx_pwm_t const * const p_instance,
323*150812a8SEvalZero bool wait_until_stopped);
324*150812a8SEvalZero
325*150812a8SEvalZero /**
326*150812a8SEvalZero * @brief Function for checking the status of the PWM peripheral.
327*150812a8SEvalZero *
328*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
329*150812a8SEvalZero *
330*150812a8SEvalZero * @retval true If the PWM peripheral is stopped.
331*150812a8SEvalZero * @retval false If the PWM peripheral is not stopped.
332*150812a8SEvalZero */
333*150812a8SEvalZero bool nrfx_pwm_is_stopped(nrfx_pwm_t const * const p_instance);
334*150812a8SEvalZero
335*150812a8SEvalZero /**
336*150812a8SEvalZero * @brief Function for updating the sequence data during playback.
337*150812a8SEvalZero *
338*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
339*150812a8SEvalZero * @param[in] seq_id Identifier of the sequence (0 or 1).
340*150812a8SEvalZero * @param[in] p_sequence Pointer to the new sequence definition.
341*150812a8SEvalZero */
342*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_update(
343*150812a8SEvalZero nrfx_pwm_t const * const p_instance,
344*150812a8SEvalZero uint8_t seq_id,
345*150812a8SEvalZero nrf_pwm_sequence_t const * p_sequence);
346*150812a8SEvalZero
347*150812a8SEvalZero /**
348*150812a8SEvalZero * @brief Function for updating the pointer to the duty cycle values
349*150812a8SEvalZero * in the specified sequence during playback.
350*150812a8SEvalZero *
351*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
352*150812a8SEvalZero * @param[in] seq_id Identifier of the sequence (0 or 1).
353*150812a8SEvalZero * @param[in] values New pointer to the duty cycle values.
354*150812a8SEvalZero */
355*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance,
356*150812a8SEvalZero uint8_t seq_id,
357*150812a8SEvalZero nrf_pwm_values_t values);
358*150812a8SEvalZero
359*150812a8SEvalZero /**
360*150812a8SEvalZero * @brief Function for updating the number of duty cycle values
361*150812a8SEvalZero * in the specified sequence during playback.
362*150812a8SEvalZero *
363*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
364*150812a8SEvalZero * @param[in] seq_id Identifier of the sequence (0 or 1).
365*150812a8SEvalZero * @param[in] length New number of the duty cycle values.
366*150812a8SEvalZero */
367*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance,
368*150812a8SEvalZero uint8_t seq_id,
369*150812a8SEvalZero uint16_t length);
370*150812a8SEvalZero
371*150812a8SEvalZero /**
372*150812a8SEvalZero * @brief Function for updating the number of repeats for duty cycle values
373*150812a8SEvalZero * in specified sequence during playback.
374*150812a8SEvalZero *
375*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
376*150812a8SEvalZero * @param[in] seq_id Identifier of the sequence (0 or 1).
377*150812a8SEvalZero * @param[in] repeats New number of repeats.
378*150812a8SEvalZero */
379*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance,
380*150812a8SEvalZero uint8_t seq_id,
381*150812a8SEvalZero uint32_t repeats);
382*150812a8SEvalZero
383*150812a8SEvalZero /**
384*150812a8SEvalZero * @brief Function for updating the additional delay after the specified
385*150812a8SEvalZero * sequence during playback.
386*150812a8SEvalZero *
387*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
388*150812a8SEvalZero * @param[in] seq_id Identifier of the sequence (0 or 1).
389*150812a8SEvalZero * @param[in] end_delay New end delay value (in PWM periods).
390*150812a8SEvalZero */
391*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance,
392*150812a8SEvalZero uint8_t seq_id,
393*150812a8SEvalZero uint32_t end_delay);
394*150812a8SEvalZero
395*150812a8SEvalZero /**
396*150812a8SEvalZero * @brief Function for returning the address of a specified PWM task that can
397*150812a8SEvalZero * be used in PPI module.
398*150812a8SEvalZero *
399*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
400*150812a8SEvalZero * @param[in] task Requested task.
401*150812a8SEvalZero *
402*150812a8SEvalZero * @return Task address.
403*150812a8SEvalZero */
404*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance,
405*150812a8SEvalZero nrf_pwm_task_t task);
406*150812a8SEvalZero
407*150812a8SEvalZero /**@brief Function for returning the address of a specified PWM event that can
408*150812a8SEvalZero * be used in PPI module.
409*150812a8SEvalZero *
410*150812a8SEvalZero * @param[in] p_instance Pointer to the driver instance structure.
411*150812a8SEvalZero * @param[in] event Requested event.
412*150812a8SEvalZero *
413*150812a8SEvalZero * @return Event address.
414*150812a8SEvalZero */
415*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance,
416*150812a8SEvalZero nrf_pwm_event_t event);
417*150812a8SEvalZero
418*150812a8SEvalZero
419*150812a8SEvalZero #ifndef SUPPRESS_INLINE_IMPLEMENTATION
420*150812a8SEvalZero
nrfx_pwm_step(nrfx_pwm_t const * const p_instance)421*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_step(nrfx_pwm_t const * const p_instance)
422*150812a8SEvalZero {
423*150812a8SEvalZero nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_NEXTSTEP);
424*150812a8SEvalZero }
425*150812a8SEvalZero
nrfx_pwm_sequence_update(nrfx_pwm_t const * const p_instance,uint8_t seq_id,nrf_pwm_sequence_t const * p_sequence)426*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_update(nrfx_pwm_t const * const p_instance,
427*150812a8SEvalZero uint8_t seq_id,
428*150812a8SEvalZero nrf_pwm_sequence_t const * p_sequence)
429*150812a8SEvalZero {
430*150812a8SEvalZero nrf_pwm_sequence_set(p_instance->p_registers, seq_id, p_sequence);
431*150812a8SEvalZero }
432*150812a8SEvalZero
nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance,uint8_t seq_id,nrf_pwm_values_t values)433*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_values_update(nrfx_pwm_t const * const p_instance,
434*150812a8SEvalZero uint8_t seq_id,
435*150812a8SEvalZero nrf_pwm_values_t values)
436*150812a8SEvalZero {
437*150812a8SEvalZero nrf_pwm_seq_ptr_set(p_instance->p_registers, seq_id, values.p_raw);
438*150812a8SEvalZero }
439*150812a8SEvalZero
nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance,uint8_t seq_id,uint16_t length)440*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_length_update(nrfx_pwm_t const * const p_instance,
441*150812a8SEvalZero uint8_t seq_id,
442*150812a8SEvalZero uint16_t length)
443*150812a8SEvalZero {
444*150812a8SEvalZero nrf_pwm_seq_cnt_set(p_instance->p_registers, seq_id, length);
445*150812a8SEvalZero }
446*150812a8SEvalZero
nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance,uint8_t seq_id,uint32_t repeats)447*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_repeats_update(nrfx_pwm_t const * const p_instance,
448*150812a8SEvalZero uint8_t seq_id,
449*150812a8SEvalZero uint32_t repeats)
450*150812a8SEvalZero {
451*150812a8SEvalZero nrf_pwm_seq_refresh_set(p_instance->p_registers, seq_id, repeats);
452*150812a8SEvalZero }
453*150812a8SEvalZero
nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance,uint8_t seq_id,uint32_t end_delay)454*150812a8SEvalZero __STATIC_INLINE void nrfx_pwm_sequence_end_delay_update(nrfx_pwm_t const * const p_instance,
455*150812a8SEvalZero uint8_t seq_id,
456*150812a8SEvalZero uint32_t end_delay)
457*150812a8SEvalZero {
458*150812a8SEvalZero nrf_pwm_seq_end_delay_set(p_instance->p_registers, seq_id, end_delay);
459*150812a8SEvalZero }
460*150812a8SEvalZero
nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance,nrf_pwm_task_t task)461*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_pwm_task_address_get(nrfx_pwm_t const * const p_instance,
462*150812a8SEvalZero nrf_pwm_task_t task)
463*150812a8SEvalZero {
464*150812a8SEvalZero return nrf_pwm_task_address_get(p_instance->p_registers, task);
465*150812a8SEvalZero }
466*150812a8SEvalZero
nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance,nrf_pwm_event_t event)467*150812a8SEvalZero __STATIC_INLINE uint32_t nrfx_pwm_event_address_get(nrfx_pwm_t const * const p_instance,
468*150812a8SEvalZero nrf_pwm_event_t event)
469*150812a8SEvalZero {
470*150812a8SEvalZero return nrf_pwm_event_address_get(p_instance->p_registers, event);
471*150812a8SEvalZero }
472*150812a8SEvalZero
473*150812a8SEvalZero #endif // SUPPRESS_INLINE_IMPLEMENTATION
474*150812a8SEvalZero
475*150812a8SEvalZero
476*150812a8SEvalZero void nrfx_pwm_0_irq_handler(void);
477*150812a8SEvalZero void nrfx_pwm_1_irq_handler(void);
478*150812a8SEvalZero void nrfx_pwm_2_irq_handler(void);
479*150812a8SEvalZero void nrfx_pwm_3_irq_handler(void);
480*150812a8SEvalZero
481*150812a8SEvalZero
482*150812a8SEvalZero /** @} */
483*150812a8SEvalZero
484*150812a8SEvalZero #ifdef __cplusplus
485*150812a8SEvalZero }
486*150812a8SEvalZero #endif
487*150812a8SEvalZero
488*150812a8SEvalZero #endif // NRFX_PWM_H__
489