1*150812a8SEvalZero /* 2*150812a8SEvalZero 3*150812a8SEvalZero Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 4*150812a8SEvalZero 5*150812a8SEvalZero Redistribution and use in source and binary forms, with or without 6*150812a8SEvalZero modification, are permitted provided that the following conditions are met: 7*150812a8SEvalZero 8*150812a8SEvalZero 1. Redistributions of source code must retain the above copyright notice, this 9*150812a8SEvalZero list of conditions and the following disclaimer. 10*150812a8SEvalZero 11*150812a8SEvalZero 2. Redistributions in binary form must reproduce the above copyright 12*150812a8SEvalZero notice, this list of conditions and the following disclaimer in the 13*150812a8SEvalZero documentation and/or other materials provided with the distribution. 14*150812a8SEvalZero 15*150812a8SEvalZero 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16*150812a8SEvalZero contributors may be used to endorse or promote products derived from this 17*150812a8SEvalZero software without specific prior written permission. 18*150812a8SEvalZero 19*150812a8SEvalZero THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20*150812a8SEvalZero AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*150812a8SEvalZero IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22*150812a8SEvalZero ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23*150812a8SEvalZero LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24*150812a8SEvalZero CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25*150812a8SEvalZero SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26*150812a8SEvalZero INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27*150812a8SEvalZero CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28*150812a8SEvalZero ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29*150812a8SEvalZero POSSIBILITY OF SUCH DAMAGE. 30*150812a8SEvalZero 31*150812a8SEvalZero */ 32*150812a8SEvalZero 33*150812a8SEvalZero #ifndef NRF51_TO_NRF52810_H 34*150812a8SEvalZero #define NRF51_TO_NRF52810_H 35*150812a8SEvalZero 36*150812a8SEvalZero /*lint ++flb "Enter library region */ 37*150812a8SEvalZero 38*150812a8SEvalZero /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. 39*150812a8SEvalZero * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 40*150812a8SEvalZero * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros 41*150812a8SEvalZero * from the nrf51_deprecated.h file. */ 42*150812a8SEvalZero 43*150812a8SEvalZero 44*150812a8SEvalZero /* Differences between latest nRF51 headers and nRF52810 headers. */ 45*150812a8SEvalZero 46*150812a8SEvalZero /* IRQ */ 47*150812a8SEvalZero /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 48*150812a8SEvalZero #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 49*150812a8SEvalZero #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 50*150812a8SEvalZero 51*150812a8SEvalZero #define SWI0_IRQn SWI0_EGU0_IRQn 52*150812a8SEvalZero #define SWI1_IRQn SWI1_EGU1_IRQn 53*150812a8SEvalZero 54*150812a8SEvalZero 55*150812a8SEvalZero /* UICR */ 56*150812a8SEvalZero /* Register RBPCONF was renamed to APPROTECT. */ 57*150812a8SEvalZero #define RBPCONF APPROTECT 58*150812a8SEvalZero 59*150812a8SEvalZero #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 60*150812a8SEvalZero #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 61*150812a8SEvalZero #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 62*150812a8SEvalZero #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 63*150812a8SEvalZero 64*150812a8SEvalZero 65*150812a8SEvalZero /* GPIO */ 66*150812a8SEvalZero /* GPIO port was renamed to P0. */ 67*150812a8SEvalZero #define NRF_GPIO NRF_P0 68*150812a8SEvalZero #define NRF_GPIO_BASE NRF_P0_BASE 69*150812a8SEvalZero 70*150812a8SEvalZero 71*150812a8SEvalZero /* QDEC */ 72*150812a8SEvalZero /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ 73*150812a8SEvalZero #define PSELLED PSEL.LED 74*150812a8SEvalZero #define PSELA PSEL.A 75*150812a8SEvalZero #define PSELB PSEL.B 76*150812a8SEvalZero 77*150812a8SEvalZero 78*150812a8SEvalZero /* SPIS */ 79*150812a8SEvalZero /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 80*150812a8SEvalZero #define PSELSCK PSEL.SCK 81*150812a8SEvalZero #define PSELMISO PSEL.MISO 82*150812a8SEvalZero #define PSELMOSI PSEL.MOSI 83*150812a8SEvalZero #define PSELCSN PSEL.CSN 84*150812a8SEvalZero 85*150812a8SEvalZero /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 86*150812a8SEvalZero #define RXDPTR RXD.PTR 87*150812a8SEvalZero #define MAXRX RXD.MAXCNT 88*150812a8SEvalZero #define AMOUNTRX RXD.AMOUNT 89*150812a8SEvalZero 90*150812a8SEvalZero #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 91*150812a8SEvalZero #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 92*150812a8SEvalZero 93*150812a8SEvalZero #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 94*150812a8SEvalZero #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 95*150812a8SEvalZero 96*150812a8SEvalZero /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 97*150812a8SEvalZero #define TXDPTR TXD.PTR 98*150812a8SEvalZero #define MAXTX TXD.MAXCNT 99*150812a8SEvalZero #define AMOUNTTX TXD.AMOUNT 100*150812a8SEvalZero 101*150812a8SEvalZero #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 102*150812a8SEvalZero #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 103*150812a8SEvalZero 104*150812a8SEvalZero #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 105*150812a8SEvalZero #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 106*150812a8SEvalZero 107*150812a8SEvalZero 108*150812a8SEvalZero /* From nrf51_deprecated.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ 109*150812a8SEvalZero 110*150812a8SEvalZero /* NVMC */ 111*150812a8SEvalZero /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ 112*150812a8SEvalZero #define ERASEPROTECTEDPAGE ERASEPCR0 113*150812a8SEvalZero 114*150812a8SEvalZero 115*150812a8SEvalZero /* RADIO */ 116*150812a8SEvalZero /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 117*150812a8SEvalZero #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 118*150812a8SEvalZero #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 119*150812a8SEvalZero #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 120*150812a8SEvalZero #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 121*150812a8SEvalZero 122*150812a8SEvalZero 123*150812a8SEvalZero /* FICR */ 124*150812a8SEvalZero /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 125*150812a8SEvalZero #define DEVICEID0 DEVICEID[0] 126*150812a8SEvalZero #define DEVICEID1 DEVICEID[1] 127*150812a8SEvalZero 128*150812a8SEvalZero /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 129*150812a8SEvalZero #define ER0 ER[0] 130*150812a8SEvalZero #define ER1 ER[1] 131*150812a8SEvalZero #define ER2 ER[2] 132*150812a8SEvalZero #define ER3 ER[3] 133*150812a8SEvalZero 134*150812a8SEvalZero /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 135*150812a8SEvalZero #define IR0 IR[0] 136*150812a8SEvalZero #define IR1 IR[1] 137*150812a8SEvalZero #define IR2 IR[2] 138*150812a8SEvalZero #define IR3 IR[3] 139*150812a8SEvalZero 140*150812a8SEvalZero /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 141*150812a8SEvalZero #define DEVICEADDR0 DEVICEADDR[0] 142*150812a8SEvalZero #define DEVICEADDR1 DEVICEADDR[1] 143*150812a8SEvalZero 144*150812a8SEvalZero 145*150812a8SEvalZero /* PPI */ 146*150812a8SEvalZero /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 147*150812a8SEvalZero #define TASKS_CHG0EN TASKS_CHG[0].EN 148*150812a8SEvalZero #define TASKS_CHG0DIS TASKS_CHG[0].DIS 149*150812a8SEvalZero #define TASKS_CHG1EN TASKS_CHG[1].EN 150*150812a8SEvalZero #define TASKS_CHG1DIS TASKS_CHG[1].DIS 151*150812a8SEvalZero #define TASKS_CHG2EN TASKS_CHG[2].EN 152*150812a8SEvalZero #define TASKS_CHG2DIS TASKS_CHG[2].DIS 153*150812a8SEvalZero #define TASKS_CHG3EN TASKS_CHG[3].EN 154*150812a8SEvalZero #define TASKS_CHG3DIS TASKS_CHG[3].DIS 155*150812a8SEvalZero 156*150812a8SEvalZero /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 157*150812a8SEvalZero #define CH0_EEP CH[0].EEP 158*150812a8SEvalZero #define CH0_TEP CH[0].TEP 159*150812a8SEvalZero #define CH1_EEP CH[1].EEP 160*150812a8SEvalZero #define CH1_TEP CH[1].TEP 161*150812a8SEvalZero #define CH2_EEP CH[2].EEP 162*150812a8SEvalZero #define CH2_TEP CH[2].TEP 163*150812a8SEvalZero #define CH3_EEP CH[3].EEP 164*150812a8SEvalZero #define CH3_TEP CH[3].TEP 165*150812a8SEvalZero #define CH4_EEP CH[4].EEP 166*150812a8SEvalZero #define CH4_TEP CH[4].TEP 167*150812a8SEvalZero #define CH5_EEP CH[5].EEP 168*150812a8SEvalZero #define CH5_TEP CH[5].TEP 169*150812a8SEvalZero #define CH6_EEP CH[6].EEP 170*150812a8SEvalZero #define CH6_TEP CH[6].TEP 171*150812a8SEvalZero #define CH7_EEP CH[7].EEP 172*150812a8SEvalZero #define CH7_TEP CH[7].TEP 173*150812a8SEvalZero #define CH8_EEP CH[8].EEP 174*150812a8SEvalZero #define CH8_TEP CH[8].TEP 175*150812a8SEvalZero #define CH9_EEP CH[9].EEP 176*150812a8SEvalZero #define CH9_TEP CH[9].TEP 177*150812a8SEvalZero #define CH10_EEP CH[10].EEP 178*150812a8SEvalZero #define CH10_TEP CH[10].TEP 179*150812a8SEvalZero #define CH11_EEP CH[11].EEP 180*150812a8SEvalZero #define CH11_TEP CH[11].TEP 181*150812a8SEvalZero #define CH12_EEP CH[12].EEP 182*150812a8SEvalZero #define CH12_TEP CH[12].TEP 183*150812a8SEvalZero #define CH13_EEP CH[13].EEP 184*150812a8SEvalZero #define CH13_TEP CH[13].TEP 185*150812a8SEvalZero #define CH14_EEP CH[14].EEP 186*150812a8SEvalZero #define CH14_TEP CH[14].TEP 187*150812a8SEvalZero #define CH15_EEP CH[15].EEP 188*150812a8SEvalZero #define CH15_TEP CH[15].TEP 189*150812a8SEvalZero 190*150812a8SEvalZero /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 191*150812a8SEvalZero #define CHG0 CHG[0] 192*150812a8SEvalZero #define CHG1 CHG[1] 193*150812a8SEvalZero #define CHG2 CHG[2] 194*150812a8SEvalZero #define CHG3 CHG[3] 195*150812a8SEvalZero 196*150812a8SEvalZero /* All bitfield macros for the CHGx registers therefore changed name. */ 197*150812a8SEvalZero #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 198*150812a8SEvalZero #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 199*150812a8SEvalZero #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 200*150812a8SEvalZero #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 201*150812a8SEvalZero 202*150812a8SEvalZero #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 203*150812a8SEvalZero #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 204*150812a8SEvalZero #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 205*150812a8SEvalZero #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 206*150812a8SEvalZero 207*150812a8SEvalZero #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 208*150812a8SEvalZero #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 209*150812a8SEvalZero #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 210*150812a8SEvalZero #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 211*150812a8SEvalZero 212*150812a8SEvalZero #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 213*150812a8SEvalZero #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 214*150812a8SEvalZero #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 215*150812a8SEvalZero #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 216*150812a8SEvalZero 217*150812a8SEvalZero #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 218*150812a8SEvalZero #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 219*150812a8SEvalZero #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 220*150812a8SEvalZero #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 221*150812a8SEvalZero 222*150812a8SEvalZero #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 223*150812a8SEvalZero #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 224*150812a8SEvalZero #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 225*150812a8SEvalZero #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 226*150812a8SEvalZero 227*150812a8SEvalZero #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 228*150812a8SEvalZero #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 229*150812a8SEvalZero #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 230*150812a8SEvalZero #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 231*150812a8SEvalZero 232*150812a8SEvalZero #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 233*150812a8SEvalZero #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 234*150812a8SEvalZero #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 235*150812a8SEvalZero #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 236*150812a8SEvalZero 237*150812a8SEvalZero #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 238*150812a8SEvalZero #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 239*150812a8SEvalZero #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 240*150812a8SEvalZero #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 241*150812a8SEvalZero 242*150812a8SEvalZero #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 243*150812a8SEvalZero #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 244*150812a8SEvalZero #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 245*150812a8SEvalZero #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 246*150812a8SEvalZero 247*150812a8SEvalZero #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 248*150812a8SEvalZero #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 249*150812a8SEvalZero #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 250*150812a8SEvalZero #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 251*150812a8SEvalZero 252*150812a8SEvalZero #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 253*150812a8SEvalZero #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 254*150812a8SEvalZero #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 255*150812a8SEvalZero #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 256*150812a8SEvalZero 257*150812a8SEvalZero #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 258*150812a8SEvalZero #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 259*150812a8SEvalZero #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 260*150812a8SEvalZero #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 261*150812a8SEvalZero 262*150812a8SEvalZero #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 263*150812a8SEvalZero #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 264*150812a8SEvalZero #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 265*150812a8SEvalZero #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 266*150812a8SEvalZero 267*150812a8SEvalZero #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 268*150812a8SEvalZero #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 269*150812a8SEvalZero #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 270*150812a8SEvalZero #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 271*150812a8SEvalZero 272*150812a8SEvalZero #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 273*150812a8SEvalZero #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 274*150812a8SEvalZero #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 275*150812a8SEvalZero #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 276*150812a8SEvalZero 277*150812a8SEvalZero #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 278*150812a8SEvalZero #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 279*150812a8SEvalZero #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 280*150812a8SEvalZero #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 281*150812a8SEvalZero 282*150812a8SEvalZero #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 283*150812a8SEvalZero #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 284*150812a8SEvalZero #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 285*150812a8SEvalZero #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 286*150812a8SEvalZero 287*150812a8SEvalZero #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 288*150812a8SEvalZero #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 289*150812a8SEvalZero #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 290*150812a8SEvalZero #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 291*150812a8SEvalZero 292*150812a8SEvalZero #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 293*150812a8SEvalZero #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 294*150812a8SEvalZero #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 295*150812a8SEvalZero #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 296*150812a8SEvalZero 297*150812a8SEvalZero #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 298*150812a8SEvalZero #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 299*150812a8SEvalZero #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 300*150812a8SEvalZero #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 301*150812a8SEvalZero 302*150812a8SEvalZero #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 303*150812a8SEvalZero #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 304*150812a8SEvalZero #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 305*150812a8SEvalZero #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 306*150812a8SEvalZero 307*150812a8SEvalZero #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 308*150812a8SEvalZero #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 309*150812a8SEvalZero #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 310*150812a8SEvalZero #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 311*150812a8SEvalZero 312*150812a8SEvalZero #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 313*150812a8SEvalZero #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 314*150812a8SEvalZero #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 315*150812a8SEvalZero #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 316*150812a8SEvalZero 317*150812a8SEvalZero #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 318*150812a8SEvalZero #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 319*150812a8SEvalZero #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 320*150812a8SEvalZero #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 321*150812a8SEvalZero 322*150812a8SEvalZero #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 323*150812a8SEvalZero #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 324*150812a8SEvalZero #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 325*150812a8SEvalZero #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 326*150812a8SEvalZero 327*150812a8SEvalZero #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 328*150812a8SEvalZero #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 329*150812a8SEvalZero #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 330*150812a8SEvalZero #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 331*150812a8SEvalZero 332*150812a8SEvalZero #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 333*150812a8SEvalZero #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 334*150812a8SEvalZero #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 335*150812a8SEvalZero #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 336*150812a8SEvalZero 337*150812a8SEvalZero #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 338*150812a8SEvalZero #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 339*150812a8SEvalZero #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 340*150812a8SEvalZero #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 341*150812a8SEvalZero 342*150812a8SEvalZero #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 343*150812a8SEvalZero #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 344*150812a8SEvalZero #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 345*150812a8SEvalZero #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 346*150812a8SEvalZero 347*150812a8SEvalZero #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 348*150812a8SEvalZero #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 349*150812a8SEvalZero #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 350*150812a8SEvalZero #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 351*150812a8SEvalZero 352*150812a8SEvalZero #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 353*150812a8SEvalZero #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 354*150812a8SEvalZero #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 355*150812a8SEvalZero #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 356*150812a8SEvalZero 357*150812a8SEvalZero #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 358*150812a8SEvalZero #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 359*150812a8SEvalZero #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 360*150812a8SEvalZero #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 361*150812a8SEvalZero 362*150812a8SEvalZero #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 363*150812a8SEvalZero #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 364*150812a8SEvalZero #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 365*150812a8SEvalZero #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 366*150812a8SEvalZero 367*150812a8SEvalZero #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 368*150812a8SEvalZero #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 369*150812a8SEvalZero #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 370*150812a8SEvalZero #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 371*150812a8SEvalZero 372*150812a8SEvalZero #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 373*150812a8SEvalZero #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 374*150812a8SEvalZero #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 375*150812a8SEvalZero #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 376*150812a8SEvalZero 377*150812a8SEvalZero #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 378*150812a8SEvalZero #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 379*150812a8SEvalZero #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 380*150812a8SEvalZero #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 381*150812a8SEvalZero 382*150812a8SEvalZero #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 383*150812a8SEvalZero #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 384*150812a8SEvalZero #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 385*150812a8SEvalZero #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 386*150812a8SEvalZero 387*150812a8SEvalZero #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 388*150812a8SEvalZero #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 389*150812a8SEvalZero #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 390*150812a8SEvalZero #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 391*150812a8SEvalZero 392*150812a8SEvalZero #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 393*150812a8SEvalZero #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 394*150812a8SEvalZero #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 395*150812a8SEvalZero #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 396*150812a8SEvalZero 397*150812a8SEvalZero #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 398*150812a8SEvalZero #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 399*150812a8SEvalZero #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 400*150812a8SEvalZero #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 401*150812a8SEvalZero 402*150812a8SEvalZero #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 403*150812a8SEvalZero #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 404*150812a8SEvalZero #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 405*150812a8SEvalZero #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 406*150812a8SEvalZero 407*150812a8SEvalZero #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 408*150812a8SEvalZero #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 409*150812a8SEvalZero #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 410*150812a8SEvalZero #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 411*150812a8SEvalZero 412*150812a8SEvalZero #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 413*150812a8SEvalZero #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 414*150812a8SEvalZero #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 415*150812a8SEvalZero #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 416*150812a8SEvalZero 417*150812a8SEvalZero #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 418*150812a8SEvalZero #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 419*150812a8SEvalZero #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 420*150812a8SEvalZero #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 421*150812a8SEvalZero 422*150812a8SEvalZero #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 423*150812a8SEvalZero #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 424*150812a8SEvalZero #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 425*150812a8SEvalZero #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 426*150812a8SEvalZero 427*150812a8SEvalZero #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 428*150812a8SEvalZero #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 429*150812a8SEvalZero #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 430*150812a8SEvalZero #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 431*150812a8SEvalZero 432*150812a8SEvalZero #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 433*150812a8SEvalZero #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 434*150812a8SEvalZero #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 435*150812a8SEvalZero #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 436*150812a8SEvalZero 437*150812a8SEvalZero #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 438*150812a8SEvalZero #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 439*150812a8SEvalZero #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 440*150812a8SEvalZero #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 441*150812a8SEvalZero 442*150812a8SEvalZero #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 443*150812a8SEvalZero #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 444*150812a8SEvalZero #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 445*150812a8SEvalZero #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 446*150812a8SEvalZero 447*150812a8SEvalZero #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 448*150812a8SEvalZero #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 449*150812a8SEvalZero #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 450*150812a8SEvalZero #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 451*150812a8SEvalZero 452*150812a8SEvalZero #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 453*150812a8SEvalZero #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 454*150812a8SEvalZero #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 455*150812a8SEvalZero #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 456*150812a8SEvalZero 457*150812a8SEvalZero #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 458*150812a8SEvalZero #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 459*150812a8SEvalZero #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 460*150812a8SEvalZero #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 461*150812a8SEvalZero 462*150812a8SEvalZero #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 463*150812a8SEvalZero #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 464*150812a8SEvalZero #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 465*150812a8SEvalZero #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 466*150812a8SEvalZero 467*150812a8SEvalZero #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 468*150812a8SEvalZero #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 469*150812a8SEvalZero #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 470*150812a8SEvalZero #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 471*150812a8SEvalZero 472*150812a8SEvalZero #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 473*150812a8SEvalZero #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 474*150812a8SEvalZero #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 475*150812a8SEvalZero #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 476*150812a8SEvalZero 477*150812a8SEvalZero #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 478*150812a8SEvalZero #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 479*150812a8SEvalZero #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 480*150812a8SEvalZero #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 481*150812a8SEvalZero 482*150812a8SEvalZero #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 483*150812a8SEvalZero #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 484*150812a8SEvalZero #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 485*150812a8SEvalZero #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 486*150812a8SEvalZero 487*150812a8SEvalZero #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 488*150812a8SEvalZero #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 489*150812a8SEvalZero #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 490*150812a8SEvalZero #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 491*150812a8SEvalZero 492*150812a8SEvalZero #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 493*150812a8SEvalZero #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 494*150812a8SEvalZero #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 495*150812a8SEvalZero #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 496*150812a8SEvalZero 497*150812a8SEvalZero #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 498*150812a8SEvalZero #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 499*150812a8SEvalZero #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 500*150812a8SEvalZero #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 501*150812a8SEvalZero 502*150812a8SEvalZero #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 503*150812a8SEvalZero #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 504*150812a8SEvalZero #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 505*150812a8SEvalZero #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 506*150812a8SEvalZero 507*150812a8SEvalZero #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 508*150812a8SEvalZero #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 509*150812a8SEvalZero #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 510*150812a8SEvalZero #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 511*150812a8SEvalZero 512*150812a8SEvalZero #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 513*150812a8SEvalZero #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 514*150812a8SEvalZero #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 515*150812a8SEvalZero #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 516*150812a8SEvalZero 517*150812a8SEvalZero 518*150812a8SEvalZero 519*150812a8SEvalZero 520*150812a8SEvalZero /*lint --flb "Leave library region" */ 521*150812a8SEvalZero 522*150812a8SEvalZero #endif /* NRF51_TO_NRF52810_H */ 523*150812a8SEvalZero 524