issue - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/issue

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
51de4363	22-Nov-2023	sinsanction <[email protected]>	IssueQueue: reduce entryReg width EnqEntry.scala Entries.scala IssueQueue.scala OthersEntry.scala
520f7dac	22-Nov-2023	sinsanction <[email protected]>	Backend: reduce imm width and move imm generating of instr fusion to enq /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala EnqEntry.scala Entries.scala ImmExtractor.scala IssueBlockParams.scala IssueQueue.scala OthersEntry.scala /XiangShan/src/main/scala/xiangshan/package.scala
e08589a5	21-Nov-2023	sinsanction <[email protected]>	EnqEntry, OthersEntry: optimize timing EnqEntry.scala OthersEntry.scala
aa2b5219	20-Nov-2023	sinsanction <[email protected]>	IssueQueue: move enq bypass wakeup to EnqEntry EnqEntry.scala Entries.scala IssueQueue.scala
59f958d4	21-Nov-2023	zhanglyGit <[email protected]>	Backend: optimize IQ timing(ldcancel and flush) EnqEntry.scala IssueQueue.scala OthersEntry.scala
0030d978	20-Nov-2023	zhanglyGit <[email protected]>	Backend: remove unused signals in (BusyTable -> IQ) /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala Dispatch2Iq.scala IssueQueue.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
9910ea36	17-Nov-2023	zhanglyGit <[email protected]>	Backend: refactor load finalBlock timing /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Scheduler.scala
4fa00a44	17-Nov-2023	zhanglyGit <[email protected]>	Backend: refactor load finalBlock timing /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala Scheduler.scala
fb445e8d	16-Nov-2023	zhanglyGit <[email protected]>	Backend: remove cancelNetwork and some cancel false path /XiangShan/src/main/scala/xiangshan/backend/Backend.scala IssueQueue.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
af4bd265	15-Nov-2023	zhanglyGit <[email protected]>	Backend: refactor wakeup and cancel timing EnqEntry.scala Entries.scala IssueQueue.scala MultiWakeupQueue.scala OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
5778f950	03-Nov-2023	sinsanction <[email protected]>	IssueQueue: better implementation of enq_ready IssueQueue.scala
527eefbd	03-Nov-2023	sinsanction <[email protected]>	IssueQueue: all deq ports use the same AgeDetector AgeDetector.scala IssueQueue.scala NewAgeDetector.scala
5a6da888	03-Nov-2023	sinsanction <[email protected]>	IssueQueue: reorder the selection of sub deq result, slightly improve performance Entries.scala IssueQueue.scala
cf4a131a	01-Nov-2023	sinsanction <[email protected]>	IssueQueue: refactor AgeDetector and oldest selection policy /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala AgeDetector.scala Entries.scala IssueQueue.scala NewAgeDetector.scala
ea159d42	30-Oct-2023	sinsanction <[email protected]>	IssueQueue: remove deqResp /XiangShan/src/main/scala/xiangshan/Parameters.scala EnqEntry.scala Entries.scala FuBusyTableWrite.scala IssueQueue.scala OthersEntry.scala Scheduler.scala
f7f73727	25-Oct-2023	sinsanction <[email protected]>	IssueQueue: refactor deq policy /XiangShan/Makefile /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala Entries.scala IssueBlockParams.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
8d081717	24-Oct-2023	szw_kaixin <[email protected]>	backend: control dontTouch opcode by debugEn /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala CancelNetwork.scala Dispatch2Iq.scala Entries.scala FuBusyTableWrite.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
66e57d91	23-Oct-2023	sinsanction <[email protected]>	IssueQueue: optimize timing - use FuTypeOrR for fuType checking /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala FuBusyTableRead.scala FuBusyTableWrite.scala IssueQueue.scala
40283787	18-Oct-2023	sinsanction <[email protected]>	IssueQueue: optimize timing - parameterize deq imms for instruction fusion - refactor deq entry selection /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala Entries.scala IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
559c1710	15-Dec-2023	Haojin Tang <[email protected]>	Scheduler: connect fake port to all zeros Scheduler.scala
56bcaed7	15-Dec-2023	Haojin Tang <[email protected]>	Dispatch2Iq: enable dynamic mem deq port selection * hyu priority for load, by percentage of load instrs among mem instrs * port priority for load/store, by load pressure of IQ /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala Dispatch2Iq.scala IssueBlockParams.scala IssueQueue.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
1548ca99	14-Dec-2023	Haojin Tang <[email protected]>	mdp: enable LFST by default /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala IssueQueue.scala
59a1db8a	14-Dec-2023	Haojin Tang <[email protected]>	mdp: connect missing wires /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala IssueQueue.scala
e77d3114	14-Dec-2023	Haojin Tang <[email protected]>	Issue: split LDU0 from STA0 /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala Scheduler.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
c9933825	15-Nov-2023	Haojin Tang <[email protected]>	Dispatch2Iq: refactor mem deq ports selection Dispatch2Iq.scala
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