1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles._ 9import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 10import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 11import xiangshan.backend.fu.FuType 12import xiangshan.backend.regfile.RfWritePortWithConfig 13import xiangshan.backend.rename.BusyTable 14import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 15 16sealed trait SchedulerType 17 18case class IntScheduler() extends SchedulerType 19case class MemScheduler() extends SchedulerType 20case class VfScheduler() extends SchedulerType 21case class NoScheduler() extends SchedulerType 22 23class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 24 override def shouldBeInlined: Boolean = false 25 26 val numIntStateWrite = backendParams.numPregWb(IntData()) 27 val numVfStateWrite = backendParams.numPregWb(VecData()) 28 29 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 30 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 31 32 lazy val module: SchedulerImpBase = params.schdType match { 33 case IntScheduler() => new SchedulerArithImp(this)(params, p) 34 case MemScheduler() => new SchedulerMemImp(this)(params, p) 35 case VfScheduler() => new SchedulerArithImp(this)(params, p) 36 case _ => null 37 } 38} 39 40class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 41 // params alias 42 private val LoadQueueSize = VirtualLoadQueueSize 43 44 val fromTop = new Bundle { 45 val hartId = Input(UInt(8.W)) 46 } 47 val fromWbFuBusyTable = new Bundle{ 48 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 49 } 50 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 51 52 val fromCtrlBlock = new Bundle { 53 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 54 val flush = Flipped(ValidIO(new Redirect)) 55 } 56 val fromDispatch = new Bundle { 57 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 58 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 59 } 60 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 61 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 62 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 63 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 64 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 65 66 val fromSchedulers = new Bundle { 67 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 68 } 69 70 val toSchedulers = new Bundle { 71 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 72 } 73 74 val fromDataPath = new Bundle { 75 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 76 val og0Cancel = Input(ExuOH(backendParams.numExu)) 77 // Todo: remove this after no cancel signal from og1 78 val og1Cancel = Input(ExuOH(backendParams.numExu)) 79 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 80 // just be compatible to old code 81 def apply(i: Int)(j: Int) = resp(i)(j) 82 } 83 84 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 85 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 87 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 88 89 val memIO = if (params.isMemSchd) Some(new Bundle { 90 val lsqEnqIO = Flipped(new LsqEnqIO) 91 }) else None 92 val fromMem = if (params.isMemSchd) Some(new Bundle { 93 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 94 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 95 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 96 val stIssuePtr = Input(new SqPtr()) 97 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 98 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 99 val lqDeqPtr = Input(new LqPtr) 100 val sqDeqPtr = Input(new SqPtr) 101 // from lsq 102 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 103 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 104 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 105 }) else None 106 val toMem = if (params.isMemSchd) Some(new Bundle { 107 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 108 }) else None 109} 110 111abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 112 extends LazyModuleImp(wrapper) 113 with HasXSParameter 114{ 115 val io = IO(new SchedulerIO()) 116 117 // alias 118 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 119 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 120 private val schdType = params.schdType 121 122 // Modules 123 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 124 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 125 126 // valid count 127 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 128 129 // BusyTable Modules 130 val intBusyTable = schdType match { 131 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 132 case _ => None 133 } 134 135 val vfBusyTable = schdType match { 136 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 137 case _ => None 138 } 139 140 dispatch2Iq.io match { case dp2iq => 141 dp2iq.redirect <> io.fromCtrlBlock.flush 142 dp2iq.in <> io.fromDispatch.uops 143 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 144 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 145 } 146 147 intBusyTable match { 148 case Some(bt) => 149 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 150 btAllocPregs.valid := dpAllocPregs.isInt 151 btAllocPregs.bits := dpAllocPregs.preg 152 } 153 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 154 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 155 wb.bits := io.intWriteBack(i).addr 156 } 157 bt.io.wakeUp := io.fromSchedulers.wakeupVec 158 bt.io.cancel := io.fromDataPath.cancelToBusyTable 159 case None => 160 } 161 162 vfBusyTable match { 163 case Some(bt) => 164 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 165 btAllocPregs.valid := dpAllocPregs.isFp 166 btAllocPregs.bits := dpAllocPregs.preg 167 } 168 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 169 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 170 wb.bits := io.vfWriteBack(i).addr 171 } 172 bt.io.wakeUp := io.fromSchedulers.wakeupVec 173 bt.io.cancel := io.fromDataPath.cancelToBusyTable 174 case None => 175 } 176 177 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 178 val writeback = params.schdType match { 179 case IntScheduler() => io.intWriteBack 180 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 181 case VfScheduler() => io.vfWriteBack 182 case _ => Seq() 183 } 184 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 185 sink.valid := source.wen 186 sink.bits.rfWen := source.intWen 187 sink.bits.fpWen := source.fpWen 188 sink.bits.vecWen := source.vecWen 189 sink.bits.pdest := source.addr 190 } 191 192 // Connect bundles having the same wakeup source 193 issueQueues.zipWithIndex.foreach { case(iq, i) => 194 iq.io.wakeupFromIQ.foreach { wakeUp => 195 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 196 } 197 iq.io.og0Cancel := io.fromDataPath.og0Cancel 198 iq.io.og1Cancel := io.fromDataPath.og1Cancel 199 iq.io.ldCancel := io.ldCancel 200 } 201 202 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 203 issueQueues.flatMap(_.io.wakeupToIQ) 204 .map(x => (x.bits.exuIdx, x)) 205 .toMap 206 207 // Connect bundles having the same wakeup source 208 io.toSchedulers.wakeupVec.foreach { wakeUp => 209 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 210 } 211 212 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 213 toDpDy <> issueQueues(i).io.deqDelay 214 } 215 216 // Response 217 issueQueues.zipWithIndex.foreach { case (iq, i) => 218 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 219 og0Resp := io.fromDataPath(i)(j).og0resp 220 } 221 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 222 og1Resp := io.fromDataPath(i)(j).og1resp 223 } 224 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 225 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 226 finalIssueResp := io.loadFinalIssueResp(i)(j) 227 } else { 228 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 229 } 230 }) 231 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 232 memAddrIssueResp := io.memAddrIssueResp(i)(j) 233 }) 234 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 235 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 236 } 237 238 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 239 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 240 241 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 242 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 243} 244 245class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 246 extends SchedulerImpBase(wrapper) 247 with HasXSParameter 248{ 249// dontTouch(io.vfWbFuBusyTable) 250 println(s"[SchedulerArithImp] " + 251 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 252 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 253 254 issueQueues.zipWithIndex.foreach { case (iq, i) => 255 iq.io.flush <> io.fromCtrlBlock.flush 256 iq.io.enq <> dispatch2Iq.io.out(i) 257 iq.io.wakeupFromWB := wakeupFromWBVec 258 } 259} 260 261// FIXME: Vector mem instructions may not be handled properly! 262class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 263 extends SchedulerImpBase(wrapper) 264 with HasXSParameter 265{ 266 println(s"[SchedulerMemImp] " + 267 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 268 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 269 270 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 271 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0 || iq.params.VstaCnt > 0) // included in memAddrIQs 272 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0 || iq.params.VlduCnt > 0) 273 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0 || iq.params.VstdCnt > 0) 274 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 275 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 276 277 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 278 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 279 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 280 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 281 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 282 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 283 284 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 285 286 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 287 iq.io.flush <> io.fromCtrlBlock.flush 288 iq.io.enq <> dispatch2Iq.io.out(i) 289 iq.io.wakeupFromWB := wakeupFromWBVec 290 } 291 292 ldAddrIQs.zipWithIndex.foreach { 293 case (imp: IssueQueueMemAddrImp, i) => 294 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 295 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 296 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 297 case _ => 298 } 299 300 stAddrIQs.zipWithIndex.foreach { 301 case (imp: IssueQueueMemAddrImp, i) => 302 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 303 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 304 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 305 case _ => 306 } 307 308 hyuIQs.zip(hyuIQIdxs).foreach { 309 case (imp: IssueQueueMemAddrImp, idx) => 310 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 311 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 312 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 313 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 314 // TODO: refactor ditry code 315 imp.io.deqDelay(1).ready := false.B 316 io.toDataPathAfterDelay(idx)(1).valid := false.B 317 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 318 case _ => 319 } 320 321 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 322 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 323 324 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 325 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 326 327 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 328 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 329 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 330 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 331 332 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 333 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 334 335 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 336 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 337 338 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 339 dispatch2Iq.io.out(idxInSchBlk).zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 340 val isAllReady = staIQ.ready && stdIQ.ready 341 dp.ready := isAllReady 342 staIQ.valid := dp.valid && isAllReady 343 stdIQ.valid := dp.valid && isAllReady && FuType.isStore(dp.bits.fuType) 344 } 345 } 346 347 for ((idxInSchBlk, i) <- hyaIdxSeq.zipWithIndex) { 348 dispatch2Iq.io.out(idxInSchBlk).zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 349 val isAllReady = hyaIQ.ready && hydIQ.ready 350 dp.ready := isAllReady 351 hyaIQ.valid := dp.valid && isAllReady 352 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 353 } 354 } 355 356 stDataIQs.zipWithIndex.foreach { case (iq, i) => 357 iq.io.flush <> io.fromCtrlBlock.flush 358 iq.io.wakeupFromWB := wakeupFromWBVec 359 } 360 361 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 362 stdIQEnq.bits := staIQEnq.bits 363 // Store data reuses store addr src(1) in dispatch2iq 364 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 365 // \ 366 // ---src*(1)--> [stdIQ] 367 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 368 // instead of dispatch2Iq.io.out(x).bits.src*(1) 369 val stdIdx = 1 370 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 371 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 372 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(stdIdx) 373 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(stdIdx) 374 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 375 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 376 } 377 378 vecMemIQs.foreach { 379 case imp: IssueQueueVecMemImp => 380 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 381 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 382 // not used 383 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 384 // maybe not used 385 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 386 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 387 case _ => 388 } 389 390 val lsqEnqCtrl = Module(new LsqEnqCtrl) 391 392 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 393 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 394 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 395 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 396 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 397 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 398 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 399} 400