1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utils.OptionWrapper 8import xiangshan._ 9import xiangshan.backend.Bundles._ 10import xiangshan.backend.datapath.DataConfig.{IntData, VAddrData, VecData} 11import xiangshan.backend.datapath.WbConfig.{IntWB, VfWB} 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.regfile.RfWritePortWithConfig 14import xiangshan.backend.rename.BusyTable 15import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr, LqPtr} 16 17sealed trait SchedulerType 18 19case class IntScheduler() extends SchedulerType 20case class MemScheduler() extends SchedulerType 21case class VfScheduler() extends SchedulerType 22case class NoScheduler() extends SchedulerType 23 24class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 25 override def shouldBeInlined: Boolean = false 26 27 val numIntStateWrite = backendParams.numPregWb(IntData()) 28 val numVfStateWrite = backendParams.numPregWb(VecData()) 29 30 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 31 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 32 33 lazy val module: SchedulerImpBase = params.schdType match { 34 case IntScheduler() => new SchedulerArithImp(this)(params, p) 35 case MemScheduler() => new SchedulerMemImp(this)(params, p) 36 case VfScheduler() => new SchedulerArithImp(this)(params, p) 37 case _ => null 38 } 39} 40 41class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 42 // params alias 43 private val LoadQueueSize = VirtualLoadQueueSize 44 45 val fromTop = new Bundle { 46 val hartId = Input(UInt(8.W)) 47 } 48 val fromWbFuBusyTable = new Bundle{ 49 val fuBusyTableRead = MixedVec(params.issueBlockParams.map(x => Input(x.genWbFuBusyTableReadBundle))) 50 } 51 val wbFuBusyTable = MixedVec(params.issueBlockParams.map(x => Output(x.genWbFuBusyTableWriteBundle))) 52 53 val fromCtrlBlock = new Bundle { 54 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 55 val flush = Flipped(ValidIO(new Redirect)) 56 } 57 val fromDispatch = new Bundle { 58 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 59 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 60 } 61 val intWriteBack = MixedVec(Vec(backendParams.numPregWb(IntData()), 62 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 63 val vfWriteBack = MixedVec(Vec(backendParams.numPregWb(VecData()), 64 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 65 val toDataPathAfterDelay: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 66 67 val fromSchedulers = new Bundle { 68 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpInValidBundle) 69 } 70 71 val toSchedulers = new Bundle { 72 val wakeupVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = params.genIQWakeUpOutValidBundle 73 } 74 75 val fromDataPath = new Bundle { 76 val resp: MixedVec[MixedVec[OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 77 val og0Cancel = Input(ExuOH(backendParams.numExu)) 78 // Todo: remove this after no cancel signal from og1 79 val og1Cancel = Input(ExuOH(backendParams.numExu)) 80 val cancelToBusyTable = Vec(backendParams.numExu, Flipped(ValidIO(new CancelSignal))) 81 // just be compatible to old code 82 def apply(i: Int)(j: Int) = resp(i)(j) 83 } 84 85 val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 86 val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) 87 88 val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO)) 89 90 val finalBlockMem = OptionWrapper(params.isMemSchd, MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.numExu, Input(Bool())))))) 91 92 val finalBlockMem = OptionWrapper(params.isMemSchd, MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.numExu, Input(Bool())))))) 93 94 val memIO = if (params.isMemSchd) Some(new Bundle { 95 val lsqEnqIO = Flipped(new LsqEnqIO) 96 }) else None 97 val fromMem = if (params.isMemSchd) Some(new Bundle { 98 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 99 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 100 val hyuFeedback = Flipped(Vec(params.HyuCnt, new MemRSFeedbackIO)) 101 val stIssuePtr = Input(new SqPtr()) 102 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 103 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 104 val lqDeqPtr = Input(new LqPtr) 105 val sqDeqPtr = Input(new SqPtr) 106 // from lsq 107 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 108 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 109 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 110 }) else None 111 val toMem = if (params.isMemSchd) Some(new Bundle { 112 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 113 }) else None 114} 115 116abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 117 extends LazyModuleImp(wrapper) 118 with HasXSParameter 119{ 120 val io = IO(new SchedulerIO()) 121 122 // alias 123 private val iqWakeUpInMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 124 io.fromSchedulers.wakeupVec.map(x => (x.bits.exuIdx, x)).toMap 125 private val schdType = params.schdType 126 127 // Modules 128 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 129 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 130 131 // valid count 132 dispatch2Iq.io.iqValidCnt := issueQueues.filter(_.params.StdCnt == 0).map(_.io.status.validCnt) 133 134 // BusyTable Modules 135 val intBusyTable = schdType match { 136 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite, IntPhyRegs, IntWB()))) 137 case _ => None 138 } 139 140 val vfBusyTable = schdType match { 141 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite, VfPhyRegs, VfWB()))) 142 case _ => None 143 } 144 145 dispatch2Iq.io match { case dp2iq => 146 dp2iq.redirect <> io.fromCtrlBlock.flush 147 dp2iq.in <> io.fromDispatch.uops 148 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 149 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 150 } 151 152 intBusyTable match { 153 case Some(bt) => 154 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 155 btAllocPregs.valid := dpAllocPregs.isInt 156 btAllocPregs.bits := dpAllocPregs.preg 157 } 158 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 159 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 160 wb.bits := io.intWriteBack(i).addr 161 } 162 bt.io.wakeUp := io.fromSchedulers.wakeupVec 163 bt.io.cancel := io.fromDataPath.cancelToBusyTable 164 case None => 165 } 166 167 vfBusyTable match { 168 case Some(bt) => 169 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 170 btAllocPregs.valid := dpAllocPregs.isFp 171 btAllocPregs.bits := dpAllocPregs.preg 172 } 173 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 174 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 175 wb.bits := io.vfWriteBack(i).addr 176 } 177 bt.io.wakeUp := io.fromSchedulers.wakeupVec 178 bt.io.cancel := io.fromDataPath.cancelToBusyTable 179 case None => 180 } 181 182 val wakeupFromWBVec = Wire(params.genWBWakeUpSinkValidBundle) 183 val writeback = params.schdType match { 184 case IntScheduler() => io.intWriteBack 185 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 186 case VfScheduler() => io.vfWriteBack 187 case _ => Seq() 188 } 189 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 190 sink.valid := source.wen 191 sink.bits.rfWen := source.intWen 192 sink.bits.fpWen := source.fpWen 193 sink.bits.vecWen := source.vecWen 194 sink.bits.pdest := source.addr 195 } 196 197 // Connect bundles having the same wakeup source 198 issueQueues.zipWithIndex.foreach { case(iq, i) => 199 iq.io.wakeupFromIQ.foreach { wakeUp => 200 wakeUp := iqWakeUpInMap(wakeUp.bits.exuIdx) 201 } 202 iq.io.og0Cancel := io.fromDataPath.og0Cancel 203 iq.io.og1Cancel := io.fromDataPath.og1Cancel 204 iq.io.ldCancel := io.ldCancel 205 if(params.isMemSchd) { 206 iq.io.finalBlock.zip(io.finalBlockMem.get(i)).foreach(x => x._1 := x._2) 207 } else { 208 iq.io.finalBlock.foreach(_ := false.B) 209 } 210 } 211 212 private val iqWakeUpOutMap: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = 213 issueQueues.flatMap(_.io.wakeupToIQ) 214 .map(x => (x.bits.exuIdx, x)) 215 .toMap 216 217 // Connect bundles having the same wakeup source 218 io.toSchedulers.wakeupVec.foreach { wakeUp => 219 wakeUp := iqWakeUpOutMap(wakeUp.bits.exuIdx) 220 } 221 222 io.toDataPathAfterDelay.zipWithIndex.foreach { case (toDpDy, i) => 223 toDpDy <> issueQueues(i).io.deqDelay 224 } 225 226 // Response 227 issueQueues.zipWithIndex.foreach { case (iq, i) => 228 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 229 og0Resp := io.fromDataPath(i)(j).og0resp 230 } 231 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 232 og1Resp := io.fromDataPath(i)(j).og1resp 233 } 234 iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => 235 if (io.loadFinalIssueResp(i).isDefinedAt(j)) { 236 finalIssueResp := io.loadFinalIssueResp(i)(j) 237 } else { 238 finalIssueResp := 0.U.asTypeOf(finalIssueResp) 239 } 240 }) 241 iq.io.memAddrIssueResp.foreach(_.zipWithIndex.foreach { case (memAddrIssueResp, j) => 242 memAddrIssueResp := io.memAddrIssueResp(i)(j) 243 }) 244 iq.io.wbBusyTableRead := io.fromWbFuBusyTable.fuBusyTableRead(i) 245 io.wbFuBusyTable(i) := iq.io.wbBusyTableWrite 246 } 247 248 println(s"[Scheduler] io.fromSchedulers.wakeupVec: ${io.fromSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 249 println(s"[Scheduler] iqWakeUpInKeys: ${iqWakeUpInMap.keys}") 250 251 println(s"[Scheduler] iqWakeUpOutKeys: ${iqWakeUpOutMap.keys}") 252 println(s"[Scheduler] io.toSchedulers.wakeupVec: ${io.toSchedulers.wakeupVec.map(x => backendParams.getExuName(x.bits.exuIdx))}") 253} 254 255class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 256 extends SchedulerImpBase(wrapper) 257 with HasXSParameter 258{ 259// dontTouch(io.vfWbFuBusyTable) 260 println(s"[SchedulerArithImp] " + 261 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 262 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 263 264 issueQueues.zipWithIndex.foreach { case (iq, i) => 265 iq.io.flush <> io.fromCtrlBlock.flush 266 iq.io.enq <> dispatch2Iq.io.out(i) 267 iq.io.wakeupFromWB := wakeupFromWBVec 268 } 269} 270 271// FIXME: Vector mem instructions may not be handled properly! 272class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 273 extends SchedulerImpBase(wrapper) 274 with HasXSParameter 275{ 276 println(s"[SchedulerMemImp] " + 277 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 278 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 279 280 val memAddrIQs = issueQueues.filter(_.params.isMemAddrIQ) 281 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0 || iq.params.VstaCnt > 0) // included in memAddrIQs 282 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0 || iq.params.VlduCnt > 0) 283 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0 || iq.params.VstdCnt > 0) 284 val vecMemIQs = issueQueues.filter(_.params.isVecMemIQ) 285 val (hyuIQs, hyuIQIdxs) = issueQueues.zipWithIndex.filter(_._1.params.HyuCnt > 0).unzip 286 287 println(s"[SchedulerMemImp] memAddrIQs.size: ${memAddrIQs.size}, enq.size: ${memAddrIQs.map(_.io.enq.size).sum}") 288 println(s"[SchedulerMemImp] stAddrIQs.size: ${stAddrIQs.size }, enq.size: ${stAddrIQs.map(_.io.enq.size).sum}") 289 println(s"[SchedulerMemImp] ldAddrIQs.size: ${ldAddrIQs.size }, enq.size: ${ldAddrIQs.map(_.io.enq.size).sum}") 290 println(s"[SchedulerMemImp] stDataIQs.size: ${stDataIQs.size }, enq.size: ${stDataIQs.map(_.io.enq.size).sum}") 291 println(s"[SchedulerMemImp] hyuIQs.size: ${hyuIQs.size }, enq.size: ${hyuIQs.map(_.io.enq.size).sum}") 292 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 293 294 io.toMem.get.loadFastMatch := 0.U.asTypeOf(io.toMem.get.loadFastMatch) // TODO: is still needed? 295 296 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 297 iq.io.flush <> io.fromCtrlBlock.flush 298 iq.io.enq <> dispatch2Iq.io.out(i) 299 iq.io.wakeupFromWB := wakeupFromWBVec 300 } 301 302 ldAddrIQs.zipWithIndex.foreach { 303 case (imp: IssueQueueMemAddrImp, i) => 304 imp.io.memIO.get.feedbackIO.head := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO.head) 305 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 306 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 307 case _ => 308 } 309 310 stAddrIQs.zipWithIndex.foreach { 311 case (imp: IssueQueueMemAddrImp, i) => 312 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.staFeedback(i) 313 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 314 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 315 case _ => 316 } 317 318 hyuIQs.zip(hyuIQIdxs).foreach { 319 case (imp: IssueQueueMemAddrImp, idx) => 320 imp.io.memIO.get.feedbackIO.head := io.fromMem.get.hyuFeedback.head 321 imp.io.memIO.get.feedbackIO(1) := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO(1)) 322 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 323 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 324 // TODO: refactor ditry code 325 imp.io.deqDelay(1).ready := false.B 326 io.toDataPathAfterDelay(idx)(1).valid := false.B 327 io.toDataPathAfterDelay(idx)(1).bits := 0.U.asTypeOf(io.toDataPathAfterDelay(idx)(1).bits) 328 case _ => 329 } 330 331 private val staIdxSeq = (stAddrIQs).map(iq => iq.params.idxInSchBlk) 332 private val hyaIdxSeq = (hyuIQs).map(iq => iq.params.idxInSchBlk) 333 334 println(s"[SchedulerMemImp] sta iq idx in memSchdBlock: $staIdxSeq") 335 println(s"[SchedulerMemImp] hya iq idx in memSchdBlock: $hyaIdxSeq") 336 337 private val staEnqs = stAddrIQs.map(_.io.enq).flatten 338 private val stdEnqs = stDataIQs.map(_.io.enq).flatten.take(staEnqs.size) 339 private val hyaEnqs = hyuIQs.map(_.io.enq).flatten 340 private val hydEnqs = stDataIQs.map(_.io.enq).flatten.drop(staEnqs.size) 341 342 require(staEnqs.size == stdEnqs.size, s"number of enq ports of store address IQs(${staEnqs.size}) " + 343 s"should be equal to number of enq ports of store data IQs(${stdEnqs.size})") 344 345 require(hyaEnqs.size == hydEnqs.size, s"number of enq ports of hybrid address IQs(${hyaEnqs.size}) " + 346 s"should be equal to number of enq ports of hybrid data IQs(${hydEnqs.size})") 347 348 for ((idxInSchBlk, i) <- staIdxSeq.zipWithIndex) { 349 dispatch2Iq.io.out(idxInSchBlk).zip(staEnqs).zip(stdEnqs).foreach{ case((dp, staIQ), stdIQ) => 350 val isAllReady = staIQ.ready && stdIQ.ready 351 dp.ready := isAllReady 352 staIQ.valid := dp.valid && isAllReady 353 stdIQ.valid := dp.valid && isAllReady && FuType.isStore(dp.bits.fuType) 354 } 355 } 356 357 for ((idxInSchBlk, i) <- hyaIdxSeq.zipWithIndex) { 358 dispatch2Iq.io.out(idxInSchBlk).zip(hyaEnqs).zip(hydEnqs).foreach{ case((dp, hyaIQ), hydIQ) => 359 val isAllReady = hyaIQ.ready && hydIQ.ready 360 dp.ready := isAllReady 361 hyaIQ.valid := dp.valid && isAllReady 362 hydIQ.valid := dp.valid && isAllReady && FuType.FuTypeOrR(dp.bits.fuType, FuType.stu, FuType.mou) 363 } 364 } 365 366 stDataIQs.zipWithIndex.foreach { case (iq, i) => 367 iq.io.flush <> io.fromCtrlBlock.flush 368 iq.io.wakeupFromWB := wakeupFromWBVec 369 } 370 371 (stdEnqs ++ hydEnqs).zip(staEnqs ++ hyaEnqs).zipWithIndex.foreach { case ((stdIQEnq, staIQEnq), i) => 372 stdIQEnq.bits := staIQEnq.bits 373 // Store data reuses store addr src(1) in dispatch2iq 374 // [dispatch2iq] --src*------src*(0)--> [staIQ|hyaIQ] 375 // \ 376 // ---src*(1)--> [stdIQ] 377 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 378 // instead of dispatch2Iq.io.out(x).bits.src*(1) 379 val stdIdx = 1 380 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(stdIdx) 381 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(stdIdx) 382 stdIQEnq.bits.dataSource(0) := staIQEnq.bits.dataSource(stdIdx) 383 stdIQEnq.bits.l1ExuOH(0) := staIQEnq.bits.l1ExuOH(stdIdx) 384 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(stdIdx) 385 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 386 } 387 388 vecMemIQs.foreach { 389 case imp: IssueQueueVecMemImp => 390 imp.io.memIO.get.sqDeqPtr.foreach(_ := io.fromMem.get.sqDeqPtr) 391 imp.io.memIO.get.lqDeqPtr.foreach(_ := io.fromMem.get.lqDeqPtr) 392 // not used 393 imp.io.memIO.get.feedbackIO := 0.U.asTypeOf(imp.io.memIO.get.feedbackIO) 394 // maybe not used 395 imp.io.memIO.get.checkWait.stIssuePtr := io.fromMem.get.stIssuePtr 396 imp.io.memIO.get.checkWait.memWaitUpdateReq := io.fromMem.get.memWaitUpdateReq 397 case _ => 398 } 399 400 val lsqEnqCtrl = Module(new LsqEnqCtrl) 401 402 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 403 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 404 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 405 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 406 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 407 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 408 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 409} 410