xref: /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala (revision af4bd265b9ee15d3efcb7178c3403e5c1714a573) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
14
15
16class OthersEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
17  //input
18  val enq = Flipped(ValidIO(new EntryBundle))
19  val flush = Flipped(ValidIO(new Redirect))
20  val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val og0Cancel = Input(ExuOH(backendParams.numExu))
23  val og1Cancel = Input(ExuOH(backendParams.numExu))
24  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
25  val deqSel = Input(Bool())
26  val transSel = Input(Bool())
27  val issueResp = Flipped(ValidIO(new EntryDeqRespBundle))
28  val deqPortIdxWrite = Input(UInt(1.W))
29  //output
30  val valid = Output(Bool())
31  val canIssue = Output(Bool())
32  val clear = Output(Bool())
33  val fuType = Output(FuType())
34  val dataSource = Output(Vec(params.numRegSrc, DataSource()))
35  val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, ExuOH())))
36  val srcTimer = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, UInt(3.W))))
37  val isFirstIssue = Output(Bool())
38  val entry = ValidIO(new EntryBundle)
39  val robIdx = Output(new RobPtr)
40  val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
41  val deqPortIdxRead = Output(UInt(1.W))
42  val issueTimerRead = Output(UInt(2.W))
43  // mem only
44  val fromMem = if(params.isMemAddrIQ) Some(new Bundle {
45    val stIssuePtr = Input(new SqPtr)
46    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
47  }) else None
48  // vector mem only
49  val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle {
50    val sqDeqPtr = Input(new SqPtr)
51    val lqDeqPtr = Input(new LqPtr)
52  })
53  // debug
54  val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool()))
55
56  def wakeup = wakeUpFromWB ++ wakeUpFromIQ
57}
58
59class OthersEntry(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
60  val io = IO(new OthersEntryIO)
61
62  val validReg = RegInit(false.B)
63  val entryReg = Reg(new EntryBundle)
64
65  val validRegNext = Wire(Bool())
66  val entryRegNext = Wire(new EntryBundle)
67  val flushed = Wire(Bool())
68  val clear = Wire(Bool())
69  val deqSuccess = Wire(Bool())
70  val srcWakeUp = Wire(Vec(params.numRegSrc, Bool()))
71  val srcWakeUpByWB = Wire(Vec(params.numRegSrc, Bool()))
72  val srcCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
73  val srcLoadCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
74  val srcWakeUpByIQVec = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
75  val srcWakeUpByIQWithoutCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
76  val srcWakeUpL1ExuOHOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
77  val srcLoadDependencyOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
78  val srcWakeUpButCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
79  val wakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
80  val shiftedWakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
81  val shiftedWakeupLoadDependencyByIQBypassVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
82  val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
83
84  //Reg
85  validReg := validRegNext
86  entryReg := entryRegNext
87
88  //Wire
89  flushed := entryReg.status.robIdx.needFlush(io.flush)
90  clear := flushed || deqSuccess
91  deqSuccess := io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.fuIdle && !srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B)
92  srcWakeUpByWB := io.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq
93  srcWakeUp := srcWakeUpByWB.zip(srcWakeUpByIQVec).map { case (x, y) => x || y.asUInt.orR }
94
95  shiftedWakeupLoadDependencyByIQVec
96    .zip(wakeupLoadDependencyByIQVec)
97    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
98    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
99      case ((dep, originalDep), deqPortIdx) =>
100        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
101          dep := (originalDep << 2).asUInt | 2.U
102        else
103          dep := originalDep << 1
104    }
105  }
106  shiftedWakeupLoadDependencyByIQBypassVec
107    .zip(wakeupLoadDependencyByIQVec)
108    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
109    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
110      case ((dep, originalDep), deqPortIdx) =>
111        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
112          dep := (originalDep << 2).asUInt | 2.U
113        else
114          dep := originalDep << 1
115    }
116  }
117
118  when(io.enq.valid && io.transSel) {
119    validRegNext := true.B
120  }.elsewhen(clear) {
121    validRegNext := false.B
122  }.otherwise {
123    validRegNext := validReg
124  }
125
126  if (params.hasIQWakeUp) {
127    srcCancelVec.get.zip(srcLoadCancelVec.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) =>
128      val ldTransCancel = Mux(
129        wakeUpByIQVec.asUInt.orR,
130        Mux1H(wakeUpByIQVec, wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), io.ldCancel))),
131        false.B
132      )
133      srcLoadCancel := LoadShouldCancel(entryReg.status.srcLoadDependency.map(_(srcIdx)), io.ldCancel)
134      srcCancel := srcLoadCancel || ldTransCancel
135    }
136    cancelVec.get.foreach(_ := false.B)
137  }
138
139  if (io.wakeUpFromIQ.isEmpty) {
140    srcWakeUpByIQVec := 0.U.asTypeOf(srcWakeUpByIQVec)
141    wakeupLoadDependencyByIQVec := 0.U.asTypeOf(wakeupLoadDependencyByIQVec)
142  } else {
143    val wakeupVec: Seq[Seq[Bool]] = io.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
144      bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)
145    ).toSeq.transpose
146    val cancelSel = io.wakeUpFromIQ.map(x => x.bits.exuIdx).map(x => io.og0Cancel(x))
147    srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
148    srcWakeUpButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel }))
149    srcWakeUpByIQWithoutCancel := wakeupVec.map(x => VecInit(x))
150    wakeupLoadDependencyByIQVec := io.wakeUpFromIQ.map(_.bits.loadDependency).toSeq
151  }
152
153  when(io.enq.valid && io.transSel) {
154    entryRegNext := io.enq.bits
155  }.otherwise {
156    //update status
157    entryRegNext.status.srcState.zip(entryReg.status.srcState).zip(srcWakeUp).zipWithIndex.foreach { case (((stateNext, state), wakeup), srcIdx) =>
158      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
159      stateNext := Mux(cancel, false.B, wakeup | state)
160      if (params.hasIQWakeUp) {
161        cancelVec.get(srcIdx) := cancel
162      }
163    }
164    entryRegNext.status.dataSources.zip(entryReg.status.dataSources).zip(srcWakeUpByIQVec).foreach {
165      case ((dataSourceNext: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]) =>
166        when(wakeUpByIQOH.asUInt.orR) {
167          dataSourceNext.value := DataSource.bypass
168        }.otherwise {
169          dataSourceNext.value := DataSource.reg
170        }
171    }
172    if (params.hasIQWakeUp) {
173      entryRegNext.status.srcWakeUpL1ExuOH.get.zip(srcWakeUpByIQVec).zip(srcWakeUp).zipWithIndex.foreach {
174        case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
175          when(wakeUpByIQOH.asUInt.orR) {
176            exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.toSeq.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)))
177          }.elsewhen(wakeUp) {
178            exuOH := 0.U.asTypeOf(exuOH)
179          }.otherwise {
180            exuOH := entryReg.status.srcWakeUpL1ExuOH.get(srcIdx)
181          }
182      }
183      entryRegNext.status.srcTimer.get.zip(entryReg.status.srcTimer.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach {
184        case (((srcIssuedTimerNext, srcIssuedTimer), wakeUpByIQOH: Vec[Bool]), srcIdx) =>
185          srcIssuedTimerNext := MuxCase(3.U, Seq(
186            // T0: waked up by IQ, T1: reset timer as 1
187            wakeUpByIQOH.asUInt.orR -> 2.U,
188            // do not overflow
189            srcIssuedTimer.andR -> srcIssuedTimer,
190            // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq
191            (validReg && SrcState.isReady(entryReg.status.srcState(srcIdx)) && entryReg.status.srcWakeUpL1ExuOH.get.asUInt.orR) -> (srcIssuedTimer + 1.U)
192          ))
193      }
194      entryRegNext.status.srcLoadDependency.get.zip(entryReg.status.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
195        case (((loadDependencyNext, loadDependency), wakeUpByIQVec), wakeup) =>
196          loadDependencyNext :=
197            Mux(wakeup,
198              Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQVec), 0.U.asTypeOf(loadDependency)),
199              Mux(validReg && loadDependency.asUInt.orR, VecInit(loadDependency.map(i => i(i.getWidth - 2, 0) << 1)), loadDependency)
200            )
201      }
202    }
203    entryRegNext.status.issueTimer := "b10".U //otherwise
204    entryRegNext.status.deqPortIdx := 0.U //otherwise
205    when(io.deqSel){
206      entryRegNext.status.issueTimer := 0.U
207      entryRegNext.status.deqPortIdx := io.deqPortIdxWrite
208    }.elsewhen(entryReg.status.issued){
209      entryRegNext.status.issueTimer := entryReg.status.issueTimer + 1.U
210      entryRegNext.status.deqPortIdx := entryReg.status.deqPortIdx
211    }
212    entryRegNext.status.psrc := entryReg.status.psrc
213    entryRegNext.status.srcType := entryReg.status.srcType
214    entryRegNext.status.fuType := entryReg.status.fuType
215    entryRegNext.status.robIdx := entryReg.status.robIdx
216    entryRegNext.status.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
217    entryRegNext.status.issued := entryReg.status.issued // otherwise
218    when(srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B) || srcWakeUpButCancel.map(_.fold(false.B)(_ || _)).fold(false.B)(_ || _)) {
219      entryRegNext.status.issued := false.B
220    }.elsewhen(io.deqSel) {
221      entryRegNext.status.issued := true.B
222    }.elsewhen(io.issueResp.valid && RSFeedbackType.isBlocked(io.issueResp.bits.respType)) {
223      entryRegNext.status.issued := false.B
224    }.elsewhen(!entryReg.status.srcReady) {
225      entryRegNext.status.issued := false.B
226    }
227    entryRegNext.status.firstIssue := io.deqSel || entryReg.status.firstIssue
228    entryRegNext.status.blocked := false.B //todo
229    //remain imm and payload
230    entryRegNext.imm := entryReg.imm
231    entryRegNext.payload := entryReg.payload
232    if (params.needPc) {
233      entryRegNext.status.pc.get := entryReg.status.pc.get
234    }
235  }
236  if(params.hasIQWakeUp) {
237    srcWakeUpL1ExuOHOut.get.zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).zipWithIndex.foreach {
238      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
239        when(wakeUpByIQOH.asUInt.orR) {
240          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
241        }.elsewhen(wakeUp) {
242          exuOH := 0.U.asTypeOf(exuOH)
243        }.otherwise {
244          exuOH := entryReg.status.srcWakeUpL1ExuOH.get(srcIdx)
245        }
246    }
247    srcLoadDependencyOut.get.zip(entryReg.status.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
248      case (((loadDependencyOut, loadDependency), wakeUpByIQVec), wakeup) =>
249        loadDependencyOut :=
250          Mux(wakeup,
251            Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQBypassVec), 0.U.asTypeOf(loadDependency)),
252            loadDependency
253          )
254    }
255  }
256  val canIssue = entryReg.status.canIssue && validReg && !srcCancelVec.getOrElse(false.B).asUInt.orR
257  val canIssueBypass = validReg && !entryReg.status.issued && !entryReg.status.blocked &&
258    VecInit(entryReg.status.srcState.zip(srcWakeUpByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) =>
259      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
260      Mux(cancel, false.B, wakeupVec.asUInt.orR | state)
261    }).asUInt.andR
262  io.dataSource.zip(entryReg.status.dataSources).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
263    case (((dataSourceOut: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
264      when(wakeUpByIQOH.asUInt.orR) {
265        dataSourceOut.value := DataSource.forward
266      }.elsewhen(wakeUpAll) {
267        dataSourceOut.value := DataSource.reg
268      }.otherwise {
269        dataSourceOut.value := dataSource.value
270      }
271  }
272  if (params.hasIQWakeUp) {
273    io.srcTimer.get.zip(entryReg.status.srcTimer.get).zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).foreach {
274      case (((srcTimerOut, srcTimer), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
275        when(wakeUpByIQOH.asUInt.orR) {
276          srcTimerOut := 1.U
277        }.otherwise {
278          srcTimerOut := srcTimer
279        }
280    }
281  }
282
283  //output
284  io.canIssue := canIssue || canIssueBypass
285  io.clear := clear
286  io.fuType := entryReg.status.fuType
287  io.srcWakeUpL1ExuOH.foreach(_ := Mux(canIssueBypass && !canIssue, srcWakeUpL1ExuOHOut.get, entryReg.status.srcWakeUpL1ExuOH.get))
288  io.valid := validReg
289  io.isFirstIssue := !entryReg.status.firstIssue
290  io.entry.valid := validReg
291  io.entry.bits := entryReg
292  io.entry.bits.status.srcLoadDependency.foreach(_ := Mux(canIssueBypass && !canIssue, srcLoadDependencyOut.get, entryReg.status.srcLoadDependency.get))
293  io.robIdx := entryReg.status.robIdx
294  io.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
295  io.issueTimerRead := entryReg.status.issueTimer
296  io.deqPortIdxRead := entryReg.status.deqPortIdx
297  io.cancel.foreach(_ := cancelVec.get.asUInt.orR)
298}
299
300class OthersEntryMem()(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry
301  with HasCircularQueuePtrHelper {
302
303  val fromMem = io.fromMem.get
304
305  val memStatus = entryReg.status.mem.get
306  val memStatusNext = entryRegNext.status.mem.get
307  // load cannot be issued before older store, unless meet some condition
308  val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr)
309
310  val deqFailedForStdInvalid = io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.dataInvalid
311
312  val staWaitedReleased = Cat(
313    fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value)
314  ).orR
315  val stdWaitedReleased = Cat(
316    fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value)
317  ).orR
318  val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait
319  val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd
320  val waitStd = !olderStdReady
321  val waitSta = !olderStaNotViolate
322
323  when(io.enq.valid && io.transSel) {
324    memStatusNext.waitForSqIdx := io.enq.bits.status.mem.get.waitForSqIdx
325    // update by lfst at dispatch stage
326    memStatusNext.waitForRobIdx := io.enq.bits.status.mem.get.waitForRobIdx
327    // new load inst don't known if it is blocked by store data ahead of it
328    memStatusNext.waitForStd := false.B
329    // update by ssit at rename stage
330    memStatusNext.strictWait := io.enq.bits.status.mem.get.strictWait
331    memStatusNext.sqIdx := io.enq.bits.status.mem.get.sqIdx
332  }.elsewhen(deqFailedForStdInvalid) {
333    // Todo: check if need assign statusNext.block
334    memStatusNext.waitForSqIdx := io.issueResp.bits.dataInvalidSqIdx
335    memStatusNext.waitForRobIdx := memStatus.waitForRobIdx
336    memStatusNext.waitForStd := true.B
337    memStatusNext.strictWait := memStatus.strictWait
338    memStatusNext.sqIdx := memStatus.sqIdx
339  }.otherwise {
340    memStatusNext := memStatus
341  }
342
343  val shouldBlock = Mux(io.enq.valid && io.transSel, io.enq.bits.status.blocked, entryReg.status.blocked)
344  val blockNotReleased = waitStd || waitSta
345  val respBlock = deqFailedForStdInvalid
346  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
347}
348
349class OthersEntryVecMemAddr()(implicit p: Parameters, params: IssueBlockParams) extends OthersEntryMem {
350
351  require(params.isVecMemAddrIQ, "OthersEntryVecMemAddr can only be instance of VecMemAddr IQ")
352
353  val vecMemStatus = entryReg.status.vecMem.get
354  val vecMemStatusNext = entryRegNext.status.vecMem.get
355  val fromLsq = io.fromLsq.get
356
357  when(io.enq.valid && io.transSel) {
358    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
359    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
360  }.otherwise {
361    vecMemStatusNext := vecMemStatus
362  }
363
364  val isLsqHead = {
365    // if (params.isVecLdAddrIQ)
366      entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr &&
367    // else
368      entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr
369  }
370  dontTouch(shouldBlock)
371  dontTouch(blockNotReleased)
372  dontTouch(blockedByOlderStore)
373  dontTouch(respBlock)
374  dontTouch(isLsqHead)
375  dontTouch(waitStd)
376  dontTouch(waitSta)
377  dontTouch(memStatusNext)
378  dontTouch(fromMem)
379  dontTouch(io.issueResp)
380  dontTouch(isLsqHead)
381
382  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
383}
384
385class OthersEntryVecMemData()(implicit p: Parameters, params: IssueBlockParams) extends OthersEntry
386  with HasCircularQueuePtrHelper {
387
388  require(params.isVecStDataIQ, "OthersEntryVecMemData can only be instance of VecMemData IQ")
389
390  val vecMemStatus = entryReg.status.vecMem.get
391  val vecMemStatusNext = entryRegNext.status.vecMem.get
392  val fromLsq = io.fromLsq.get
393
394  when(io.enq.valid && io.transSel) {
395    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
396    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
397  }.otherwise {
398    vecMemStatusNext := vecMemStatus
399  }
400
401  val isLsqHead = entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value
402
403  entryRegNext.status.blocked := !isLsqHead
404}
405
406object OthersEntry {
407  def apply(implicit p: Parameters, iqParams: IssueBlockParams): OthersEntry = {
408    iqParams.schdType match {
409      case IntScheduler() => new OthersEntry()
410      case MemScheduler() =>
411        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new OthersEntryMem()
412        else if (iqParams.isVecMemAddrIQ) new OthersEntryVecMemAddr()
413        else if (iqParams.isVecStDataIQ) new OthersEntryVecMemData()
414        else new OthersEntry()
415      case VfScheduler() => new OthersEntry()
416      case _ => null
417    }
418  }
419}