xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala (revision aa2b521979d7d37fba77dc1cc46579eb198def48) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
14
15
16class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
17  //input
18  val enq = Flipped(ValidIO(new EntryBundle))
19  val flush = Flipped(ValidIO(new Redirect))
20  val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val og0Cancel = Input(ExuOH(backendParams.numExu))
23  val og1Cancel = Input(ExuOH(backendParams.numExu))
24  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
25  val enqDelayWakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
26  val enqDelayWakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
27  val enqDelayOg0Cancel = Input(ExuOH(backendParams.numExu))
28  val enqDelayLdCancel = Vec(backendParams.LduCnt, Flipped(new LoadCancelIO))
29  val deqSel = Input(Bool())
30  val deqPortIdxWrite = Input(UInt(1.W))
31  val transSel = Input(Bool())
32  val issueResp = Flipped(ValidIO(new EntryDeqRespBundle))
33  //output
34  val valid = Output(Bool())
35  val canIssue = Output(Bool())
36  val clear = Output(Bool())
37  val fuType = Output(FuType())
38  val dataSource = Output(Vec(params.numRegSrc, DataSource()))
39  val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, ExuOH())))
40  val srcTimer = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, UInt(3.W))))
41  val transEntry =  ValidIO(new EntryBundle)
42  val isFirstIssue = Output(Bool())
43  val entry = ValidIO(new EntryBundle)
44  val robIdx = Output(new RobPtr)
45  val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
46  val deqPortIdxRead = Output(UInt(1.W))
47  val issueTimerRead = Output(UInt(2.W))
48  // mem only
49  val fromMem = if(params.isMemAddrIQ) Some(new Bundle {
50    val stIssuePtr = Input(new SqPtr)
51    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
52  }) else None
53  // vector mem only
54  val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle {
55    val sqDeqPtr = Input(new SqPtr)
56    val lqDeqPtr = Input(new LqPtr)
57  })
58  // debug
59  val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool()))
60
61  def wakeup = wakeUpFromWB ++ wakeUpFromIQ
62}
63
64class EnqEntry(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
65  val io = IO(new EnqEntryIO)
66
67  val validReg = RegInit(false.B)
68  val entryReg = Reg(new EntryBundle)
69  val enqDelayValidReg = RegInit(false.B)
70
71  val validRegNext = Wire(Bool())
72  val entryRegNext = Wire(new EntryBundle)
73  val entryUpdate = Wire(new EntryBundle)
74  val enqDelayValidRegNext = Wire(Bool())
75  val enqReady = Wire(Bool())
76  val clear = Wire(Bool())
77  val flushed = Wire(Bool())
78  val deqSuccess = Wire(Bool())
79  val srcWakeUp = Wire(Vec(params.numRegSrc, Bool()))
80  val srcWakeUpByWB = Wire(Vec(params.numRegSrc, Bool()))
81  val srcCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
82  val srcLoadCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
83  val srcWakeUpByIQVec = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
84  val srcWakeUpByIQWithoutCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
85  val srcWakeUpButCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
86  val srcWakeUpL1ExuOHOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
87  val srcLoadDependencyOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
88  val wakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
89  val shiftedWakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
90  val shiftedWakeupLoadDependencyByIQBypassVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
91  val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
92
93  val currentStatus = Wire(new Status())
94  val enqDelaySrcState = Wire(Vec(params.numRegSrc, SrcState()))
95  val enqDelayDataSources = Wire(Vec(params.numRegSrc, DataSource()))
96  val enqDelaySrcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
97  val enqDelaySrcTimer = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, UInt(3.W))))
98  val enqDelaySrcLoadDependency = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
99
100  val enqDelaySrcWakeUpByWB: Vec[UInt] = Wire(Vec(params.numRegSrc, SrcState()))
101  val enqDelaySrcWakeUpByIQ: Vec[UInt] = Wire(Vec(params.numRegSrc, SrcState()))
102  val enqDelaySrcWakeUpByIQVec: Vec[Vec[Bool]] = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
103  val enqDelayShiftedWakeupLoadDependencyByIQVec: Vec[Vec[UInt]] = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
104
105  //Reg
106  validReg := validRegNext
107  entryReg := entryRegNext
108  enqDelayValidReg := enqDelayValidRegNext
109
110  //Wire
111  when(io.enq.valid && enqReady) {
112    validRegNext := true.B
113  }.elsewhen(clear) {
114    validRegNext := false.B
115  }.otherwise {
116    validRegNext := validReg
117  }
118
119  when(io.enq.valid && enqReady) {
120    entryRegNext := io.enq.bits
121  }.otherwise {
122    entryRegNext := entryUpdate
123  }
124
125  when(io.enq.valid && enqReady) {
126    enqDelayValidRegNext := true.B
127  }.otherwise {
128    enqDelayValidRegNext := false.B
129  }
130
131  enqReady := !validReg || clear
132  clear := flushed || io.transSel || deqSuccess
133  flushed := entryReg.status.robIdx.needFlush(io.flush)
134  deqSuccess := io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.fuIdle && !srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B)
135
136  // current wakeup
137  srcWakeUpByWB := io.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq
138  srcWakeUp := srcWakeUpByWB.zip(srcWakeUpByIQVec).map { case (x, y) => x || y.asUInt.orR }
139
140  shiftedWakeupLoadDependencyByIQVec
141    .zip(wakeupLoadDependencyByIQVec)
142    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
143    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
144      case ((dep, originalDep), deqPortIdx) =>
145        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
146          dep := (originalDep << 2).asUInt | 2.U
147        else
148          dep := originalDep << 1
149    }
150  }
151  shiftedWakeupLoadDependencyByIQBypassVec
152    .zip(wakeupLoadDependencyByIQVec)
153    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
154    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
155      case ((dep, originalDep), deqPortIdx) =>
156        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
157          dep := (originalDep << 1).asUInt | 1.U
158        else
159          dep := originalDep
160    }
161  }
162
163  if (params.hasIQWakeUp) {
164    srcCancelVec.get.zip(srcLoadCancelVec.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) =>
165      val ldTransCancel = Mux(
166        wakeUpByIQVec.asUInt.orR,
167        Mux1H(wakeUpByIQVec, wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), io.ldCancel))),
168        false.B
169      )
170      srcLoadCancel := LoadShouldCancel(currentStatus.srcLoadDependency.map(_(srcIdx)), io.ldCancel)
171      srcCancel := srcLoadCancel || ldTransCancel
172    }
173  }
174
175  if (io.wakeUpFromIQ.isEmpty) {
176    srcWakeUpByIQVec := 0.U.asTypeOf(srcWakeUpByIQVec)
177    wakeupLoadDependencyByIQVec := 0.U.asTypeOf(wakeupLoadDependencyByIQVec)
178  } else {
179    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
180      bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)
181    ).toIndexedSeq.transpose
182    val cancelSel = io.wakeUpFromIQ.map(x => x.bits.exuIdx).map(x => io.og0Cancel(x))
183    srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
184    srcWakeUpButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel }))
185    srcWakeUpByIQWithoutCancel := wakeupVec.map(x => VecInit(x))
186    wakeupLoadDependencyByIQVec := io.wakeUpFromIQ.map(_.bits.loadDependency).toSeq
187  }
188
189  // enq delay wakeup
190  enqDelaySrcWakeUpByWB.zipWithIndex.foreach { case (wakeup, i) =>
191    wakeup := io.enqDelayWakeUpFromWB.map(x => x.bits.wakeUp(Seq((entryReg.status.psrc(i), entryReg.status.srcType(i))), x.valid).head
192    ).reduce(_ || _)
193  }
194
195  if (params.hasIQWakeUp) {
196    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.enqDelayWakeUpFromIQ.map( x =>
197      x.bits.wakeUp(entryReg.status.psrc.zip(entryReg.status.srcType), x.valid)
198    ).toIndexedSeq.transpose
199    val cancelSel = io.enqDelayWakeUpFromIQ.map(x => x.bits.exuIdx).map(io.enqDelayOg0Cancel(_))
200    enqDelaySrcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
201  } else {
202    enqDelaySrcWakeUpByIQVec := 0.U.asTypeOf(enqDelaySrcWakeUpByIQVec)
203  }
204
205  if (params.hasIQWakeUp) {
206    enqDelaySrcWakeUpByIQ.zipWithIndex.foreach { case (wakeup, i) =>
207      val ldTransCancel = Mux1H(enqDelaySrcWakeUpByIQVec(i), io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency).map(dp => LoadShouldCancel(Some(dp), io.enqDelayLdCancel)).toSeq)
208      wakeup := enqDelaySrcWakeUpByIQVec(i).asUInt.orR && !ldTransCancel
209    }
210  } else {
211    enqDelaySrcWakeUpByIQ := 0.U.asTypeOf(enqDelaySrcWakeUpByIQ)
212  }
213
214  enqDelayShiftedWakeupLoadDependencyByIQVec.zip(io.enqDelayWakeUpFromIQ.map(_.bits.loadDependency))
215    .zip(params.wakeUpInExuSources.map(_.name)).foreach { case ((dps, ldps), name) =>
216    dps.zip(ldps).zipWithIndex.foreach { case ((dp, ldp), deqPortIdx) =>
217      if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
218        dp := (ldp << 2).asUInt | 2.U
219      else
220        dp := ldp << 1
221    }
222  }
223
224  for(i <- 0 until params.numRegSrc) {
225    enqDelaySrcState(i) := entryReg.status.srcState(i) | enqDelaySrcWakeUpByWB(i) | enqDelaySrcWakeUpByIQ(i)
226    enqDelayDataSources(i).value := Mux(enqDelaySrcWakeUpByIQ(i).asBool, DataSource.bypass, DataSource.reg)
227    if (params.hasIQWakeUp) {
228      val wakeUpValid = enqDelaySrcWakeUpByIQVec(i).asUInt.orR
229      val wakeUpOH = enqDelaySrcWakeUpByIQVec(i)
230      enqDelaySrcWakeUpL1ExuOH.get(i) := Mux1H(wakeUpOH, io.enqDelayWakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
231      enqDelaySrcTimer.get(i) := Mux(wakeUpValid, 2.U, 3.U)
232      enqDelaySrcLoadDependency.get(i) := Mux1H(wakeUpOH, enqDelayShiftedWakeupLoadDependencyByIQVec)
233    }
234  }
235  currentStatus := entryReg.status
236  when (enqDelayValidReg) {
237    currentStatus.srcState := enqDelaySrcState
238    currentStatus.dataSources := enqDelayDataSources
239    currentStatus.srcWakeUpL1ExuOH.foreach(_ := enqDelaySrcWakeUpL1ExuOH.get)
240    currentStatus.srcTimer.foreach(_ := enqDelaySrcTimer.get)
241    currentStatus.srcLoadDependency.foreach(_ := enqDelaySrcLoadDependency.get)
242  }
243
244  //entryUpdate
245  entryUpdate.status.srcState.zip(currentStatus.srcState).zip(srcWakeUp).zipWithIndex.foreach { case (((stateNext, state), wakeup), srcIdx) =>
246    val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
247    stateNext := Mux(cancel, false.B, wakeup | state)
248    if (params.hasIQWakeUp) {
249      cancelVec.get(srcIdx) := cancel
250    }
251  }
252  entryUpdate.status.dataSources.zip(srcWakeUpByIQVec).foreach {
253    case (dataSourceNext: DataSource, wakeUpByIQOH: Vec[Bool]) =>
254      when(wakeUpByIQOH.asUInt.orR) {
255        dataSourceNext.value := DataSource.bypass
256      }.otherwise {
257        dataSourceNext.value := DataSource.reg
258      }
259  }
260  if (params.hasIQWakeUp) {
261    entryUpdate.status.srcWakeUpL1ExuOH.get.zip(srcWakeUpByIQVec).zip(srcWakeUp).zipWithIndex.foreach {
262      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
263        when(wakeUpByIQOH.asUInt.orR) {
264          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.toSeq.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)))
265        }.elsewhen(wakeUp) {
266          exuOH := 0.U.asTypeOf(exuOH)
267        }.otherwise {
268          exuOH := currentStatus.srcWakeUpL1ExuOH.get(srcIdx)
269        }
270    }
271    srcWakeUpL1ExuOHOut.get.zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).zipWithIndex.foreach {
272      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
273        when(wakeUpByIQOH.asUInt.orR) {
274          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
275        }.elsewhen(wakeUp) {
276          exuOH := 0.U.asTypeOf(exuOH)
277        }.otherwise {
278          exuOH := currentStatus.srcWakeUpL1ExuOH.get(srcIdx)
279        }
280    }
281    entryUpdate.status.srcTimer.get.zip(currentStatus.srcTimer.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach {
282      case (((srcIssuedTimerNext, srcIssuedTimer), wakeUpByIQOH: Vec[Bool]), srcIdx) =>
283        srcIssuedTimerNext := MuxCase(3.U, Seq(
284          // T0: waked up by IQ, T1: reset timer as 1
285          wakeUpByIQOH.asUInt.orR -> 2.U,
286          // do not overflow
287          srcIssuedTimer.andR -> srcIssuedTimer,
288          // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq
289          (validReg && SrcState.isReady(currentStatus.srcState(srcIdx)) && currentStatus.srcWakeUpL1ExuOH.get.asUInt.orR) -> (srcIssuedTimer + 1.U)
290        ))
291    }
292    entryUpdate.status.srcLoadDependency.get.zip(currentStatus.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
293      case (((loadDependencyNext, loadDependency), wakeUpByIQVec), wakeup) =>
294        loadDependencyNext :=
295          Mux(wakeup,
296            Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQVec), 0.U.asTypeOf(loadDependency)),
297            Mux(validReg && loadDependency.asUInt.orR, VecInit(loadDependency.map(i => i(i.getWidth - 2, 0) << 1)), loadDependency)
298          )
299    }
300    srcLoadDependencyOut.get.zip(currentStatus.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
301      case (((loadDependencyOut, loadDependency), wakeUpByIQVec), wakeup) =>
302        loadDependencyOut :=
303          Mux(wakeup,
304            Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQBypassVec),
305            loadDependency
306          )
307    }
308  }
309  entryUpdate.status.issueTimer := "b10".U //otherwise
310  entryUpdate.status.deqPortIdx := 0.U //otherwise
311  when(io.deqSel) {
312    entryUpdate.status.issueTimer := 0.U
313    entryUpdate.status.deqPortIdx := io.deqPortIdxWrite
314  }.elsewhen(entryReg.status.issued){
315    entryUpdate.status.issueTimer := entryReg.status.issueTimer + 1.U
316    entryUpdate.status.deqPortIdx := entryReg.status.deqPortIdx
317  }
318  entryUpdate.status.psrc := entryReg.status.psrc
319  entryUpdate.status.srcType := entryReg.status.srcType
320  entryUpdate.status.fuType := entryReg.status.fuType
321  entryUpdate.status.robIdx := entryReg.status.robIdx
322  entryUpdate.status.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
323  entryUpdate.status.issued := entryReg.status.issued // otherwise
324  when(srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B) || srcWakeUpButCancel.map(_.fold(false.B)(_ || _)).fold(false.B)(_ || _)) {
325    entryUpdate.status.issued := false.B
326  }.elsewhen(io.deqSel) {
327    entryUpdate.status.issued := true.B
328  }.elsewhen(io.issueResp.valid && RSFeedbackType.isBlocked(io.issueResp.bits.respType)) {
329    entryUpdate.status.issued := false.B
330  }.elsewhen(!currentStatus.srcReady) {
331    entryUpdate.status.issued := false.B
332  }
333  entryUpdate.status.firstIssue := io.deqSel || entryReg.status.firstIssue
334  entryUpdate.status.blocked := false.B //todo
335  //remain imm and payload
336  entryUpdate.imm := entryReg.imm
337  entryUpdate.payload := entryReg.payload
338  if(params.needPc) {
339    entryUpdate.status.pc.get := entryReg.status.pc.get
340  }
341
342  //output
343  val canIssue = currentStatus.canIssue && validReg && !srcCancelVec.getOrElse(false.B).asUInt.orR
344  val canIssueBypass = validReg && !entryReg.status.issued && !entryReg.status.blocked &&
345    VecInit(currentStatus.srcState.zip(srcWakeUpByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) =>
346      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
347      Mux(cancel, false.B, wakeupVec.asUInt.orR | state)
348    }).asUInt.andR
349  io.dataSource.zip(currentStatus.dataSources).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
350    case (((dataSourceOut: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
351      when(wakeUpByIQOH.asUInt.orR) {
352        dataSourceOut.value := DataSource.forward
353      }.elsewhen(wakeUpAll) {
354        dataSourceOut.value := DataSource.reg
355      }.otherwise {
356        dataSourceOut.value := dataSource.value
357      }
358  }
359  if (params.hasIQWakeUp) {
360    io.srcTimer.get.zip(currentStatus.srcTimer.get).zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).foreach {
361      case (((srcTimerOut, srcTimer), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
362        when(wakeUpByIQOH.asUInt.orR) {
363          srcTimerOut := 1.U
364        }.otherwise {
365          srcTimerOut := srcTimer
366        }
367    }
368    io.srcWakeUpL1ExuOH.get := Mux(canIssueBypass && !canIssue, srcWakeUpL1ExuOHOut.get, currentStatus.srcWakeUpL1ExuOH.get)
369  }
370  io.transEntry.valid := validReg && io.transSel && !flushed && !deqSuccess
371  io.transEntry.bits := entryUpdate
372  io.canIssue := (canIssue || canIssueBypass) && !flushed
373  io.clear := clear
374  io.fuType := entryReg.status.fuType
375  io.valid := validReg
376  io.isFirstIssue := !entryReg.status.firstIssue
377  io.entry.valid := validReg
378  io.entry.bits := entryReg
379  io.entry.bits.status := currentStatus
380  io.entry.bits.status.srcLoadDependency.foreach(_ := Mux(canIssueBypass && !canIssue, srcLoadDependencyOut.get, currentStatus.srcLoadDependency.get))
381  io.robIdx := entryReg.status.robIdx
382  io.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
383  io.issueTimerRead := entryReg.status.issueTimer
384  io.deqPortIdxRead := entryReg.status.deqPortIdx
385  io.cancel.foreach(_ := cancelVec.get.asUInt.orR)
386}
387
388class EnqEntryMem()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
389  with HasCircularQueuePtrHelper {
390  val fromMem = io.fromMem.get
391
392  val memStatus = entryReg.status.mem.get
393  println("memStatus" + memStatus)
394  val memStatusNext = entryRegNext.status.mem.get
395  val memStatusUpdate = entryUpdate.status.mem.get
396
397  // load cannot be issued before older store, unless meet some condition
398  val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr)
399
400  val deqFailedForStdInvalid = io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.dataInvalid
401
402  val staWaitedReleased = Cat(
403    fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value)
404  ).orR
405  val stdWaitedReleased = Cat(
406    fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value)
407  ).orR
408  val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait
409  val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd
410  val waitStd = !olderStdReady
411  val waitSta = !olderStaNotViolate
412
413  when (io.enq.valid && enqReady) {
414    memStatusNext.waitForSqIdx := io.enq.bits.status.mem.get.waitForSqIdx
415    // update by lfst at dispatch stage
416    memStatusNext.waitForRobIdx := io.enq.bits.status.mem.get.waitForRobIdx
417    // new load inst don't known if it is blocked by store data ahead of it
418    memStatusNext.waitForStd := false.B
419    // update by ssit at rename stage
420    memStatusNext.strictWait := io.enq.bits.status.mem.get.strictWait
421    memStatusNext.sqIdx := io.enq.bits.status.mem.get.sqIdx
422  }.otherwise {
423    memStatusNext := memStatusUpdate
424  }
425
426  when(deqFailedForStdInvalid) {
427    memStatusUpdate.waitForSqIdx := io.issueResp.bits.dataInvalidSqIdx
428    memStatusUpdate.waitForRobIdx := memStatus.waitForRobIdx
429    memStatusUpdate.waitForStd := true.B
430    memStatusUpdate.strictWait := memStatus.strictWait
431    memStatusUpdate.sqIdx := memStatus.sqIdx
432  }.otherwise {
433    memStatusUpdate := memStatus
434  }
435
436  val shouldBlock = Mux(io.enq.valid && enqReady, io.enq.bits.status.blocked, entryReg.status.blocked)
437  val blockNotReleased = waitStd || waitSta
438  val respBlock = deqFailedForStdInvalid
439  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
440  entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
441
442}
443
444class EnqEntryVecMemAddr()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntryMem {
445
446  require(params.isVecMemAddrIQ, "EnqEntryVecMemAddr can only be instance of VecMemAddr IQ")
447
448  val vecMemStatus = entryReg.status.vecMem.get
449  val vecMemStatusNext = entryRegNext.status.vecMem.get
450  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
451  val fromLsq = io.fromLsq.get
452
453  when (io.enq.valid && enqReady) {
454    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
455    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
456  }.otherwise {
457    vecMemStatusNext := vecMemStatusUpdate
458  }
459  vecMemStatusUpdate := vecMemStatus
460
461  val isLsqHead = {
462    // if (params.isVecLdAddrIQ)
463      entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr &&
464    // else
465      entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr
466  }
467
468  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
469  entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
470}
471
472class EnqEntryVecMemData()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
473  with HasCircularQueuePtrHelper {
474
475  require(params.isVecStDataIQ, "EnqEntryVecMemData can only be instance of VecMemData IQ")
476
477  val vecMemStatus = entryReg.status.vecMem.get
478  val vecMemStatusNext = entryRegNext.status.vecMem.get
479  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
480  val fromLsq = io.fromLsq.get
481
482  when (io.enq.valid && enqReady) {
483    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
484    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
485  }.otherwise {
486    vecMemStatusNext := vecMemStatusUpdate
487  }
488  vecMemStatusUpdate := vecMemStatus
489
490  val isLsqHead = entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value
491
492  entryRegNext.status.blocked := !isLsqHead
493  entryUpdate.status.blocked := !isLsqHead
494}
495
496object EnqEntry {
497  def apply(implicit p: Parameters, iqParams: IssueBlockParams): EnqEntry = {
498    iqParams.schdType match {
499      case IntScheduler() => new EnqEntry()
500      case MemScheduler() =>
501        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new EnqEntryMem()
502        else if (iqParams.isVecMemAddrIQ) new EnqEntryVecMemAddr()
503        else if (iqParams.isVecStDataIQ) new EnqEntryVecMemData()
504        else new EnqEntry()
505      case VfScheduler() => new EnqEntry()
506      case _ => null
507    }
508  }
509}