xref: /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala (revision af4bd265b9ee15d3efcb7178c3403e5c1714a573) 
1package xiangshan.backend.issue
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import utility.HasCircularQueuePtrHelper
7import utils.{MathUtils, OptionWrapper}
8import xiangshan._
9import xiangshan.backend.Bundles._
10import xiangshan.backend.fu.FuType
11import xiangshan.backend.datapath.DataSource
12import xiangshan.backend.rob.RobPtr
13import xiangshan.mem.{MemWaitUpdateReq, SqPtr, LqPtr}
14
15
16class EnqEntryIO(implicit p: Parameters, params: IssueBlockParams) extends XSBundle {
17  //input
18  val enq = Flipped(ValidIO(new EntryBundle))
19  val flush = Flipped(ValidIO(new Redirect))
20  val wakeUpFromWB: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = Flipped(params.genWBWakeUpSinkValidBundle)
21  val wakeUpFromIQ: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(params.genIQWakeUpSinkValidBundle)
22  val og0Cancel = Input(ExuOH(backendParams.numExu))
23  val og1Cancel = Input(ExuOH(backendParams.numExu))
24  val ldCancel = Vec(backendParams.LduCnt + backendParams.HyuCnt, Flipped(new LoadCancelIO))
25  val deqSel = Input(Bool())
26  val deqPortIdxWrite = Input(UInt(1.W))
27  val transSel = Input(Bool())
28  val issueResp = Flipped(ValidIO(new EntryDeqRespBundle))
29  //output
30  val valid = Output(Bool())
31  val canIssue = Output(Bool())
32  val clear = Output(Bool())
33  val fuType = Output(FuType())
34  val dataSource = Output(Vec(params.numRegSrc, DataSource()))
35  val srcWakeUpL1ExuOH = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, ExuOH())))
36  val srcTimer = OptionWrapper(params.hasIQWakeUp, Output(Vec(params.numRegSrc, UInt(3.W))))
37  val transEntry =  ValidIO(new EntryBundle)
38  val isFirstIssue = Output(Bool())
39  val entry = ValidIO(new EntryBundle)
40  val robIdx = Output(new RobPtr)
41  val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx()))
42  val deqPortIdxRead = Output(UInt(1.W))
43  val issueTimerRead = Output(UInt(2.W))
44  // mem only
45  val fromMem = if(params.isMemAddrIQ) Some(new Bundle {
46    val stIssuePtr = Input(new SqPtr)
47    val memWaitUpdateReq = Flipped(new MemWaitUpdateReq)
48  }) else None
49  // vector mem only
50  val fromLsq = OptionWrapper(params.isVecMemIQ, new Bundle {
51    val sqDeqPtr = Input(new SqPtr)
52    val lqDeqPtr = Input(new LqPtr)
53  })
54  // debug
55  val cancel = OptionWrapper(params.hasIQWakeUp, Output(Bool()))
56
57  def wakeup = wakeUpFromWB ++ wakeUpFromIQ
58}
59
60class EnqEntry(implicit p: Parameters, params: IssueBlockParams) extends XSModule {
61  val io = IO(new EnqEntryIO)
62
63  val validReg = RegInit(false.B)
64  val entryReg = Reg(new EntryBundle)
65
66  val validRegNext = Wire(Bool())
67  val entryRegNext = Wire(new EntryBundle)
68  val entryUpdate = Wire(new EntryBundle)
69  val enqReady = Wire(Bool())
70  val clear = Wire(Bool())
71  val flushed = Wire(Bool())
72  val deqSuccess = Wire(Bool())
73  val srcWakeUp = Wire(Vec(params.numRegSrc, Bool()))
74  val srcWakeUpByWB = Wire(Vec(params.numRegSrc, Bool()))
75  val srcCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
76  val srcLoadCancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
77  val srcWakeUpByIQVec = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
78  val srcWakeUpByIQWithoutCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
79  val srcWakeUpButCancel = Wire(Vec(params.numRegSrc, Vec(params.numWakeupFromIQ, Bool())))
80  val srcWakeUpL1ExuOHOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, ExuOH())))
81  val srcLoadDependencyOut = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Vec(LoadPipelineWidth, UInt(3.W)))))
82  val wakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
83  val shiftedWakeupLoadDependencyByIQVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
84  val shiftedWakeupLoadDependencyByIQBypassVec = Wire(Vec(params.numWakeupFromIQ, Vec(LoadPipelineWidth, UInt(3.W))))
85  val cancelVec = OptionWrapper(params.hasIQWakeUp, Wire(Vec(params.numRegSrc, Bool())))
86
87  //Reg
88  validReg := validRegNext
89  entryReg := entryRegNext
90
91  //Wire
92  when(io.enq.valid && enqReady) {
93    validRegNext := true.B
94  }.elsewhen(clear) {
95    validRegNext := false.B
96  }.otherwise {
97    validRegNext := validReg
98  }
99
100  when(io.enq.valid && enqReady) {
101    entryRegNext := io.enq.bits
102  }.otherwise {
103    entryRegNext := entryUpdate
104  }
105
106  enqReady := !validReg || clear
107  clear := flushed || io.transSel || deqSuccess
108  flushed := entryReg.status.robIdx.needFlush(io.flush)
109  deqSuccess := io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.fuIdle && !srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B)
110  srcWakeUpByWB := io.wakeUpFromWB.map(bundle => bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)).transpose.map(x => VecInit(x.toSeq).asUInt.orR).toSeq
111  srcWakeUp := srcWakeUpByWB.zip(srcWakeUpByIQVec).map { case (x, y) => x || y.asUInt.orR }
112
113  shiftedWakeupLoadDependencyByIQVec
114    .zip(wakeupLoadDependencyByIQVec)
115    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
116    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
117      case ((dep, originalDep), deqPortIdx) =>
118        if (params.backendParam.getLdExuIdx(params.backendParam.allExuParams.find(_.name == name).get) == deqPortIdx)
119          dep := (originalDep << 2).asUInt | 2.U
120        else
121          dep := originalDep << 1
122    }
123  }
124  shiftedWakeupLoadDependencyByIQBypassVec
125    .zip(wakeupLoadDependencyByIQVec)
126    .zip(params.wakeUpInExuSources.map(_.name)).foreach {
127    case ((deps, originalDeps), name) => deps.zip(originalDeps).zipWithIndex.foreach {
128      case ((dep, originalDep), deqPortIdx) =>
129        if (name.contains("LDU") && name.replace("LDU", "").toInt == deqPortIdx)
130          dep := (originalDep << 1).asUInt | 1.U
131        else
132          dep := originalDep
133    }
134  }
135
136  if (params.hasIQWakeUp) {
137    srcCancelVec.get.zip(srcLoadCancelVec.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach { case (((srcCancel, srcLoadCancel), wakeUpByIQVec), srcIdx) =>
138      val ldTransCancel = Mux(
139        wakeUpByIQVec.asUInt.orR,
140        Mux1H(wakeUpByIQVec, wakeupLoadDependencyByIQVec.map(dep => LoadShouldCancel(Some(dep), io.ldCancel))),
141        false.B
142      )
143      srcLoadCancel := LoadShouldCancel(entryReg.status.srcLoadDependency.map(_(srcIdx)), io.ldCancel)
144      srcCancel := srcLoadCancel || ldTransCancel
145    }
146  }
147
148  if (io.wakeUpFromIQ.isEmpty) {
149    srcWakeUpByIQVec := 0.U.asTypeOf(srcWakeUpByIQVec)
150    wakeupLoadDependencyByIQVec := 0.U.asTypeOf(wakeupLoadDependencyByIQVec)
151  } else {
152    val wakeupVec: IndexedSeq[IndexedSeq[Bool]] = io.wakeUpFromIQ.map((bundle: ValidIO[IssueQueueIQWakeUpBundle]) =>
153      bundle.bits.wakeUp(entryReg.status.psrc zip entryReg.status.srcType, bundle.valid)
154    ).toIndexedSeq.transpose
155    val cancelSel = io.wakeUpFromIQ.map(x => x.bits.exuIdx).map(x => io.og0Cancel(x))
156    srcWakeUpByIQVec := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && !cancel }))
157    srcWakeUpButCancel := wakeupVec.map(x => VecInit(x.zip(cancelSel).map { case (wakeup, cancel) => wakeup && cancel }))
158    srcWakeUpByIQWithoutCancel := wakeupVec.map(x => VecInit(x))
159    wakeupLoadDependencyByIQVec := io.wakeUpFromIQ.map(_.bits.loadDependency).toSeq
160  }
161
162  //entryUpdate
163  entryUpdate.status.srcState.zip(entryReg.status.srcState).zip(srcWakeUp).zipWithIndex.foreach { case (((stateNext, state), wakeup), srcIdx) =>
164    val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
165    stateNext := Mux(cancel, false.B, wakeup | state)
166    if (params.hasIQWakeUp) {
167      cancelVec.get(srcIdx) := cancel
168    }
169  }
170  entryUpdate.status.dataSources.zip(entryReg.status.dataSources).zip(srcWakeUpByIQVec).foreach {
171    case ((dataSourceNext: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]) =>
172      when(wakeUpByIQOH.asUInt.orR) {
173        dataSourceNext.value := DataSource.bypass
174      }.otherwise {
175        dataSourceNext.value := DataSource.reg
176      }
177  }
178  if (params.hasIQWakeUp) {
179    entryUpdate.status.srcWakeUpL1ExuOH.get.zip(srcWakeUpByIQVec).zip(srcWakeUp).zipWithIndex.foreach {
180      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
181        when(wakeUpByIQOH.asUInt.orR) {
182          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.toSeq.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)))
183        }.elsewhen(wakeUp) {
184          exuOH := 0.U.asTypeOf(exuOH)
185        }.otherwise {
186          exuOH := entryReg.status.srcWakeUpL1ExuOH.get(srcIdx)
187        }
188    }
189    srcWakeUpL1ExuOHOut.get.zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).zipWithIndex.foreach {
190      case (((exuOH: UInt, wakeUpByIQOH: Vec[Bool]), wakeUp: Bool), srcIdx) =>
191        when(wakeUpByIQOH.asUInt.orR) {
192          exuOH := Mux1H(wakeUpByIQOH, io.wakeUpFromIQ.map(x => MathUtils.IntToOH(x.bits.exuIdx).U(backendParams.numExu.W)).toSeq)
193        }.elsewhen(wakeUp) {
194          exuOH := 0.U.asTypeOf(exuOH)
195        }.otherwise {
196          exuOH := entryReg.status.srcWakeUpL1ExuOH.get(srcIdx)
197        }
198    }
199    entryUpdate.status.srcTimer.get.zip(entryReg.status.srcTimer.get).zip(srcWakeUpByIQVec).zipWithIndex.foreach {
200      case (((srcIssuedTimerNext, srcIssuedTimer), wakeUpByIQOH: Vec[Bool]), srcIdx) =>
201        srcIssuedTimerNext := MuxCase(3.U, Seq(
202          // T0: waked up by IQ, T1: reset timer as 1
203          wakeUpByIQOH.asUInt.orR -> 2.U,
204          // do not overflow
205          srcIssuedTimer.andR -> srcIssuedTimer,
206          // T2+: increase if the entry is valid, the src is ready, and the src is woken up by iq
207          (validReg && SrcState.isReady(entryReg.status.srcState(srcIdx)) && entryReg.status.srcWakeUpL1ExuOH.get.asUInt.orR) -> (srcIssuedTimer + 1.U)
208        ))
209    }
210    entryUpdate.status.srcLoadDependency.get.zip(entryReg.status.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
211      case (((loadDependencyNext, loadDependency), wakeUpByIQVec), wakeup) =>
212        loadDependencyNext :=
213          Mux(wakeup,
214            Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQVec), 0.U.asTypeOf(loadDependency)),
215            Mux(validReg && loadDependency.asUInt.orR, VecInit(loadDependency.map(i => i(i.getWidth - 2, 0) << 1)), loadDependency)
216          )
217    }
218    srcLoadDependencyOut.get.zip(entryReg.status.srcLoadDependency.get).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
219      case (((loadDependencyOut, loadDependency), wakeUpByIQVec), wakeup) =>
220        loadDependencyOut :=
221          Mux(wakeup,
222            Mux(wakeUpByIQVec.asUInt.orR, Mux1H(wakeUpByIQVec, shiftedWakeupLoadDependencyByIQBypassVec), 0.U.asTypeOf(loadDependency)),
223            loadDependency
224          )
225    }
226  }
227  entryUpdate.status.issueTimer := "b10".U //otherwise
228  entryUpdate.status.deqPortIdx := 0.U //otherwise
229  when(io.deqSel) {
230    entryUpdate.status.issueTimer := 0.U
231    entryUpdate.status.deqPortIdx := io.deqPortIdxWrite
232  }.elsewhen(entryReg.status.issued){
233    entryUpdate.status.issueTimer := entryReg.status.issueTimer + 1.U
234    entryUpdate.status.deqPortIdx := entryReg.status.deqPortIdx
235  }
236  entryUpdate.status.psrc := entryReg.status.psrc
237  entryUpdate.status.srcType := entryReg.status.srcType
238  entryUpdate.status.fuType := entryReg.status.fuType
239  entryUpdate.status.robIdx := entryReg.status.robIdx
240  entryUpdate.status.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
241  entryUpdate.status.issued := entryReg.status.issued // otherwise
242  when(srcLoadCancelVec.map(_.reduce(_ || _)).getOrElse(false.B) || srcWakeUpButCancel.map(_.fold(false.B)(_ || _)).fold(false.B)(_ || _)) {
243    entryUpdate.status.issued := false.B
244  }.elsewhen(io.deqSel) {
245    entryUpdate.status.issued := true.B
246  }.elsewhen(io.issueResp.valid && RSFeedbackType.isBlocked(io.issueResp.bits.respType)) {
247    entryUpdate.status.issued := false.B
248  }.elsewhen(!entryReg.status.srcReady) {
249    entryUpdate.status.issued := false.B
250  }
251  entryUpdate.status.firstIssue := io.deqSel || entryReg.status.firstIssue
252  entryUpdate.status.blocked := false.B //todo
253  //remain imm and payload
254  entryUpdate.imm := entryReg.imm
255  entryUpdate.payload := entryReg.payload
256  if(params.needPc) {
257    entryUpdate.status.pc.get := entryReg.status.pc.get
258  }
259  val canIssue = entryReg.status.canIssue && validReg && !srcCancelVec.getOrElse(false.B).asUInt.orR
260  val canIssueBypass = validReg && !entryReg.status.issued && !entryReg.status.blocked &&
261    VecInit(entryReg.status.srcState.zip(srcWakeUpByIQWithoutCancel).zipWithIndex.map { case ((state, wakeupVec), srcIdx) =>
262      val cancel = srcCancelVec.map(_ (srcIdx)).getOrElse(false.B)
263      Mux(cancel, false.B, wakeupVec.asUInt.orR | state)
264    }).asUInt.andR
265  io.dataSource.zip(entryReg.status.dataSources).zip(srcWakeUpByIQVec).zip(srcWakeUp).foreach {
266    case (((dataSourceOut: DataSource, dataSource: DataSource), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
267      when(wakeUpByIQOH.asUInt.orR) {
268        dataSourceOut.value := DataSource.forward
269      }.elsewhen(wakeUpAll) {
270        dataSourceOut.value := DataSource.reg
271      }.otherwise {
272        dataSourceOut.value := dataSource.value
273      }
274  }
275  if (params.hasIQWakeUp) {
276    io.srcTimer.get.zip(entryReg.status.srcTimer.get).zip(srcWakeUpByIQWithoutCancel).zip(srcWakeUp).foreach {
277      case (((srcTimerOut, srcTimer), wakeUpByIQOH: Vec[Bool]), wakeUpAll) =>
278        when(wakeUpByIQOH.asUInt.orR) {
279          srcTimerOut := 1.U
280        }.otherwise {
281          srcTimerOut := srcTimer
282        }
283    }
284  }
285
286  //output
287  io.transEntry.valid := validReg && io.transSel && !flushed && !deqSuccess
288  io.transEntry.bits := entryUpdate
289  io.canIssue := canIssue || canIssueBypass
290  io.clear := clear
291  io.fuType := entryReg.status.fuType
292  io.srcWakeUpL1ExuOH.foreach(_ := Mux(canIssueBypass && !canIssue, srcWakeUpL1ExuOHOut.get, entryReg.status.srcWakeUpL1ExuOH.get))
293  io.valid := validReg
294  io.isFirstIssue := !entryReg.status.firstIssue
295  io.entry.valid := validReg
296  io.entry.bits := entryReg
297  io.entry.bits.status.srcLoadDependency.foreach(_ := Mux(canIssueBypass && !canIssue, srcLoadDependencyOut.get, entryReg.status.srcLoadDependency.get))
298  io.robIdx := entryReg.status.robIdx
299  io.uopIdx.foreach(_ := entryReg.status.uopIdx.get)
300  io.issueTimerRead := entryReg.status.issueTimer
301  io.deqPortIdxRead := entryReg.status.deqPortIdx
302  io.cancel.foreach(_ := cancelVec.get.asUInt.orR)
303}
304
305class EnqEntryMem()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
306  with HasCircularQueuePtrHelper {
307  val fromMem = io.fromMem.get
308
309  val memStatus = entryReg.status.mem.get
310  println("memStatus" + memStatus)
311  val memStatusNext = entryRegNext.status.mem.get
312  val memStatusUpdate = entryUpdate.status.mem.get
313
314  // load cannot be issued before older store, unless meet some condition
315  val blockedByOlderStore = isAfter(memStatusNext.sqIdx, fromMem.stIssuePtr)
316
317  val deqFailedForStdInvalid = io.issueResp.valid && io.issueResp.bits.respType === RSFeedbackType.dataInvalid
318
319  val staWaitedReleased = Cat(
320    fromMem.memWaitUpdateReq.robIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForRobIdx.value)
321  ).orR
322  val stdWaitedReleased = Cat(
323    fromMem.memWaitUpdateReq.sqIdx.map(x => x.valid && x.bits.value === memStatusNext.waitForSqIdx.value)
324  ).orR
325  val olderStaNotViolate = staWaitedReleased && !memStatusNext.strictWait
326  val olderStdReady = stdWaitedReleased && memStatusNext.waitForStd
327  val waitStd = !olderStdReady
328  val waitSta = !olderStaNotViolate
329
330  when (io.enq.valid && enqReady) {
331    memStatusNext.waitForSqIdx := io.enq.bits.status.mem.get.waitForSqIdx
332    // update by lfst at dispatch stage
333    memStatusNext.waitForRobIdx := io.enq.bits.status.mem.get.waitForRobIdx
334    // new load inst don't known if it is blocked by store data ahead of it
335    memStatusNext.waitForStd := false.B
336    // update by ssit at rename stage
337    memStatusNext.strictWait := io.enq.bits.status.mem.get.strictWait
338    memStatusNext.sqIdx := io.enq.bits.status.mem.get.sqIdx
339  }.otherwise {
340    memStatusNext := memStatusUpdate
341  }
342
343  when(deqFailedForStdInvalid) {
344    memStatusUpdate.waitForSqIdx := io.issueResp.bits.dataInvalidSqIdx
345    memStatusUpdate.waitForRobIdx := memStatus.waitForRobIdx
346    memStatusUpdate.waitForStd := true.B
347    memStatusUpdate.strictWait := memStatus.strictWait
348    memStatusUpdate.sqIdx := memStatus.sqIdx
349  }.otherwise {
350    memStatusUpdate := memStatus
351  }
352
353  val shouldBlock = Mux(io.enq.valid && enqReady, io.enq.bits.status.blocked, entryReg.status.blocked)
354  val blockNotReleased = waitStd || waitSta
355  val respBlock = deqFailedForStdInvalid
356  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
357  entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock
358
359}
360
361class EnqEntryVecMemAddr()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntryMem {
362
363  require(params.isVecMemAddrIQ, "EnqEntryVecMemAddr can only be instance of VecMemAddr IQ")
364
365  val vecMemStatus = entryReg.status.vecMem.get
366  val vecMemStatusNext = entryRegNext.status.vecMem.get
367  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
368  val fromLsq = io.fromLsq.get
369
370  when (io.enq.valid && enqReady) {
371    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
372    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
373  }.otherwise {
374    vecMemStatusNext := vecMemStatusUpdate
375  }
376  vecMemStatusUpdate := vecMemStatus
377
378  val isLsqHead = {
379    // if (params.isVecLdAddrIQ)
380      entryRegNext.status.vecMem.get.lqIdx <= fromLsq.lqDeqPtr &&
381    // else
382      entryRegNext.status.vecMem.get.sqIdx <= fromLsq.sqDeqPtr
383  }
384
385  entryRegNext.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
386  entryUpdate.status.blocked := shouldBlock && blockNotReleased && blockedByOlderStore || respBlock || !isLsqHead
387}
388
389class EnqEntryVecMemData()(implicit p: Parameters, params: IssueBlockParams) extends EnqEntry
390  with HasCircularQueuePtrHelper {
391
392  require(params.isVecStDataIQ, "EnqEntryVecMemData can only be instance of VecMemData IQ")
393
394  val vecMemStatus = entryReg.status.vecMem.get
395  val vecMemStatusNext = entryRegNext.status.vecMem.get
396  val vecMemStatusUpdate = entryUpdate.status.vecMem.get
397  val fromLsq = io.fromLsq.get
398
399  when (io.enq.valid && enqReady) {
400    vecMemStatusNext.sqIdx := io.enq.bits.status.vecMem.get.sqIdx
401    vecMemStatusNext.lqIdx := io.enq.bits.status.vecMem.get.lqIdx
402  }.otherwise {
403    vecMemStatusNext := vecMemStatusUpdate
404  }
405  vecMemStatusUpdate := vecMemStatus
406
407  val isLsqHead = entryRegNext.status.vecMem.get.sqIdx.value === fromLsq.sqDeqPtr.value
408
409  entryRegNext.status.blocked := !isLsqHead
410  entryUpdate.status.blocked := !isLsqHead
411}
412
413object EnqEntry {
414  def apply(implicit p: Parameters, iqParams: IssueBlockParams): EnqEntry = {
415    iqParams.schdType match {
416      case IntScheduler() => new EnqEntry()
417      case MemScheduler() =>
418        if (iqParams.isLdAddrIQ || iqParams.isStAddrIQ || iqParams.isHyAddrIQ) new EnqEntryMem()
419        else if (iqParams.isVecMemAddrIQ) new EnqEntryVecMemAddr()
420        else if (iqParams.isVecStDataIQ) new EnqEntryVecMemData()
421        else new EnqEntry()
422      case VfScheduler() => new EnqEntry()
423      case _ => null
424    }
425  }
426}