dispatch - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/dispatch

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
a089663a	06-Jan-2021	Yinan Xu <[email protected]>	indexMapping: optimize logic IndexMapping.scala
994af529	06-Jan-2021	Yinan Xu <[email protected]>	dispatchQueue: add needAlloc to optimize address generation timing /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/scripts/autorun/README.md /XiangShan/scripts/autorun/common/__init__.py /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/test/csrc/axi4.cpp /XiangShan/src/test/csrc/axi4.h /XiangShan/src/test/csrc/common.cpp /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/vsrc/assert.v
1d975383	02-Jan-2021	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into perf-debug /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/debug/cputest.sh /XiangShan/rocket-chip /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala Dispatch.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/assert.cpp /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/compress.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/decode/DecodeUnitDiffTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/vsrc/assert.v
b0afd6c7	29-Dec-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into opt-dpq /XiangShan/rocket-chip /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/Pipeline.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
d736a492	26-Dec-2020	Yinan Xu <[email protected]>	lsq,dpq,roq: fix validCounter width /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
fba022a8	26-Dec-2020	Yinan Xu <[email protected]>	dispatchQueue: wrap data into separate module /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala
2ab2279c	23-Dec-2020	Yinan Xu <[email protected]>	dpq: use reg to keep track of the number of valid entries /XiangShan/.github/workflows/emu.yml /XiangShan/block-inclusivecache-sifive /XiangShan/debug/cputest.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala
c33aed1f	22-Dec-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into opt-redirect /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala
bfb958a3	21-Dec-2020	Yinan Xu <[email protected]>	redirect: add redirect level to optimize redirect generation /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
fe6452fc	21-Dec-2020	Yinan Xu <[email protected]>	roq: wrap data in RoqDataModule /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
4fa135e8	20-Dec-2020	Yinan Xu <[email protected]>	commitType: let AMO be INT type Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/compress.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h
780ade3f	20-Dec-2020	Yinan Xu <[email protected]>	lsq: optimize enqueue logic /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala Dispatch.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
8ba1aec3	19-Dec-2020	Yinan Xu <[email protected]>	roq: optimize enq timing Dispatch.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala
c348ab30	19-Dec-2020	Yinan Xu <[email protected]>	dispatchQueue: change enqNum to RenameWidth /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala
cc449d02	17-Dec-2020	Yinan Xu <[email protected]>	dispatchQueue: use Vec for deqPtr to reduce delay DispatchQueue.scala
0780c9f5	17-Dec-2020	Yinan Xu <[email protected]>	DispatchQueue: use Vec for deqPtr to reduce delay /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/compress.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/xiangshan/backend/decode/DecodeUnitDiffTest.scala
bca39442	13-Dec-2020	YikeZhou <[email protected]>	Merge branch 'master' into decode-alt /XiangShan/block-inclusivecache-sifive /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/xiangshan/backend/decode/DecodeUnitDiffTest.scala
2ea5e87c	13-Dec-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into perf-debug /XiangShan/block-inclusivecache-sifive /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/test/csrc/ram.cpp
458204f2	12-Dec-2020	Yinan Xu <[email protected]>	UIntToMask: force slicing the result to UInt with a certain length /XiangShan/.gitmodules /XiangShan/block-inclusivecache-sifive /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
a7006537	11-Dec-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into perf-debug /XiangShan/.github/workflows/check-usage.sh /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/api-config-chipsalliance /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest /XiangShan/debug/Makefile /XiangShan/debug/cputest.sh /XiangShan/debug/sc_stat.sh /XiangShan/rocket-chip /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala Dispatch.scala Dispatch1.scala Dispatch2Fp.scala Dispatch2Int.scala Dispatch2Ls.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/Classify.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/README.md /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/RoundingUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/LZA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/package.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ORTree.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/device/SimMMIOTest.scala /XiangShan/src/test/scala/device/TLTimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/vsrc/ram.v
a63ad672	11-Dec-2020	YikeZhou <[email protected]>	Merge branch 'master' into decode-alt /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala Dispatch.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/decode/DecodeUnitDiffTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
43913318	11-Dec-2020	Yinan Xu <[email protected]>	dispatch: remove replay logic /XiangShan/Makefile /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala
21732575	03-Dec-2020	Yinan Xu <[email protected]>	replay: send redirect when replay /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala Dispatch.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
6c4c9f29	01-Dec-2020	Yinan Xu <[email protected]>	dispatch1: remove bypass correctness check since it works well Dispatch1.scala
dbb91cb5	01-Dec-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/master' into opt-rename /XiangShan/Makefile /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/test/csrc/emu.cpp
1 2 3 4 5 6 7 8910 >>...17