1package xiangshan.backend.decode 2 3import chisel3._ 4import chisel3.util._ 5 6import freechips.rocketchip.config.Parameters 7import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 8import freechips.rocketchip.rocket.{CSR,Causes} 9import freechips.rocketchip.util.{uintToBitPat,UIntIsOneOf} 10 11import xiangshan._ 12import utils._ 13import xiangshan.backend._ 14import xiangshan.backend.decode.AltInstructions._ 15import xiangshan.backend.fu.fpu.FPUOpType 16import freechips.rocketchip.tile.RocketTile 17 18/** 19 * Abstract trait giving defaults and other relevant values to different Decode constants/ 20 */ 21abstract trait DecodeConstants { 22 def X = BitPat("b?") 23 def N = BitPat("b0") 24 def Y = BitPat("b1") 25 26 def decodeDefault: List[BitPat] = // illegal instruction 27 // src1Type src2Type src3Type fuType fuOpType rfWen 28 // | | | | | | fpWen 29 // | | | | | | | isXSTrap 30 // | | | | | | | | noSpecExec 31 // | | | | | | | | | blockBackward 32 // | | | | | | | | | | flushPipe 33 // | | | | | | | | | | | isRVF 34 // | | | | | | | | | | | | selImm 35 List(SrcType.DC, SrcType.DC, SrcType.DC, FuType.alu, ALUOpType.sll, N, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 36 37 val table: Array[(BitPat, List[BitPat])] 38} 39 40trait DecodeUnitConstants 41{ 42 // abstract out instruction decode magic numbers 43 val RD_MSB = 11 44 val RD_LSB = 7 45 val RS1_MSB = 19 46 val RS1_LSB = 15 47 val RS2_MSB = 24 48 val RS2_LSB = 20 49 val RS3_MSB = 31 50 val RS3_LSB = 27 51} 52 53/** 54 * Decoded control signals 55 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 56 */ 57 58/** 59 * Decode constants for RV64 60 */ 61object X64Decode extends DecodeConstants { 62 val table: Array[(BitPat, List[BitPat])] = Array( 63 LD -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.ld, Y, N, N, N, N, N, N, SelImm.IMM_I), 64 LWU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lwu, Y, N, N, N, N, N, N, SelImm.IMM_I), 65 SD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, N, SelImm.IMM_S), 66 67 SLLI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_I), 68 SRLI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, N, SelImm.IMM_I), 69 SRAI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, N, SelImm.IMM_I), 70 71 ADDIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, N, SelImm.IMM_I), 72 SLLIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, N, SelImm.IMM_I), 73 SRAIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, N, SelImm.IMM_I), 74 SRLIW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, N, SelImm.IMM_I), 75 76 ADDW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, N, SelImm.IMM_X), 77 SUBW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.subw, Y, N, N, N, N, N, N, SelImm.IMM_X), 78 SLLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, N, SelImm.IMM_X), 79 SRAW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, N, SelImm.IMM_X), 80 SRLW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, N, SelImm.IMM_X) 81 ) 82} 83 84/** 85 * Overall Decode constants 86 */ 87object XDecode extends DecodeConstants { 88 val table: Array[(BitPat, List[BitPat])] = Array( 89 LW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lw, Y, N, N, N, N, N, N, SelImm.IMM_I), 90 LH -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lh, Y, N, N, N, N, N, N, SelImm.IMM_I), 91 LHU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lhu, Y, N, N, N, N, N, N, SelImm.IMM_I), 92 LB -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lb, Y, N, N, N, N, N, N, SelImm.IMM_I), 93 LBU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.lbu, Y, N, N, N, N, N, N, SelImm.IMM_I), 94 95 SW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, N, SelImm.IMM_S), 96 SH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sh, N, N, N, N, N, N, N, SelImm.IMM_S), 97 SB -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.stu, LSUOpType.sb, N, N, N, N, N, N, N, SelImm.IMM_S), 98 99 LUI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_U), 100 101 ADDI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_I), 102 ANDI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, N, SelImm.IMM_I), 103 ORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, N, SelImm.IMM_I), 104 XORI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, N, SelImm.IMM_I), 105 SLTI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, N, SelImm.IMM_I), 106 SLTIU -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, N, SelImm.IMM_I), 107 108 SLL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_X), 109 ADD -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_X), 110 SUB -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sub, Y, N, N, N, N, N, N, SelImm.IMM_X), 111 SLT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, N, SelImm.IMM_X), 112 SLTU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, N, SelImm.IMM_X), 113 AND -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, N, SelImm.IMM_X), 114 OR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, N, SelImm.IMM_X), 115 XOR -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, N, SelImm.IMM_X), 116 SRA -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, N, SelImm.IMM_X), 117 SRL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, N, SelImm.IMM_X), 118 119 MUL -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mul, Y, N, N, N, N, N, N, SelImm.IMM_X), 120 MULH -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulh, Y, N, N, N, N, N, N, SelImm.IMM_X), 121 MULHU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulhu, Y, N, N, N, N, N, N, SelImm.IMM_X), 122 MULHSU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulhsu, Y, N, N, N, N, N, N, SelImm.IMM_X), 123 MULW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mul, MDUOpType.mulw, Y, N, N, N, N, N, N, SelImm.IMM_X), 124 125 DIV -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.div, Y, N, N, N, N, N, N, SelImm.IMM_X), 126 DIVU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divu, Y, N, N, N, N, N, N, SelImm.IMM_X), 127 REM -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.rem, Y, N, N, N, N, N, N, SelImm.IMM_X), 128 REMU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remu, Y, N, N, N, N, N, N, SelImm.IMM_X), 129 DIVW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divw, Y, N, N, N, N, N, N, SelImm.IMM_X), 130 DIVUW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.divuw, Y, N, N, N, N, N, N, SelImm.IMM_X), 131 REMW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remw, Y, N, N, N, N, N, N, SelImm.IMM_X), 132 REMUW -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.div, MDUOpType.remuw, Y, N, N, N, N, N, N, SelImm.IMM_X), 133 134 AUIPC -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, N, SelImm.IMM_U), 135 JAL -> List(SrcType.pc , SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jal, Y, N, N, N, N, N, N, SelImm.IMM_UJ), 136 JALR -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.jmp, JumpOpType.jalr, Y, N, N, N, N, N, N, SelImm.IMM_I), 137 BEQ -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.beq, N, N, N, N, N, N, N, SelImm.IMM_SB), 138 BNE -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bne, N, N, N, N, N, N, N, SelImm.IMM_SB), 139 BGE -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bge, N, N, N, N, N, N, N, SelImm.IMM_SB), 140 BGEU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bgeu, N, N, N, N, N, N, N, SelImm.IMM_SB), 141 BLT -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.blt, N, N, N, N, N, N, N, SelImm.IMM_SB), 142 BLTU -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.alu, ALUOpType.bltu, N, N, N, N, N, N, N, SelImm.IMM_SB), 143 144 // I-type, the immediate12 holds the CSR register. 145 CSRRW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wrt, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 146 CSRRS -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.set, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 147 CSRRC -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.clr, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 148 149 CSRRWI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.wrti, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), 150 CSRRSI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.seti, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), 151 CSRRCI -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.clri, Y, N, N, Y, Y, N, N, SelImm.IMM_Z), 152 153 SFENCE_VMA->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.sfence, N, N, N, Y, Y, Y, N, SelImm.IMM_X), 154 ECALL -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 155 SRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 156 MRET -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 157 158 WFI -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, N, SelImm.IMM_X), 159 160 FENCE_I -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.fencei, N, N, N, Y, Y, Y, N, SelImm.IMM_X), 161 FENCE -> List(SrcType.pc, SrcType.imm, SrcType.DC, FuType.fence, FenceOpType.fence, N, N, N, Y, Y, Y, N, SelImm.IMM_X), 162 163 // A-type 164 AMOADD_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoadd_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 165 AMOXOR_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoxor_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 166 AMOSWAP_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoswap_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 167 AMOAND_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoand_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 168 AMOOR_W -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoor_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 169 AMOMIN_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomin_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 170 AMOMINU_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amominu_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 171 AMOMAX_W-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomax_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 172 AMOMAXU_W->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomaxu_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 173 174 AMOADD_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoadd_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 175 AMOXOR_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoxor_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 176 AMOSWAP_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoswap_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 177 AMOAND_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoand_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 178 AMOOR_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amoor_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 179 AMOMIN_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomin_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 180 AMOMINU_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amominu_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 181 AMOMAX_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomax_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 182 AMOMAXU_D->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.amomaxu_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 183 184 LR_W -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.mou, LSUOpType.lr_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 185 LR_D -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.mou, LSUOpType.lr_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 186 SC_W -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.sc_w, Y, N, N, Y, Y, N, N, SelImm.IMM_X), 187 SC_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.mou, LSUOpType.sc_d, Y, N, N, Y, Y, N, N, SelImm.IMM_X) 188 ) 189} 190 191/** 192 * FP Decode constants 193 */ 194object FDecode extends DecodeConstants{ 195 val table: Array[(BitPat, List[BitPat])] = Array( 196 197 FLW -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.flw, N, Y, N, N, N, N, N, SelImm.IMM_I), 198 FLD -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.ldu, LSUOpType.ld, N, Y, N, N, N, N, N, SelImm.IMM_I), 199 FSW -> List(SrcType.reg, SrcType.fp, SrcType.DC, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, N, SelImm.IMM_S), 200 FSD -> List(SrcType.reg, SrcType.fp, SrcType.DC, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, N, SelImm.IMM_S), 201 202 FCLASS_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.fclass, Y, N, N, N, N, N, Y, SelImm.IMM_X), 203 FCLASS_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.fclass, Y, N, N, N, N, N, N, SelImm.IMM_X), 204 205 FMV_D_X -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.fmv_i2f, N, Y, N, N, N, N, N, SelImm.IMM_X), 206 FMV_X_D -> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.fmv_f2i, Y, N, N, N, N, N, N, SelImm.IMM_X), 207 FMV_X_W -> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.fmv_f2i, Y, N, N, N, N, N, N, SelImm.IMM_X), 208 FMV_W_X -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.fmv_i2f, N, Y, N, N, N, N, N, SelImm.IMM_X), 209 210 FSGNJ_S -> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fsgnj, N, Y, N, N, N, N, Y, SelImm.IMM_X), 211 FSGNJ_D -> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmisc, FPUOpType.fsgnj, N, Y, N, N, N, N, N, SelImm.IMM_X), 212 FSGNJX_S-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fsgnjx, N, Y, N, N, N, N, Y, SelImm.IMM_X), 213 FSGNJX_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmisc, FPUOpType.fsgnjx, N, Y, N, N, N, N, N, SelImm.IMM_X), 214 FSGNJN_S-> List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fsgnjn, N, Y, N, N, N, N, Y, SelImm.IMM_X), 215 FSGNJN_D-> List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmisc, FPUOpType.fsgnjn, N, Y, N, N, N, N, N, SelImm.IMM_X), 216 217 // FP to FP 218 FCVT_S_D-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.d2s, N, Y, N, N, N, N, Y, SelImm.IMM_X), 219 FCVT_D_S-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.s2d, N, Y, N, N, N, N, N, SelImm.IMM_X), 220 221 // Int to FP 222 FCVT_S_W-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.w2f, N, Y, N, N, N, N, Y, SelImm.IMM_X), 223 FCVT_S_WU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.wu2f, N, Y, N, N, N, N, Y, SelImm.IMM_X), 224 FCVT_S_L-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.l2f, N, Y, N, N, N, N, Y, SelImm.IMM_X), 225 FCVT_S_LU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.lu2f, N, Y, N, N, N, N, Y, SelImm.IMM_X), 226 227 FCVT_D_W-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.w2f, N, Y, N, N, N, N, N, SelImm.IMM_X), 228 FCVT_D_WU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.wu2f, N, Y, N, N, N, N, N, SelImm.IMM_X), 229 FCVT_D_L-> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.l2f, N, Y, N, N, N, N, N, SelImm.IMM_X), 230 FCVT_D_LU->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.i2f, FPUOpType.lu2f, N, Y, N, N, N, N, N, SelImm.IMM_X), 231 232 // FP to Int 233 FCVT_W_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2w, Y, N, N, N, N, N, Y, SelImm.IMM_X), 234 FCVT_WU_S->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2wu, Y, N, N, N, N, N, Y, SelImm.IMM_X), 235 FCVT_L_S-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2l, Y, N, N, N, N, N, Y, SelImm.IMM_X), 236 FCVT_LU_S->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2lu, Y, N, N, N, N, N, Y, SelImm.IMM_X), 237 238 FCVT_W_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2w, Y, N, N, N, N, N, N, SelImm.IMM_X), 239 FCVT_WU_D->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2wu, Y, N, N, N, N, N, N, SelImm.IMM_X), 240 FCVT_L_D-> List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2l, Y, N, N, N, N, N, N, SelImm.IMM_X), 241 FCVT_LU_D->List(SrcType.fp , SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.f2lu, Y, N, N, N, N, N, N, SelImm.IMM_X), 242 243 // "fp_single" is used for wb_data formatting (and debugging) 244 FEQ_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.feq, Y, N, N, N, N, N, Y, SelImm.IMM_X), 245 FLT_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.flt, Y, N, N, N, N, N, Y, SelImm.IMM_X), 246 FLE_S ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fle, Y, N, N, N, N, N, Y, SelImm.IMM_X), 247 248 FEQ_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.feq, Y, N, N, N, N, N, N, SelImm.IMM_X), 249 FLT_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.flt, Y, N, N, N, N, N, N, SelImm.IMM_X), 250 FLE_D ->List(SrcType.fp , SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fle, Y, N, N, N, N, N, N, SelImm.IMM_X), 251 252 FMIN_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fmin, N, Y, N, N, N, N, Y, SelImm.IMM_X), 253 FMAX_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fmax, N, Y, N, N, N, N, Y, SelImm.IMM_X), 254 FMIN_D ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmisc, FPUOpType.fmin, N, Y, N, N, N, N, N, SelImm.IMM_X), 255 FMAX_D ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmisc, FPUOpType.fmax, N, Y, N, N, N, N, N, SelImm.IMM_X), 256 257 FADD_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FPUOpType.fadd, N, Y, N, N, N, N, Y, SelImm.IMM_X), 258 FSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FPUOpType.fsub, N, Y, N, N, N, N, Y, SelImm.IMM_X), 259 FMUL_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FPUOpType.fmul, N, Y, N, N, N, N, Y, SelImm.IMM_X), 260 FADD_D ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmac, FPUOpType.fadd, N, Y, N, N, N, N, N, SelImm.IMM_X), 261 FSUB_D ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmac, FPUOpType.fsub, N, Y, N, N, N, N, N, SelImm.IMM_X), 262 FMUL_D ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmac, FPUOpType.fmul, N, Y, N, N, N, N, N, SelImm.IMM_X), 263 264 FMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FPUOpType.fmadd, N, Y, N, N, N, N, Y, SelImm.IMM_X), 265 FMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FPUOpType.fmsub, N, Y, N, N, N, N, Y, SelImm.IMM_X), 266 FNMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FPUOpType.fnmadd, N, Y, N, N, N, N, Y, SelImm.IMM_X), 267 FNMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FPUOpType.fnmsub, N, Y, N, N, N, N, Y, SelImm.IMM_X), 268 FMADD_D ->List(SrcType.reg, SrcType.reg, SrcType.fp, FuType.fmac, FPUOpType.fmadd, N, Y, N, N, N, N, N, SelImm.IMM_X), 269 FMSUB_D ->List(SrcType.reg, SrcType.reg, SrcType.fp, FuType.fmac, FPUOpType.fmsub, N, Y, N, N, N, N, N, SelImm.IMM_X), 270 FNMADD_D ->List(SrcType.reg, SrcType.reg, SrcType.fp, FuType.fmac, FPUOpType.fnmadd, N, Y, N, N, N, N, N, SelImm.IMM_X), 271 FNMSUB_D ->List(SrcType.reg, SrcType.reg, SrcType.fp, FuType.fmac, FPUOpType.fnmsub, N, Y, N, N, N, N, N, SelImm.IMM_X) 272 ) 273} 274 275/** 276 * FP Divide SquareRoot Constants 277 */ 278object FDivSqrtDecode extends DecodeConstants { 279 val table: Array[(BitPat, List[BitPat])] = Array( 280 FDIV_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmisc, FPUOpType.fdiv, N, Y, N, N, N, N, Y, SelImm.IMM_X), 281 FDIV_D ->List(SrcType.reg, SrcType.reg, SrcType.DC, FuType.fmisc, FPUOpType.fdiv, N, Y, N, N, N, N, N, SelImm.IMM_X), 282 FSQRT_S ->List(SrcType.fp, SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.fsqrt, N, Y, N, N, N, N, Y, SelImm.IMM_X), 283 FSQRT_D ->List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.fmisc, FPUOpType.fsqrt, N, Y, N, N, N, N, N, SelImm.IMM_X) 284 ) 285} 286 287/** 288 * XiangShan Trap Decode constants 289 */ 290object XSTrapDecode extends DecodeConstants { 291 // calculate as ADDI => addi zero, a0, 0 292 // replace rs '?????' with '01010'(a0) in decode stage 293 def lsrc1 = "b01010".U // $a0 294 val table: Array[(BitPat, List[BitPat])] = Array( 295 TRAP -> List(SrcType.reg, SrcType.imm, SrcType.DC, FuType.alu, ALUOpType.add, Y, N, Y, Y, Y, N, N, SelImm.IMM_I) 296 ) 297} 298 299class RVCExpander extends XSModule { 300 val io = IO(new Bundle { 301 val in = Input(UInt(32.W)) 302 val out = Output(new ExpandedInstruction) 303 val rvc = Output(Bool()) 304 }) 305 306 if (HasCExtension) { 307 io.rvc := io.in(1,0) =/= 3.U 308 io.out := new RVCDecoder(io.in, XLEN).decode 309 } else { 310 io.rvc := false.B 311 io.out := new RVCDecoder(io.in, XLEN).passthrough 312 } 313} 314 315object Imm32Gen { 316 def apply(sel: UInt, inst: UInt) = { 317 val sign = Mux(sel === SelImm.IMM_Z, 0.S, inst(31).asSInt) 318 val b30_20 = Mux(sel === SelImm.IMM_U, inst(30,20).asSInt, sign) 319 val b19_12 = Mux(sel =/= SelImm.IMM_U && sel =/= SelImm.IMM_UJ, sign, inst(19,12).asSInt) 320 val b11 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.S, 321 Mux(sel === SelImm.IMM_UJ, inst(20).asSInt, 322 Mux(sel === SelImm.IMM_SB, inst(7).asSInt, sign))) 323 val b10_5 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.U(1.W), inst(30,25)) 324 val b4_1 = Mux(sel === SelImm.IMM_U, 0.U(1.W), 325 Mux(sel === SelImm.IMM_S || sel === SelImm.IMM_SB, inst(11,8), 326 Mux(sel === SelImm.IMM_Z, inst(19,16), inst(24,21)))) 327 val b0 = Mux(sel === SelImm.IMM_S, inst(7), 328 Mux(sel === SelImm.IMM_I, inst(20), 329 Mux(sel === SelImm.IMM_Z, inst(15), 0.U(1.W)))) 330 331 Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0) 332 } 333} 334 335/** 336 * IO bundle for the Decode unit 337 */ 338class DecodeUnitIO extends XSBundle { 339 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 340 val deq = new Bundle { val cf_ctrl = Output(new CfCtrl) } 341} 342 343/** 344 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 345 */ 346class DecodeUnit extends XSModule with DecodeUnitConstants { 347 val io = IO(new DecodeUnitIO) 348 349 val ctrl_flow = Wire(new CtrlFlow) // input with RVC Expanded 350 val cf_ctrl = Wire(new CfCtrl) 351 352 val exp = Module(new RVCExpander()) 353 exp.io.in := io.enq.ctrl_flow.instr 354 ctrl_flow := io.enq.ctrl_flow 355 when (exp.io.rvc) { 356 ctrl_flow.instr := exp.io.out.bits 357 } 358 359 // save rvc decode info 360 val rvc_info = Wire(new ExpandedInstruction()) 361 val is_rvc = Wire(Bool()) 362 rvc_info := exp.io.out 363 is_rvc := exp.io.rvc 364 365 var decode_table = XDecode.table ++ FDecode.table ++ FDivSqrtDecode.table ++ X64Decode.table ++ XSTrapDecode.table 366 367 // output 368 cf_ctrl.cf := ctrl_flow 369 cf_ctrl.brTag := DontCare 370 val cs = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) 371 372 when (is_rvc) { 373 cs.lsrc1 := rvc_info.rs1 374 cs.lsrc2 := rvc_info.rs2 375 cs.lsrc3 := rvc_info.rs3 376 377 cs.ldest := rvc_info.rd 378 379 } .otherwise { 380 cs.lsrc1 := ctrl_flow.instr(RS1_MSB,RS1_LSB) 381 cs.lsrc2 := ctrl_flow.instr(RS2_MSB,RS2_LSB) 382 cs.lsrc3 := ctrl_flow.instr(RS3_MSB,RS3_LSB) 383 384 cs.ldest := ctrl_flow.instr(RD_MSB,RD_LSB) 385 } 386 387 // fill in exception vector 388 cf_ctrl.cf.exceptionVec.map(_ := false.B) 389 cf_ctrl.cf.exceptionVec(illegalInstr) := cs.imm === SelImm.INVALID_INSTR 390 cf_ctrl.cf.exceptionVec(instrPageFault) := io.enq.ctrl_flow.exceptionVec(instrPageFault) 391 392 // fix frflags 393 // fflags zero csrrs rd csr 394 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 395 when (cs.fuType === FuType.csr && isFrflags) { 396 cs.blockBackward := false.B 397 } 398 399 // fix isXSTrap 400 when (cs.isXSTrap) { 401 cs.lsrc1 := XSTrapDecode.lsrc1 402 } 403 404 cs.imm := SignExt(Imm32Gen(cs.selImm, ctrl_flow.instr), XLEN) 405 406 cf_ctrl.ctrl := cs 407 408 // fix ret and call 409 when (cs.fuType === FuType.jmp) { 410 def isLink(reg: UInt) = (reg === 1.U || reg === 5.U) 411 when (isLink(cs.ldest) && cs.fuOpType === JumpOpType.jal) { cf_ctrl.ctrl.fuOpType := JumpOpType.call } 412 when (cs.fuOpType === JumpOpType.jalr) { 413 when (isLink(cs.lsrc1)) { cf_ctrl.ctrl.fuOpType := JumpOpType.ret } 414 when (isLink(cs.ldest)) { cf_ctrl.ctrl.fuOpType := JumpOpType.call } 415 } 416 } 417 418 io.deq.cf_ctrl := cf_ctrl 419 420 //------------------------------------------------------------- 421 // Debug Info 422 XSDebug("in: instr=%x pc=%x excepVec=%b intrVec=%b crossPageIPFFix=%d\n", 423 io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 424 io.enq.ctrl_flow.intrVec.asUInt, io.enq.ctrl_flow.crossPageIPFFix) 425 XSDebug("out: src1Type=%b src2Type=%b src3Type=%b lsrc1=%d lsrc2=%d lsrc3=%d ldest=%d fuType=%b fuOpType=%b\n", 426 io.deq.cf_ctrl.ctrl.src1Type, io.deq.cf_ctrl.ctrl.src2Type, io.deq.cf_ctrl.ctrl.src3Type, 427 io.deq.cf_ctrl.ctrl.lsrc1, io.deq.cf_ctrl.ctrl.lsrc2, io.deq.cf_ctrl.ctrl.lsrc3, 428 io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 429 XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d isRVF=%d imm=%x\n", 430 io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 431 io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 432 io.deq.cf_ctrl.ctrl.isRVF, io.deq.cf_ctrl.ctrl.imm) 433} 434