1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8 9// Store Pipeline Stage 0 10// Generate addr, use addr to query DCache and DTLB 11class StoreUnit_S0 extends XSModule { 12 val io = IO(new Bundle() { 13 val in = Flipped(Decoupled(new ExuInput)) 14 val out = Decoupled(new LsPipelineBundle) 15 val redirect = Flipped(ValidIO(new Redirect)) 16 val dtlbReq = DecoupledIO(new TlbReq) 17 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 18 val tlbFeedback = ValidIO(new TlbFeedback) 19 }) 20 21 // send req to dtlb 22 val saddr = io.in.bits.src1 + io.in.bits.uop.ctrl.imm 23 24 io.dtlbReq.bits.vaddr := saddr 25 io.dtlbReq.valid := io.in.valid 26 io.dtlbReq.bits.cmd := TlbCmd.write 27 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 28 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 29 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 30 31 io.out.bits := DontCare 32 io.out.bits.vaddr := saddr 33 io.out.bits.paddr := io.dtlbResp.bits.paddr 34 io.out.bits.data := genWdata(io.in.bits.src2, io.in.bits.uop.ctrl.fuOpType(1,0)) 35 io.out.bits.uop := io.in.bits.uop 36 io.out.bits.miss := io.dtlbResp.bits.miss 37 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 38 io.out.valid := io.in.valid && !io.dtlbResp.bits.miss && !io.out.bits.uop.roqIdx.needFlush(io.redirect) 39 io.in.ready := io.out.ready 40 41 // exception check 42 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 43 "b00".U -> true.B, //b 44 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 45 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 46 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 47 )) 48 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 49 io.out.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 50 51 // Send TLB feedback to store issue queue 52 // TODO: should be moved to S1 53 io.tlbFeedback.valid := RegNext(io.in.valid && io.out.ready) 54 io.tlbFeedback.bits.hit := RegNext(!io.out.bits.miss) 55 io.tlbFeedback.bits.roqIdx := RegNext(io.out.bits.uop.roqIdx) 56 XSDebug(io.tlbFeedback.valid, 57 "S1 Store: tlbHit: %d roqIdx: %d\n", 58 io.tlbFeedback.bits.hit, 59 io.tlbFeedback.bits.roqIdx.asUInt 60 ) 61} 62 63// Load Pipeline Stage 1 64// TLB resp (send paddr to dcache) 65class StoreUnit_S1 extends XSModule { 66 val io = IO(new Bundle() { 67 val in = Flipped(Decoupled(new LsPipelineBundle)) 68 val out = Decoupled(new LsPipelineBundle) 69 // val fp_out = Decoupled(new LsPipelineBundle) 70 val stout = DecoupledIO(new ExuOutput) // writeback store 71 val redirect = Flipped(ValidIO(new Redirect)) 72 }) 73 74 // get paddr from dtlb, check if rollback is needed 75 // writeback store inst to lsq 76 // writeback to LSQ 77 io.in.ready := true.B 78 io.out.bits := io.in.bits 79 io.out.bits.miss := false.B 80 io.out.bits.mmio := AddressSpace.isMMIO(io.in.bits.paddr) 81 io.out.valid := io.in.fire() // TODO: && ! FP 82 83 io.stout.bits.uop := io.in.bits.uop 84 // io.stout.bits.uop.cf.exceptionVec := // TODO: update according to TLB result 85 io.stout.bits.data := DontCare 86 io.stout.bits.redirectValid := false.B 87 io.stout.bits.redirect := DontCare 88 io.stout.bits.brUpdate := DontCare 89 io.stout.bits.debug.isMMIO := io.out.bits.mmio 90 io.stout.bits.fflags := DontCare 91 92 val hasException = io.out.bits.uop.cf.exceptionVec.asUInt.orR 93 io.stout.valid := io.in.fire() && (!io.out.bits.mmio || hasException) // mmio inst will be writebacked immediately 94 95 // if fp 96 // io.fp_out.valid := ... 97 // io.fp_out.bits := ... 98 99} 100 101// class StoreUnit_S2 extends XSModule { 102// val io = IO(new Bundle() { 103// val in = Flipped(Decoupled(new LsPipelineBundle)) 104// val out = Decoupled(new LsPipelineBundle) 105// val redirect = Flipped(ValidIO(new Redirect)) 106// }) 107 108// io.in.ready := true.B 109// io.out.bits := io.in.bits 110// io.out.valid := io.in.valid && !io.out.bits.uop.roqIdx.needFlush(io.redirect) 111// } 112 113class StoreUnit extends XSModule { 114 val io = IO(new Bundle() { 115 val stin = Flipped(Decoupled(new ExuInput)) 116 val redirect = Flipped(ValidIO(new Redirect)) 117 val tlbFeedback = ValidIO(new TlbFeedback) 118 val dtlb = new TlbRequestIO() 119 val lsq = ValidIO(new LsPipelineBundle) 120 val stout = DecoupledIO(new ExuOutput) // writeback store 121 }) 122 123 val store_s0 = Module(new StoreUnit_S0) 124 val store_s1 = Module(new StoreUnit_S1) 125 // val store_s2 = Module(new StoreUnit_S2) 126 127 store_s0.io.in <> io.stin 128 store_s0.io.redirect <> io.redirect 129 store_s0.io.dtlbReq <> io.dtlb.req 130 store_s0.io.dtlbResp <> io.dtlb.resp 131 store_s0.io.tlbFeedback <> io.tlbFeedback 132 133 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, false.B) 134 // PipelineConnect(store_s1.io.fp_out, store_s2.io.in, true.B, false.B) 135 136 store_s1.io.redirect <> io.redirect 137 store_s1.io.stout <> io.stout 138 // send result to sq 139 io.lsq.valid := store_s1.io.out.valid 140 io.lsq.bits := store_s1.io.out.bits 141 142 store_s1.io.out.ready := true.B 143 144 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 145 XSDebug(cond, 146 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 147 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 148 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 149 p"data ${Hexadecimal(pipeline.data)} " + 150 p"mask ${Hexadecimal(pipeline.mask)}\n" 151 ) 152 } 153 154 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 155 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 156 157}