1package xiangshan.mem 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.cache._ 8import xiangshan.cache.{DCacheWordIO, DCacheLineIO, TlbRequestIO, MemoryOpConstants} 9import xiangshan.backend.LSUOpType 10import xiangshan.mem._ 11import xiangshan.backend.roq.RoqPtr 12import xiangshan.backend.fu.fpu.boxF32ToF64 13 14 15class LqPtr extends CircularQueuePtr(LqPtr.LoadQueueSize) { } 16 17object LqPtr extends HasXSParameter { 18 def apply(f: Bool, v: UInt): LqPtr = { 19 val ptr = Wire(new LqPtr) 20 ptr.flag := f 21 ptr.value := v 22 ptr 23 } 24} 25 26 27// Load Queue 28class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper { 29 val io = IO(new Bundle() { 30 val enq = new Bundle() { 31 val canAccept = Output(Bool()) 32 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 33 val resp = Vec(RenameWidth, Output(new LqPtr)) 34 } 35 val brqRedirect = Input(Valid(new Redirect)) 36 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 37 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // FIXME: Valid() only 38 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback load 39 val load_s1 = Vec(LoadPipelineWidth, Flipped(new LoadForwardQueryIO)) 40 val commits = Flipped(new RoqCommitIO) 41 val rollback = Output(Valid(new Redirect)) // replay now starts from load instead of store 42 val dcache = new DCacheLineIO 43 val uncache = new DCacheWordIO 44 val roqDeqPtr = Input(new RoqPtr) 45 val exceptionAddr = new ExceptionAddrIO 46 }) 47 48 val uop = Reg(Vec(LoadQueueSize, new MicroOp)) 49 // val data = Reg(Vec(LoadQueueSize, new LsRoqEntry)) 50 val dataModule = Module(new LSQueueData(LoadQueueSize, LoadPipelineWidth)) 51 dataModule.io := DontCare 52 val allocated = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // lq entry has been allocated 53 val datavalid = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // data is valid 54 val writebacked = RegInit(VecInit(List.fill(LoadQueueSize)(false.B))) // inst has been writebacked to CDB 55 val commited = Reg(Vec(LoadQueueSize, Bool())) // inst has been writebacked to CDB 56 val miss = Reg(Vec(LoadQueueSize, Bool())) // load inst missed, waiting for miss queue to accept miss request 57 val listening = Reg(Vec(LoadQueueSize, Bool())) // waiting for refill result 58 val pending = Reg(Vec(LoadQueueSize, Bool())) // mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq 59 60 val enqPtrExt = RegInit(VecInit((0 until RenameWidth).map(_.U.asTypeOf(new LqPtr)))) 61 val deqPtrExt = RegInit(0.U.asTypeOf(new LqPtr)) 62 val enqPtr = enqPtrExt(0).value 63 val deqPtr = deqPtrExt.value 64 val sameFlag = enqPtrExt(0).flag === deqPtrExt.flag 65 val isEmpty = enqPtr === deqPtr && sameFlag 66 val isFull = enqPtr === deqPtr && !sameFlag 67 val allowIn = !isFull 68 69 val loadCommit = (0 until CommitWidth).map(i => io.commits.valid(i) && !io.commits.isWalk && io.commits.uop(i).ctrl.commitType === CommitType.LOAD) 70 val mcommitIdx = (0 until CommitWidth).map(i => io.commits.uop(i).lqIdx.value) 71 72 val deqMask = UIntToMask(deqPtr, LoadQueueSize) 73 val enqMask = UIntToMask(enqPtr, LoadQueueSize) 74 75 /** 76 * Enqueue at dispatch 77 * 78 * Currently, LoadQueue only allows enqueue when #emptyEntries > RenameWidth(EnqWidth) 79 */ 80 val validEntries = distanceBetween(enqPtrExt(0), deqPtrExt) 81 val firedDispatch = io.enq.req.map(_.valid) 82 io.enq.canAccept := validEntries <= (LoadQueueSize - RenameWidth).U 83 XSDebug(p"(ready, valid): ${io.enq.canAccept}, ${Binary(Cat(firedDispatch))}\n") 84 for (i <- 0 until RenameWidth) { 85 val offset = if (i == 0) 0.U else PopCount((0 until i).map(firedDispatch(_))) 86 val lqIdx = enqPtrExt(offset) 87 val index = lqIdx.value 88 when (io.enq.req(i).valid && !io.brqRedirect.valid) { 89 uop(index) := io.enq.req(i).bits 90 allocated(index) := true.B 91 datavalid(index) := false.B 92 writebacked(index) := false.B 93 commited(index) := false.B 94 miss(index) := false.B 95 listening(index) := false.B 96 pending(index) := false.B 97 } 98 io.enq.resp(i) := lqIdx 99 100 XSError(!io.enq.canAccept && io.enq.req(i).valid, "should not valid when not ready\n") 101 } 102 103 // when io.brqRedirect.valid, we don't allow eneuque even though it may fire. 104 when (Cat(firedDispatch).orR && !io.brqRedirect.valid) { 105 val enqNumber = PopCount(firedDispatch) 106 enqPtrExt := VecInit(enqPtrExt.map(_ + enqNumber)) 107 XSInfo("dispatched %d insts to lq\n", enqNumber) 108 } 109 110 /** 111 * Writeback load from load units 112 * 113 * Most load instructions writeback to regfile at the same time. 114 * However, 115 * (1) For an mmio instruction with exceptions, it writes back to ROB immediately. 116 * (2) For an mmio instruction without exceptions, it does not write back. 117 * The mmio instruction will be sent to lower level when it reaches ROB's head. 118 * After uncache response, it will write back through arbiter with loadUnit. 119 * (3) For cache misses, it is marked miss and sent to dcache later. 120 * After cache refills, it will write back through arbiter with loadUnit. 121 */ 122 for (i <- 0 until LoadPipelineWidth) { 123 dataModule.io.wb(i).wen := false.B 124 when(io.loadIn(i).fire()) { 125 when(io.loadIn(i).bits.miss) { 126 XSInfo(io.loadIn(i).valid, "load miss write to lq idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n", 127 io.loadIn(i).bits.uop.lqIdx.asUInt, 128 io.loadIn(i).bits.uop.cf.pc, 129 io.loadIn(i).bits.vaddr, 130 io.loadIn(i).bits.paddr, 131 io.loadIn(i).bits.data, 132 io.loadIn(i).bits.mask, 133 io.loadIn(i).bits.forwardData.asUInt, 134 io.loadIn(i).bits.forwardMask.asUInt, 135 io.loadIn(i).bits.mmio, 136 io.loadIn(i).bits.rollback, 137 io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 138 ) 139 }.otherwise { 140 XSInfo(io.loadIn(i).valid, "load hit write to cbd lqidx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n", 141 io.loadIn(i).bits.uop.lqIdx.asUInt, 142 io.loadIn(i).bits.uop.cf.pc, 143 io.loadIn(i).bits.vaddr, 144 io.loadIn(i).bits.paddr, 145 io.loadIn(i).bits.data, 146 io.loadIn(i).bits.mask, 147 io.loadIn(i).bits.forwardData.asUInt, 148 io.loadIn(i).bits.forwardMask.asUInt, 149 io.loadIn(i).bits.mmio, 150 io.loadIn(i).bits.rollback, 151 io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 152 ) 153 } 154 val loadWbIndex = io.loadIn(i).bits.uop.lqIdx.value 155 datavalid(loadWbIndex) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 156 writebacked(loadWbIndex) := !io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 157 158 val loadWbData = Wire(new LsqEntry) 159 loadWbData.paddr := io.loadIn(i).bits.paddr 160 loadWbData.vaddr := io.loadIn(i).bits.vaddr 161 loadWbData.mask := io.loadIn(i).bits.mask 162 loadWbData.data := io.loadIn(i).bits.data // for mmio / misc / debug 163 loadWbData.mmio := io.loadIn(i).bits.mmio 164 loadWbData.fwdMask := io.loadIn(i).bits.forwardMask 165 loadWbData.fwdData := io.loadIn(i).bits.forwardData 166 loadWbData.exception := io.loadIn(i).bits.uop.cf.exceptionVec.asUInt 167 dataModule.io.wbWrite(i, loadWbIndex, loadWbData) 168 dataModule.io.wb(i).wen := true.B 169 170 val dcacheMissed = io.loadIn(i).bits.miss && !io.loadIn(i).bits.mmio 171 miss(loadWbIndex) := dcacheMissed && !io.loadIn(i).bits.uop.cf.exceptionVec.asUInt.orR 172 listening(loadWbIndex) := dcacheMissed 173 pending(loadWbIndex) := io.loadIn(i).bits.mmio && !io.loadIn(i).bits.uop.cf.exceptionVec.asUInt.orR 174 } 175 } 176 177 /** 178 * Cache miss request 179 * 180 * (1) writeback: miss 181 * (2) send to dcache: listing 182 * (3) dcache response: datavalid 183 * (4) writeback to ROB: writeback 184 */ 185 val inflightReqs = RegInit(VecInit(Seq.fill(cfg.nLoadMissEntries)(0.U.asTypeOf(new InflightBlockInfo)))) 186 val inflightReqFull = inflightReqs.map(req => req.valid).reduce(_&&_) 187 val reqBlockIndex = PriorityEncoder(~VecInit(inflightReqs.map(req => req.valid)).asUInt) 188 189 val missRefillSelVec = VecInit( 190 (0 until LoadQueueSize).map{ i => 191 val inflight = inflightReqs.map(req => req.valid && req.block_addr === get_block_addr(dataModule.io.rdata(i).paddr)).reduce(_||_) 192 allocated(i) && miss(i) && !inflight 193 }) 194 195 val missRefillSel = getFirstOne(missRefillSelVec, deqMask) 196 val missRefillBlockAddr = get_block_addr(dataModule.io.rdata(missRefillSel).paddr) 197 io.dcache.req.valid := missRefillSelVec.asUInt.orR 198 io.dcache.req.bits.cmd := MemoryOpConstants.M_XRD 199 io.dcache.req.bits.addr := missRefillBlockAddr 200 io.dcache.req.bits.data := DontCare 201 io.dcache.req.bits.mask := DontCare 202 203 io.dcache.req.bits.meta.id := DontCare 204 io.dcache.req.bits.meta.vaddr := DontCare // dataModule.io.rdata(missRefillSel).vaddr 205 io.dcache.req.bits.meta.paddr := missRefillBlockAddr 206 io.dcache.req.bits.meta.uop := uop(missRefillSel) 207 io.dcache.req.bits.meta.mmio := false.B // dataModule.io.rdata(missRefillSel).mmio 208 io.dcache.req.bits.meta.tlb_miss := false.B 209 io.dcache.req.bits.meta.mask := DontCare 210 io.dcache.req.bits.meta.replay := false.B 211 212 io.dcache.resp.ready := true.B 213 214 assert(!(dataModule.io.rdata(missRefillSel).mmio && io.dcache.req.valid)) 215 216 when(io.dcache.req.fire()) { 217 miss(missRefillSel) := false.B 218 listening(missRefillSel) := true.B 219 220 // mark this block as inflight 221 inflightReqs(reqBlockIndex).valid := true.B 222 inflightReqs(reqBlockIndex).block_addr := missRefillBlockAddr 223 assert(!inflightReqs(reqBlockIndex).valid) 224 } 225 226 when(io.dcache.resp.fire()) { 227 val inflight = inflightReqs.map(req => req.valid && req.block_addr === get_block_addr(io.dcache.resp.bits.meta.paddr)).reduce(_||_) 228 assert(inflight) 229 for (i <- 0 until cfg.nLoadMissEntries) { 230 when (inflightReqs(i).valid && inflightReqs(i).block_addr === get_block_addr(io.dcache.resp.bits.meta.paddr)) { 231 inflightReqs(i).valid := false.B 232 } 233 } 234 } 235 236 237 when(io.dcache.req.fire()){ 238 XSDebug("miss req: pc:0x%x roqIdx:%d lqIdx:%d (p)addr:0x%x vaddr:0x%x\n", 239 io.dcache.req.bits.meta.uop.cf.pc, io.dcache.req.bits.meta.uop.roqIdx.asUInt, io.dcache.req.bits.meta.uop.lqIdx.asUInt, 240 io.dcache.req.bits.addr, io.dcache.req.bits.meta.vaddr 241 ) 242 } 243 244 when(io.dcache.resp.fire()){ 245 XSDebug("miss resp: pc:0x%x roqIdx:%d lqIdx:%d (p)addr:0x%x data %x\n", 246 io.dcache.resp.bits.meta.uop.cf.pc, io.dcache.resp.bits.meta.uop.roqIdx.asUInt, io.dcache.resp.bits.meta.uop.lqIdx.asUInt, 247 io.dcache.resp.bits.meta.paddr, io.dcache.resp.bits.data 248 ) 249 } 250 251 // Refill 64 bit in a cycle 252 // Refill data comes back from io.dcache.resp 253 dataModule.io.refill.dcache := io.dcache.resp.bits 254 255 (0 until LoadQueueSize).map(i => { 256 val blockMatch = get_block_addr(dataModule.io.rdata(i).paddr) === io.dcache.resp.bits.meta.paddr 257 dataModule.io.refill.wen(i) := false.B 258 when(allocated(i) && listening(i) && blockMatch && io.dcache.resp.fire()) { 259 dataModule.io.refill.wen(i) := true.B 260 datavalid(i) := true.B 261 listening(i) := false.B 262 } 263 }) 264 265 // writeback up to 2 missed load insts to CDB 266 // just randomly pick 2 missed load (data refilled), write them back to cdb 267 val loadWbSelVec = VecInit((0 until LoadQueueSize).map(i => { 268 allocated(i) && datavalid(i) && !writebacked(i) 269 })).asUInt() // use uint instead vec to reduce verilog lines 270 val loadWbSel = Wire(Vec(StorePipelineWidth, UInt(log2Up(LoadQueueSize).W))) 271 val loadWbSelV= Wire(Vec(StorePipelineWidth, Bool())) 272 val lselvec0 = PriorityEncoderOH(loadWbSelVec) 273 val lselvec1 = PriorityEncoderOH(loadWbSelVec & (~lselvec0).asUInt) 274 loadWbSel(0) := OHToUInt(lselvec0) 275 loadWbSelV(0):= lselvec0.orR 276 loadWbSel(1) := OHToUInt(lselvec1) 277 loadWbSelV(1) := lselvec1.orR 278 (0 until StorePipelineWidth).map(i => { 279 // data select 280 val rdata = dataModule.io.rdata(loadWbSel(i)).data 281 val func = uop(loadWbSel(i)).ctrl.fuOpType 282 val raddr = dataModule.io.rdata(loadWbSel(i)).paddr 283 val rdataSel = LookupTree(raddr(2, 0), List( 284 "b000".U -> rdata(63, 0), 285 "b001".U -> rdata(63, 8), 286 "b010".U -> rdata(63, 16), 287 "b011".U -> rdata(63, 24), 288 "b100".U -> rdata(63, 32), 289 "b101".U -> rdata(63, 40), 290 "b110".U -> rdata(63, 48), 291 "b111".U -> rdata(63, 56) 292 )) 293 val rdataPartialLoad = LookupTree(func, List( 294 LSUOpType.lb -> SignExt(rdataSel(7, 0) , XLEN), 295 LSUOpType.lh -> SignExt(rdataSel(15, 0), XLEN), 296 LSUOpType.lw -> SignExt(rdataSel(31, 0), XLEN), 297 LSUOpType.ld -> SignExt(rdataSel(63, 0), XLEN), 298 LSUOpType.lbu -> ZeroExt(rdataSel(7, 0) , XLEN), 299 LSUOpType.lhu -> ZeroExt(rdataSel(15, 0), XLEN), 300 LSUOpType.lwu -> ZeroExt(rdataSel(31, 0), XLEN), 301 LSUOpType.flw -> boxF32ToF64(rdataSel(31, 0)) 302 )) 303 io.ldout(i).bits.uop := uop(loadWbSel(i)) 304 io.ldout(i).bits.uop.cf.exceptionVec := dataModule.io.rdata(loadWbSel(i)).exception.asBools 305 io.ldout(i).bits.uop.lqIdx := loadWbSel(i).asTypeOf(new LqPtr) 306 io.ldout(i).bits.data := rdataPartialLoad 307 io.ldout(i).bits.redirectValid := false.B 308 io.ldout(i).bits.redirect := DontCare 309 io.ldout(i).bits.brUpdate := DontCare 310 io.ldout(i).bits.debug.isMMIO := dataModule.io.rdata(loadWbSel(i)).mmio 311 io.ldout(i).bits.fflags := DontCare 312 io.ldout(i).valid := loadWbSelVec(loadWbSel(i)) && loadWbSelV(i) 313 when(io.ldout(i).fire()) { 314 writebacked(loadWbSel(i)) := true.B 315 XSInfo("load miss write to cbd roqidx %d lqidx %d pc 0x%x paddr %x data %x mmio %x\n", 316 io.ldout(i).bits.uop.roqIdx.asUInt, 317 io.ldout(i).bits.uop.lqIdx.asUInt, 318 io.ldout(i).bits.uop.cf.pc, 319 dataModule.io.rdata(loadWbSel(i)).paddr, 320 dataModule.io.rdata(loadWbSel(i)).data, 321 dataModule.io.rdata(loadWbSel(i)).mmio 322 ) 323 } 324 }) 325 326 /** 327 * Load commits 328 * 329 * When load commited, mark it as !allocated and move deqPtrExt forward. 330 */ 331 (0 until CommitWidth).map(i => { 332 when(loadCommit(i)) { 333 allocated(mcommitIdx(i)) := false.B 334 XSDebug("load commit %d: idx %d %x\n", i.U, mcommitIdx(i), uop(mcommitIdx(i)).cf.pc) 335 } 336 }) 337 deqPtrExt := deqPtrExt + PopCount(loadCommit) 338 339 def getFirstOne(mask: Vec[Bool], startMask: UInt) = { 340 val length = mask.length 341 val highBits = (0 until length).map(i => mask(i) & ~startMask(i)) 342 val highBitsUint = Cat(highBits.reverse) 343 PriorityEncoder(Mux(highBitsUint.orR(), highBitsUint, mask.asUInt)) 344 } 345 346 def getOldestInTwo(valid: Seq[Bool], uop: Seq[MicroOp]) = { 347 assert(valid.length == uop.length) 348 assert(valid.length == 2) 349 Mux(valid(0) && valid(1), 350 Mux(isAfter(uop(0).roqIdx, uop(1).roqIdx), uop(1), uop(0)), 351 Mux(valid(0) && !valid(1), uop(0), uop(1))) 352 } 353 354 def getAfterMask(valid: Seq[Bool], uop: Seq[MicroOp]) = { 355 assert(valid.length == uop.length) 356 val length = valid.length 357 (0 until length).map(i => { 358 (0 until length).map(j => { 359 Mux(valid(i) && valid(j), 360 isAfter(uop(i).roqIdx, uop(j).roqIdx), 361 Mux(!valid(i), true.B, false.B)) 362 }) 363 }) 364 } 365 366 /** 367 * Memory violation detection 368 * 369 * When store writes back, it searches LoadQueue for younger load instructions 370 * with the same load physical address. They loaded wrong data and need re-execution. 371 * 372 * Cycle 0: Store Writeback 373 * Generate match vector for store address with rangeMask(stPtr, enqPtr). 374 * Besides, load instructions in LoadUnit_S1 and S2 are also checked. 375 * Cycle 1: Redirect Generation 376 * There're three possible types of violations. Choose the oldest load. 377 * Set io.redirect according to the detected violation. 378 */ 379 io.load_s1 := DontCare 380 def detectRollback(i: Int) = { 381 val startIndex = io.storeIn(i).bits.uop.lqIdx.value 382 val lqIdxMask = UIntToMask(startIndex, LoadQueueSize) 383 val xorMask = lqIdxMask ^ enqMask 384 val sameFlag = io.storeIn(i).bits.uop.lqIdx.flag === enqPtrExt(0).flag 385 val toEnqPtrMask = Mux(sameFlag, xorMask, ~xorMask) 386 387 // check if load already in lq needs to be rolledback 388 val lqViolationVec = RegNext(VecInit((0 until LoadQueueSize).map(j => { 389 val addrMatch = allocated(j) && 390 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === dataModule.io.rdata(j).paddr(PAddrBits - 1, 3) 391 val entryNeedCheck = toEnqPtrMask(j) && addrMatch && (datavalid(j) || listening(j) || miss(j)) 392 // TODO: update refilled data 393 val violationVec = (0 until 8).map(k => dataModule.io.rdata(j).mask(k) && io.storeIn(i).bits.mask(k)) 394 Cat(violationVec).orR() && entryNeedCheck 395 }))) 396 val lqViolation = lqViolationVec.asUInt().orR() 397 val lqViolationIndex = getFirstOne(lqViolationVec, RegNext(lqIdxMask)) 398 val lqViolationUop = uop(lqViolationIndex) 399 // lqViolationUop.lqIdx.flag := deqMask(lqViolationIndex) ^ deqPtrExt.flag 400 // lqViolationUop.lqIdx.value := lqViolationIndex 401 XSDebug(lqViolation, p"${Binary(Cat(lqViolationVec))}, $startIndex, $lqViolationIndex\n") 402 403 // when l/s writeback to roq together, check if rollback is needed 404 val wbViolationVec = RegNext(VecInit((0 until LoadPipelineWidth).map(j => { 405 io.loadIn(j).valid && 406 isAfter(io.loadIn(j).bits.uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) && 407 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.loadIn(j).bits.paddr(PAddrBits - 1, 3) && 408 (io.storeIn(i).bits.mask & io.loadIn(j).bits.mask).orR 409 }))) 410 val wbViolation = wbViolationVec.asUInt().orR() 411 val wbViolationUop = getOldestInTwo(wbViolationVec, RegNext(VecInit(io.loadIn.map(_.bits.uop)))) 412 XSDebug(wbViolation, p"${Binary(Cat(wbViolationVec))}, $wbViolationUop\n") 413 414 // check if rollback is needed for load in l1 415 val l1ViolationVec = RegNext(VecInit((0 until LoadPipelineWidth).map(j => { 416 io.load_s1(j).valid && // L1 valid 417 isAfter(io.load_s1(j).uop.roqIdx, io.storeIn(i).bits.uop.roqIdx) && 418 io.storeIn(i).bits.paddr(PAddrBits - 1, 3) === io.load_s1(j).paddr(PAddrBits - 1, 3) && 419 (io.storeIn(i).bits.mask & io.load_s1(j).mask).orR 420 }))) 421 val l1Violation = l1ViolationVec.asUInt().orR() 422 val l1ViolationUop = getOldestInTwo(l1ViolationVec, RegNext(VecInit(io.load_s1.map(_.uop)))) 423 XSDebug(l1Violation, p"${Binary(Cat(l1ViolationVec))}, $l1ViolationUop\n") 424 425 val rollbackValidVec = Seq(lqViolation, wbViolation, l1Violation) 426 val rollbackUopVec = Seq(lqViolationUop, wbViolationUop, l1ViolationUop) 427 428 val mask = getAfterMask(rollbackValidVec, rollbackUopVec) 429 val oneAfterZero = mask(1)(0) 430 val rollbackUop = Mux(oneAfterZero && mask(2)(0), 431 rollbackUopVec(0), 432 Mux(!oneAfterZero && mask(2)(1), rollbackUopVec(1), rollbackUopVec(2))) 433 434 XSDebug( 435 l1Violation, 436 "need rollback (l4 load) pc %x roqidx %d target %x\n", 437 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, l1ViolationUop.roqIdx.asUInt 438 ) 439 XSDebug( 440 lqViolation, 441 "need rollback (ld wb before store) pc %x roqidx %d target %x\n", 442 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, lqViolationUop.roqIdx.asUInt 443 ) 444 XSDebug( 445 wbViolation, 446 "need rollback (ld/st wb together) pc %x roqidx %d target %x\n", 447 io.storeIn(i).bits.uop.cf.pc, io.storeIn(i).bits.uop.roqIdx.asUInt, wbViolationUop.roqIdx.asUInt 448 ) 449 450 (RegNext(io.storeIn(i).valid) && Cat(rollbackValidVec).orR, rollbackUop) 451 } 452 453 // rollback check 454 val rollback = Wire(Vec(StorePipelineWidth, Valid(new MicroOp))) 455 for (i <- 0 until StorePipelineWidth) { 456 val detectedRollback = detectRollback(i) 457 rollback(i).valid := detectedRollback._1 458 rollback(i).bits := detectedRollback._2 459 } 460 461 def rollbackSel(a: Valid[MicroOp], b: Valid[MicroOp]): ValidIO[MicroOp] = { 462 Mux( 463 a.valid, 464 Mux( 465 b.valid, 466 Mux(isAfter(a.bits.roqIdx, b.bits.roqIdx), b, a), // a,b both valid, sel oldest 467 a // sel a 468 ), 469 b // sel b 470 ) 471 } 472 473 val rollbackSelected = ParallelOperation(rollback, rollbackSel) 474 val lastCycleRedirect = RegNext(io.brqRedirect) 475 476 // Note that we use roqIdx - 1.U to flush the load instruction itself. 477 // Thus, here if last cycle's roqIdx equals to this cycle's roqIdx, it still triggers the redirect. 478 io.rollback.valid := rollbackSelected.valid && 479 (!lastCycleRedirect.valid || !isAfter(rollbackSelected.bits.roqIdx, lastCycleRedirect.bits.roqIdx)) 480 io.rollback.bits.roqIdx := rollbackSelected.bits.roqIdx - 1.U 481 io.rollback.bits.isReplay := true.B 482 io.rollback.bits.isMisPred := false.B 483 io.rollback.bits.isException := false.B 484 io.rollback.bits.isFlushPipe := false.B 485 io.rollback.bits.pc := DontCare 486 io.rollback.bits.target := rollbackSelected.bits.cf.pc 487 io.rollback.bits.brTag := rollbackSelected.bits.brTag 488 489 when(io.rollback.valid) { 490 XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.pc, io.rollback.bits.roqIdx.asUInt) 491 } 492 493 /** 494 * Memory mapped IO / other uncached operations 495 * 496 */ 497 val commitType = io.commits.uop(0).ctrl.commitType 498 io.uncache.req.valid := pending(deqPtr) && allocated(deqPtr) && 499 commitType === CommitType.LOAD && 500 io.roqDeqPtr === uop(deqPtr).roqIdx && 501 !io.commits.isWalk 502 503 io.uncache.req.bits.cmd := MemoryOpConstants.M_XRD 504 io.uncache.req.bits.addr := dataModule.io.rdata(deqPtr).paddr 505 io.uncache.req.bits.data := dataModule.io.rdata(deqPtr).data 506 io.uncache.req.bits.mask := dataModule.io.rdata(deqPtr).mask 507 508 io.uncache.req.bits.meta.id := DontCare 509 io.uncache.req.bits.meta.vaddr := DontCare 510 io.uncache.req.bits.meta.paddr := dataModule.io.rdata(deqPtr).paddr 511 io.uncache.req.bits.meta.uop := uop(deqPtr) 512 io.uncache.req.bits.meta.mmio := true.B 513 io.uncache.req.bits.meta.tlb_miss := false.B 514 io.uncache.req.bits.meta.mask := dataModule.io.rdata(deqPtr).mask 515 io.uncache.req.bits.meta.replay := false.B 516 517 io.uncache.resp.ready := true.B 518 519 when (io.uncache.req.fire()) { 520 pending(deqPtr) := false.B 521 522 XSDebug("uncache req: pc %x addr %x data %x op %x mask %x\n", 523 uop(deqPtr).cf.pc, 524 io.uncache.req.bits.addr, 525 io.uncache.req.bits.data, 526 io.uncache.req.bits.cmd, 527 io.uncache.req.bits.mask 528 ) 529 } 530 531 dataModule.io.uncache.wen := false.B 532 when(io.uncache.resp.fire()){ 533 datavalid(deqPtr) := true.B 534 dataModule.io.uncacheWrite(deqPtr, io.uncache.resp.bits.data(XLEN-1, 0)) 535 dataModule.io.uncache.wen := true.B 536 537 XSDebug("uncache resp: data %x\n", io.dcache.resp.bits.data) 538 } 539 540 // Read vaddr for mem exception 541 io.exceptionAddr.vaddr := dataModule.io.rdata(io.exceptionAddr.lsIdx.lqIdx.value).vaddr 542 543 // misprediction recovery / exception redirect 544 // invalidate lq term using robIdx 545 val needCancel = Wire(Vec(LoadQueueSize, Bool())) 546 for (i <- 0 until LoadQueueSize) { 547 needCancel(i) := uop(i).roqIdx.needFlush(io.brqRedirect) && allocated(i) && !commited(i) 548 when (needCancel(i)) { 549 allocated(i) := false.B 550 } 551 } 552 // we recover the pointers in the next cycle after redirect 553 val needCancelReg = RegNext(needCancel) 554 when (lastCycleRedirect.valid) { 555 val cancelCount = PopCount(needCancelReg) 556 enqPtrExt := VecInit(enqPtrExt.map(_ - cancelCount)) 557 } 558 559 // debug info 560 XSDebug("enqPtrExt %d:%d deqPtrExt %d:%d\n", enqPtrExt(0).flag, enqPtr, deqPtrExt.flag, deqPtr) 561 562 def PrintFlag(flag: Bool, name: String): Unit = { 563 when(flag) { 564 XSDebug(false, true.B, name) 565 }.otherwise { 566 XSDebug(false, true.B, " ") 567 } 568 } 569 570 for (i <- 0 until LoadQueueSize) { 571 if (i % 4 == 0) XSDebug("") 572 XSDebug(false, true.B, "%x [%x] ", uop(i).cf.pc, dataModule.io.rdata(i).paddr) 573 PrintFlag(allocated(i), "a") 574 PrintFlag(allocated(i) && datavalid(i), "v") 575 PrintFlag(allocated(i) && writebacked(i), "w") 576 PrintFlag(allocated(i) && commited(i), "c") 577 PrintFlag(allocated(i) && miss(i), "m") 578 PrintFlag(allocated(i) && listening(i), "l") 579 PrintFlag(allocated(i) && pending(i), "p") 580 XSDebug(false, true.B, " ") 581 if (i % 4 == 3 || i == LoadQueueSize - 1) XSDebug(false, true.B, "\n") 582 } 583 584} 585