1package xiangshan.backend.rename 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import utils.XSInfo 7 8class RenameBypassInfo extends XSBundle { 9 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 10 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 11 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 12 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 13} 14 15class Rename extends XSModule { 16 val io = IO(new Bundle() { 17 val redirect = Flipped(ValidIO(new Redirect)) 18 val roqCommits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) 19 // from decode buffer 20 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 21 // to dispatch1 22 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 23 val renameBypass = Output(new RenameBypassInfo) 24 }) 25 26 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 27 XSInfo( 28 in.valid && in.ready, 29 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 30 p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " + 31 p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " + 32 p"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} " + 33 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 34 p"old_pdest:${out.bits.old_pdest} " + 35 p"out v:${out.valid} r:${out.ready}\n" 36 ) 37 } 38 39 for((x,y) <- io.in.zip(io.out)){ 40 printRenameInfo(x, y) 41 } 42 43 val fpFreeList, intFreeList = Module(new FreeList).io 44 val fpRat = Module(new RenameTable(float = true)).io 45 val intRat = Module(new RenameTable(float = false)).io 46 47 fpFreeList.redirect := io.redirect 48 intFreeList.redirect := io.redirect 49 50 val flush = io.redirect.valid && (io.redirect.bits.isException || io.redirect.bits.isFlushPipe) // TODO: need check by JiaWei 51 fpRat.flush := flush 52 intRat.flush := flush 53 54 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 55 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 56 } 57 val walkValid = Cat(io.roqCommits.map(_.valid)).orR && io.roqCommits(0).bits.isWalk 58 fpFreeList.walk.valid := walkValid 59 intFreeList.walk.valid := walkValid 60 fpFreeList.walk.bits := PopCount(io.roqCommits.map(c => c.valid && needDestReg(true, c.bits.uop))) 61 intFreeList.walk.bits := PopCount(io.roqCommits.map(c => c.valid && needDestReg(false, c.bits.uop))) 62 63 val uops = Wire(Vec(RenameWidth, new MicroOp)) 64 65 uops.foreach( uop => { 66// uop.brMask := DontCare 67// uop.brTag := DontCare 68 uop.src1State := DontCare 69 uop.src2State := DontCare 70 uop.src3State := DontCare 71 uop.roqIdx := DontCare 72 uop.diffTestDebugLrScValid := DontCare 73 uop.lqIdx := DontCare 74 uop.sqIdx := DontCare 75 }) 76 77 val needFpDest = Wire(Vec(RenameWidth, Bool())) 78 val needIntDest = Wire(Vec(RenameWidth, Bool())) 79 var lastReady = WireInit(io.out(0).ready) 80 // debug assert 81 val outRdy = Cat(io.out.map(_.ready)) 82 assert(outRdy===0.U || outRdy.andR()) 83 for(i <- 0 until RenameWidth) { 84 uops(i).cf := io.in(i).bits.cf 85 uops(i).ctrl := io.in(i).bits.ctrl 86 uops(i).brTag := io.in(i).bits.brTag 87 88 val inValid = io.in(i).valid 89 90 // alloc a new phy reg 91 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 92 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 93 fpFreeList.allocReqs(i) := needFpDest(i) && lastReady 94 intFreeList.allocReqs(i) := needIntDest(i) && lastReady 95 val fpCanAlloc = fpFreeList.canAlloc(i) 96 val intCanAlloc = intFreeList.canAlloc(i) 97 val this_can_alloc = Mux( 98 needIntDest(i), 99 intCanAlloc, 100 Mux( 101 needFpDest(i), 102 fpCanAlloc, 103 true.B 104 ) 105 ) 106 io.in(i).ready := lastReady && this_can_alloc 107 108 // do checkpoints when a branch inst come 109 for(fl <- Seq(fpFreeList, intFreeList)){ 110 fl.cpReqs(i).valid := inValid 111 fl.cpReqs(i).bits := io.in(i).bits.brTag 112 } 113 114 lastReady = io.in(i).ready 115 116 uops(i).pdest := Mux(needIntDest(i), 117 intFreeList.pdests(i), 118 Mux( 119 uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 120 0.U, fpFreeList.pdests(i) 121 ) 122 ) 123 124 io.out(i).valid := io.in(i).fire() 125 io.out(i).bits := uops(i) 126 127 // write rename table 128 def writeRat(fp: Boolean) = { 129 val rat = if(fp) fpRat else intRat 130 val freeList = if(fp) fpFreeList else intFreeList 131 // speculative inst write 132 val specWen = freeList.allocReqs(i) && freeList.canAlloc(i) 133 // walk back write 134 val commitDestValid = io.roqCommits(i).valid && needDestReg(fp, io.roqCommits(i).bits.uop) 135 val walkWen = commitDestValid && io.roqCommits(i).bits.isWalk 136 137 rat.specWritePorts(i).wen := specWen || walkWen 138 rat.specWritePorts(i).addr := Mux(specWen, uops(i).ctrl.ldest, io.roqCommits(i).bits.uop.ctrl.ldest) 139 rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest) 140 141 XSInfo(walkWen, 142 {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}" + 143 p" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n" 144 ) 145 146 rat.archWritePorts(i).wen := commitDestValid && !io.roqCommits(i).bits.isWalk 147 rat.archWritePorts(i).addr := io.roqCommits(i).bits.uop.ctrl.ldest 148 rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest 149 150 XSInfo(rat.archWritePorts(i).wen, 151 {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" + 152 p" pdest:${rat.archWritePorts(i).wdata}\n" 153 ) 154 155 freeList.deallocReqs(i) := rat.archWritePorts(i).wen 156 freeList.deallocPregs(i) := io.roqCommits(i).bits.uop.old_pdest 157 158 } 159 160 writeRat(fp = false) 161 writeRat(fp = true) 162 163 // read rename table 164 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 165 val rat = if(fp) fpRat else intRat 166 val srcCnt = lsrcList.size 167 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 168 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 169 for(k <- 0 until srcCnt+1){ 170 val rportIdx = i * (srcCnt+1) + k 171 if(k != srcCnt){ 172 rat.readPorts(rportIdx).addr := lsrcList(k) 173 psrcVec(k) := rat.readPorts(rportIdx).rdata 174 } else { 175 rat.readPorts(rportIdx).addr := ldest 176 old_pdest := rat.readPorts(rportIdx).rdata 177 } 178 } 179 (psrcVec, old_pdest) 180 } 181 val lsrcList = List(uops(i).ctrl.lsrc1, uops(i).ctrl.lsrc2, uops(i).ctrl.lsrc3) 182 val ldest = uops(i).ctrl.ldest 183 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 184 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 185 uops(i).psrc1 := Mux(uops(i).ctrl.src1Type === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 186 uops(i).psrc2 := Mux(uops(i).ctrl.src2Type === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 187 uops(i).psrc3 := fpPhySrcVec(2) 188 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 189 } 190 191 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 192 // Instead, we determine whether there're some dependences between the valid instructions. 193 for (i <- 1 until RenameWidth) { 194 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 195 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.fp 196 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src1Type === SrcType.reg 197 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc1 198 }).reverse) 199 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 200 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.fp 201 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src2Type === SrcType.reg 202 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc2 203 }).reverse) 204 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 205 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.fp 206 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.src3Type === SrcType.reg 207 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc3 208 }).reverse) 209 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 210 val fpMatch = needFpDest(j) && needFpDest(i) 211 val intMatch = needIntDest(j) && needIntDest(i) 212 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 213 }).reverse) 214 } 215} 216