1package xiangshan 2 3import chisel3._ 4import chisel3.util._ 5import top.Parameters 6import xiangshan.backend._ 7import xiangshan.backend.dispatch.DispatchParameters 8import xiangshan.backend.exu.ExuParameters 9import xiangshan.backend.exu.Exu._ 10import xiangshan.frontend._ 11import xiangshan.mem._ 12import xiangshan.backend.fu.HasExceptionNO 13import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache} 14import chipsalliance.rocketchip.config 15import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet} 16import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4} 17import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams} 18import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters} 19import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver} 20import utils._ 21 22case class XSCoreParameters 23( 24 XLEN: Int = 64, 25 HasMExtension: Boolean = true, 26 HasCExtension: Boolean = true, 27 HasDiv: Boolean = true, 28 HasICache: Boolean = true, 29 HasDCache: Boolean = true, 30 EnableStoreQueue: Boolean = true, 31 AddrBits: Int = 64, 32 VAddrBits: Int = 39, 33 PAddrBits: Int = 40, 34 HasFPU: Boolean = true, 35 FectchWidth: Int = 8, 36 EnableBPU: Boolean = true, 37 EnableBPD: Boolean = true, 38 EnableRAS: Boolean = true, 39 EnableLB: Boolean = true, 40 EnableLoop: Boolean = true, 41 EnableSC: Boolean = false, 42 HistoryLength: Int = 64, 43 BtbSize: Int = 2048, 44 JbtacSize: Int = 1024, 45 JbtacBanks: Int = 8, 46 RasSize: Int = 16, 47 CacheLineSize: Int = 512, 48 UBtbWays: Int = 16, 49 BtbWays: Int = 2, 50 IBufSize: Int = 64, 51 DecodeWidth: Int = 6, 52 RenameWidth: Int = 6, 53 CommitWidth: Int = 6, 54 BrqSize: Int = 32, 55 IssQueSize: Int = 12, 56 NRPhyRegs: Int = 160, 57 NRIntReadPorts: Int = 14, 58 NRIntWritePorts: Int = 8, 59 NRFpReadPorts: Int = 14, 60 NRFpWritePorts: Int = 8, 61 LoadQueueSize: Int = 64, 62 StoreQueueSize: Int = 48, 63 RoqSize: Int = 192, 64 dpParams: DispatchParameters = DispatchParameters( 65 DqEnqWidth = 4, 66 IntDqSize = 128, 67 FpDqSize = 128, 68 LsDqSize = 96, 69 IntDqDeqWidth = 4, 70 FpDqDeqWidth = 4, 71 LsDqDeqWidth = 4 72 ), 73 exuParameters: ExuParameters = ExuParameters( 74 JmpCnt = 1, 75 AluCnt = 4, 76 MulCnt = 0, 77 MduCnt = 2, 78 FmacCnt = 4, 79 FmiscCnt = 2, 80 FmiscDivSqrtCnt = 0, 81 LduCnt = 2, 82 StuCnt = 2 83 ), 84 LoadPipelineWidth: Int = 2, 85 StorePipelineWidth: Int = 2, 86 StoreBufferSize: Int = 16, 87 RefillSize: Int = 512, 88 TlbEntrySize: Int = 32, 89 TlbL2EntrySize: Int = 256, // or 512 90 PtwL1EntrySize: Int = 16, 91 PtwL2EntrySize: Int = 256, 92 NumPerfCounters: Int = 16 93) 94 95trait HasXSParameter { 96 97 val core = Parameters.get.coreParameters 98 val env = Parameters.get.envParameters 99 100 val XLEN = core.XLEN 101 val HasMExtension = core.HasMExtension 102 val HasCExtension = core.HasCExtension 103 val HasDiv = core.HasDiv 104 val HasIcache = core.HasICache 105 val HasDcache = core.HasDCache 106 val EnableStoreQueue = core.EnableStoreQueue 107 val AddrBits = core.AddrBits // AddrBits is used in some cases 108 val VAddrBits = core.VAddrBits // VAddrBits is Virtual Memory addr bits 109 val PAddrBits = core.PAddrBits // PAddrBits is Phyical Memory addr bits 110 val AddrBytes = AddrBits / 8 // unused 111 val DataBits = XLEN 112 val DataBytes = DataBits / 8 113 val HasFPU = core.HasFPU 114 val FetchWidth = core.FectchWidth 115 val PredictWidth = FetchWidth * 2 116 val EnableBPU = core.EnableBPU 117 val EnableBPD = core.EnableBPD // enable backing predictor(like Tage) in BPUStage3 118 val EnableRAS = core.EnableRAS 119 val EnableLB = core.EnableLB 120 val EnableLoop = core.EnableLoop 121 val EnableSC = core.EnableSC 122 val HistoryLength = core.HistoryLength 123 val BtbSize = core.BtbSize 124 // val BtbWays = 4 125 val BtbBanks = PredictWidth 126 // val BtbSets = BtbSize / BtbWays 127 val JbtacSize = core.JbtacSize 128 val JbtacBanks = core.JbtacBanks 129 val RasSize = core.RasSize 130 val CacheLineSize = core.CacheLineSize 131 val CacheLineHalfWord = CacheLineSize / 16 132 val ExtHistoryLength = HistoryLength + 64 133 val UBtbWays = core.UBtbWays 134 val BtbWays = core.BtbWays 135 val IBufSize = core.IBufSize 136 val DecodeWidth = core.DecodeWidth 137 val RenameWidth = core.RenameWidth 138 val CommitWidth = core.CommitWidth 139 val BrqSize = core.BrqSize 140 val IssQueSize = core.IssQueSize 141 val BrTagWidth = log2Up(BrqSize) 142 val NRPhyRegs = core.NRPhyRegs 143 val PhyRegIdxWidth = log2Up(NRPhyRegs) 144 val RoqSize = core.RoqSize 145 val LoadQueueSize = core.LoadQueueSize 146 val StoreQueueSize = core.StoreQueueSize 147 val dpParams = core.dpParams 148 val exuParameters = core.exuParameters 149 val NRIntReadPorts = core.NRIntReadPorts 150 val NRIntWritePorts = core.NRIntWritePorts 151 val NRMemReadPorts = exuParameters.LduCnt + 2*exuParameters.StuCnt 152 val NRFpReadPorts = core.NRFpReadPorts 153 val NRFpWritePorts = core.NRFpWritePorts 154 val LoadPipelineWidth = core.LoadPipelineWidth 155 val StorePipelineWidth = core.StorePipelineWidth 156 val StoreBufferSize = core.StoreBufferSize 157 val RefillSize = core.RefillSize 158 val DTLBWidth = core.LoadPipelineWidth + core.StorePipelineWidth 159 val TlbEntrySize = core.TlbEntrySize 160 val TlbL2EntrySize = core.TlbL2EntrySize 161 val PtwL1EntrySize = core.PtwL1EntrySize 162 val PtwL2EntrySize = core.PtwL2EntrySize 163 val NumPerfCounters = core.NumPerfCounters 164 165 val icacheParameters = ICacheParameters( 166 nMissEntries = 2 167 ) 168 169 val l1plusCacheParameters = L1plusCacheParameters( 170 tagECC = Some("secded"), 171 dataECC = Some("secded"), 172 nMissEntries = 8 173 ) 174 175 val dcacheParameters = DCacheParameters( 176 tagECC = Some("secded"), 177 dataECC = Some("secded"), 178 nMissEntries = 16, 179 nLoadMissEntries = 8, 180 nStoreMissEntries = 8 181 ) 182 183 val LRSCCycles = 100 184 185 186 // cache hierarchy configurations 187 val l1BusDataWidth = 256 188 189 // L2 configurations 190 val L1BusWidth = 256 191 val L2Size = 512 * 1024 // 512KB 192 val L2BlockSize = 64 193 val L2NWays = 8 194 val L2NSets = L2Size / L2BlockSize / L2NWays 195 196 // L3 configurations 197 val L2BusWidth = 256 198 val L3Size = 4 * 1024 * 1024 // 4MB 199 val L3BlockSize = 64 200 val L3NBanks = 4 201 val L3NWays = 8 202 val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays 203 204 // on chip network configurations 205 val L3BusWidth = 256 206} 207 208trait HasXSLog { this: RawModule => 209 implicit val moduleName: String = this.name 210} 211 212abstract class XSModule extends MultiIOModule 213 with HasXSParameter 214 with HasExceptionNO 215 with HasXSLog 216{ 217 def io: Record 218} 219 220//remove this trait after impl module logic 221trait NeedImpl { this: RawModule => 222 override protected def IO[T <: Data](iodef: T): T = { 223 println(s"[Warn]: (${this.name}) please reomve 'NeedImpl' after implement this module") 224 val io = chisel3.experimental.IO(iodef) 225 io <> DontCare 226 io 227 } 228} 229 230abstract class XSBundle extends Bundle 231 with HasXSParameter 232 233case class EnviromentParameters 234( 235 FPGAPlatform: Boolean = true, 236 EnableDebug: Boolean = false 237) 238 239object AddressSpace extends HasXSParameter { 240 // (start, size) 241 // address out of MMIO will be considered as DRAM 242 def mmio = List( 243 (0x00000000L, 0x40000000L), // internal devices, such as CLINT and PLIC 244 (0x40000000L, 0x40000000L) // external devices 245 ) 246 247 def isMMIO(addr: UInt): Bool = mmio.map(range => { 248 require(isPow2(range._2)) 249 val bits = log2Up(range._2) 250 (addr ^ range._1.U)(PAddrBits-1, bits) === 0.U 251 }).reduce(_ || _) 252} 253 254 255 256class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter { 257 258 // outer facing nodes 259 val dcache = LazyModule(new DCache()) 260 val uncache = LazyModule(new Uncache()) 261 val l1pluscache = LazyModule(new L1plusCache()) 262 val ptw = LazyModule(new PTW()) 263 264 lazy val module = new XSCoreImp(this) 265} 266 267class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer) 268 with HasXSParameter 269 with HasExeBlockHelper 270{ 271 val io = IO(new Bundle { 272 val externalInterrupt = new ExternalInterruptIO 273 }) 274 275 println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}") 276 277 // to fast wake up fp, mem rs 278 val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter) 279 val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter) 280 val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter) 281 val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter) 282 283 val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter) 284 val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter) 285 val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter) 286 val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter) 287 288 val frontend = Module(new Frontend) 289 val ctrlBlock = Module(new CtrlBlock) 290 val integerBlock = Module(new IntegerBlock( 291 fastWakeUpIn = fpBlockFastWakeUpInt, 292 slowWakeUpIn = fpBlockSlowWakeUpInt ++ loadExuConfigs, 293 fastFpOut = intBlockFastWakeUpFp, 294 slowFpOut = intBlockSlowWakeUpFp, 295 fastIntOut = intBlockFastWakeUpInt, 296 slowIntOut = intBlockSlowWakeUpInt 297 )) 298 val floatBlock = Module(new FloatBlock( 299 fastWakeUpIn = intBlockFastWakeUpFp, 300 slowWakeUpIn = intBlockSlowWakeUpFp ++ loadExuConfigs, 301 fastFpOut = fpBlockFastWakeUpFp, 302 slowFpOut = fpBlockSlowWakeUpFp, 303 fastIntOut = fpBlockFastWakeUpInt, 304 slowIntOut = fpBlockSlowWakeUpInt 305 )) 306 val memBlock = Module(new MemBlock( 307 fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp, 308 slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp, 309 fastFpOut = Seq(), 310 slowFpOut = loadExuConfigs, 311 fastIntOut = Seq(), 312 slowIntOut = loadExuConfigs 313 )) 314 315 val dcache = outer.dcache.module 316 val uncache = outer.uncache.module 317 val l1pluscache = outer.l1pluscache.module 318 val ptw = outer.ptw.module 319 val icache = Module(new ICache) 320 321 frontend.io.backend <> ctrlBlock.io.frontend 322 frontend.io.icacheResp <> icache.io.resp 323 frontend.io.icacheToTlb <> icache.io.tlb 324 icache.io.req <> frontend.io.icacheReq 325 icache.io.flush <> frontend.io.icacheFlush 326 frontend.io.sfence <> integerBlock.io.fenceio.sfence 327 frontend.io.tlbCsr <> integerBlock.io.csrio.tlb 328 329 icache.io.mem_acquire <> l1pluscache.io.req 330 l1pluscache.io.resp <> icache.io.mem_grant 331 l1pluscache.io.flush := icache.io.l1plusflush 332 icache.io.fencei := integerBlock.io.fenceio.fencei 333 334 ctrlBlock.io.fromIntBlock <> integerBlock.io.toCtrlBlock 335 ctrlBlock.io.fromFpBlock <> floatBlock.io.toCtrlBlock 336 ctrlBlock.io.fromLsBlock <> memBlock.io.toCtrlBlock 337 ctrlBlock.io.toIntBlock <> integerBlock.io.fromCtrlBlock 338 ctrlBlock.io.toFpBlock <> floatBlock.io.fromCtrlBlock 339 ctrlBlock.io.toLsBlock <> memBlock.io.fromCtrlBlock 340 341 integerBlock.io.wakeUpIn.fastUops <> floatBlock.io.wakeUpIntOut.fastUops 342 integerBlock.io.wakeUpIn.fast <> floatBlock.io.wakeUpIntOut.fast 343 integerBlock.io.wakeUpIn.slow <> floatBlock.io.wakeUpIntOut.slow ++ memBlock.io.wakeUpIntOut.slow 344 345 floatBlock.io.wakeUpIn.fastUops <> integerBlock.io.wakeUpFpOut.fastUops 346 floatBlock.io.wakeUpIn.fast <> integerBlock.io.wakeUpFpOut.fast 347 floatBlock.io.wakeUpIn.slow <> integerBlock.io.wakeUpFpOut.slow ++ memBlock.io.wakeUpFpOut.slow 348 349 350 integerBlock.io.wakeUpIntOut.fast.map(_.ready := true.B) 351 integerBlock.io.wakeUpIntOut.slow.map(_.ready := true.B) 352 floatBlock.io.wakeUpFpOut.fast.map(_.ready := true.B) 353 floatBlock.io.wakeUpFpOut.slow.map(_.ready := true.B) 354 355 val wakeUpMem = Seq( 356 integerBlock.io.wakeUpIntOut, 357 integerBlock.io.wakeUpFpOut, 358 floatBlock.io.wakeUpIntOut, 359 floatBlock.io.wakeUpFpOut 360 ) 361 memBlock.io.wakeUpIn.fastUops <> wakeUpMem.flatMap(_.fastUops) 362 memBlock.io.wakeUpIn.fast <> wakeUpMem.flatMap(w => w.fast.map(f => { 363 val raw = WireInit(f) 364 raw 365 })) 366 memBlock.io.wakeUpIn.slow <> wakeUpMem.flatMap(w => w.slow.map(s => { 367 val raw = WireInit(s) 368 raw 369 })) 370 371 integerBlock.io.csrio.fflags <> ctrlBlock.io.roqio.toCSR.fflags 372 integerBlock.io.csrio.dirty_fs <> ctrlBlock.io.roqio.toCSR.dirty_fs 373 integerBlock.io.csrio.exception <> ctrlBlock.io.roqio.exception 374 integerBlock.io.csrio.isInterrupt <> ctrlBlock.io.roqio.isInterrupt 375 integerBlock.io.csrio.trapTarget <> ctrlBlock.io.roqio.toCSR.trapTarget 376 integerBlock.io.csrio.interrupt <> ctrlBlock.io.roqio.toCSR.intrBitSet 377 integerBlock.io.csrio.memExceptionVAddr <> memBlock.io.lsqio.exceptionAddr.vaddr 378 integerBlock.io.csrio.externalInterrupt <> io.externalInterrupt 379 integerBlock.io.csrio.tlb <> memBlock.io.tlbCsr 380 integerBlock.io.fenceio.sfence <> memBlock.io.sfence 381 integerBlock.io.fenceio.sbuffer <> memBlock.io.fenceToSbuffer 382 383 floatBlock.io.frm <> integerBlock.io.csrio.frm 384 385 memBlock.io.lsqio.commits <> ctrlBlock.io.roqio.commits 386 memBlock.io.lsqio.roqDeqPtr <> ctrlBlock.io.roqio.roqDeqPtr 387 memBlock.io.lsqio.exceptionAddr.lsIdx.lqIdx := ctrlBlock.io.roqio.exception.bits.lqIdx 388 memBlock.io.lsqio.exceptionAddr.lsIdx.sqIdx := ctrlBlock.io.roqio.exception.bits.sqIdx 389 memBlock.io.lsqio.exceptionAddr.isStore := CommitType.lsInstIsStore(ctrlBlock.io.roqio.exception.bits.ctrl.commitType) 390 391 ptw.io.tlb(0) <> memBlock.io.ptw 392 ptw.io.tlb(1) <> frontend.io.ptw 393 ptw.io.sfence <> integerBlock.io.fenceio.sfence 394 ptw.io.csr <> integerBlock.io.csrio.tlb 395 396 dcache.io.lsu.load <> memBlock.io.dcache.loadUnitToDcacheVec 397 dcache.io.lsu.lsq <> memBlock.io.dcache.loadMiss 398 dcache.io.lsu.atomics <> memBlock.io.dcache.atomics 399 dcache.io.lsu.store <> memBlock.io.dcache.sbufferToDcache 400 uncache.io.lsq <> memBlock.io.dcache.uncache 401 402 if (!env.FPGAPlatform) { 403 val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W)))) 404 ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug) 405 ExcitingUtils.addSink(debugFpReg, "DEBUG_FP_ARCH_REG", ExcitingUtils.Debug) 406 val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg)) 407 ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug) 408 } 409 410} 411