| #
e703da02 |
| 08-Oct-2023 |
zhanglyGit <[email protected]> |
Backend: WBDataPath and ROB support vlsu(vld res merge and exceptionGen)
|
| #
05cd9e72 |
| 09-Nov-2023 |
Haojin Tang <[email protected]> |
LsqEnqCtrl: `maxAllocate` should consider hyu
|
| #
04c99eca |
| 05-Nov-2023 |
Xuan Hu <[email protected]> |
backend: fix load cancel bundle
|
| #
d7739d95 |
| 30-Oct-2023 |
sfencevma <[email protected]> |
full initialized
|
| #
670870b3 |
| 25-Oct-2023 |
Xuan Hu <[email protected]> |
backend: support hybrid unit
* filter not fake unit when generate bundles
* add fake exu unit
* hybrid unit use one load writeback port and one store writeback port
|
| #
f9f1abd7 |
| 23-Oct-2023 |
Xuan Hu <[email protected]> |
backend: support HybridUnit at Dispatch Stage
|
| #
b133b458 |
| 21-Oct-2023 |
Xuan Hu <[email protected]> |
backend,mem: support HybridUnit
|
| #
a81cda24 |
| 19-Oct-2023 |
sfencevma <[email protected]> |
3ld2st-for-new-backend
|
| #
83ba63b3 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge error
|
| #
b7d9e8d5 |
| 28-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: parameterized generation debug IO and difftest IO
|
| #
d8a24b06 |
| 20-Sep-2023 |
zhanglyGit <[email protected]> |
Backend: refactor jump targetMem in CtrlBlock
|
| #
99bd2aaf |
| 08-Sep-2023 |
Haojin Tang <[email protected]> |
exceptionGen: retiming exception signals
|
| #
7f8f47b4 |
| 04-Sep-2023 |
Xuan Hu <[email protected]> |
backend: fix rebase bugs
|
| #
39c59369 |
| 03-Aug-2023 |
Xuan Hu <[email protected]> |
params,backend: refactor RegFile parameters
|
| #
acb0b98e |
| 21-Jul-2023 |
Xuan Hu <[email protected]> |
params,backend: add more alu and modify the regfile r/w params
|
| #
c34b4b06 |
| 21-Jul-2023 |
Xuan Hu <[email protected]> |
backend: add regfile r/w port print
|
| #
c0be7f33 |
| 19-Jul-2023 |
Xuan Hu <[email protected]> |
backend,iq: split wake up bundles, add cancel bundle
* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
*
backend,iq: split wake up bundles, add cancel bundle
* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
* Add srcTimer in StatusArray to record the cycles src has been waked up
* Add dataSources in StatusArray to record the source of src data (reg, forward, bypass or none)
* Remove useless ready field in StatusArray
show more ...
|
| #
cdac04a3 |
| 19-Jun-2023 |
Xuan Hu <[email protected]> |
iq: add wakeup exu indices in deq bundle
* one-hot encoded exu indices are would be used in datapath to select bypassed exu data
|
| #
bf35baad |
| 19-Jul-2023 |
Xuan Hu <[email protected]> |
backend: add iq wake up
|
| #
4e9757cc |
| 11-Jun-2023 |
fdy <[email protected]> |
BackendParams: Add configuration checks for BackendParams
|
| #
8d29ec32 |
| 04-May-2023 |
czw <[email protected]> |
func(wbFuBusyTable): add wbFuBusyTable
|
| #
4ee69032 |
| 24-May-2023 |
zhanglyGit <[email protected]> |
VldIssue: backend support Vld issue
|
| #
d6f9198f |
| 21-May-2023 |
Xuan Hu <[email protected]> |
rat: add separated ldest read port for vector insts
|
| #
e2e5f6b0 |
| 17-May-2023 |
Xuan Hu <[email protected]> |
backend: update VfRD to avoid conflict with vconfig read port
|
| #
98639abb |
| 22-May-2023 |
Xuan Hu <[email protected]> |
backend: refactor src configs
* calculate number of source reg instead of using immediate number
|