1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.DebugOptionsKey 31 32import scala.reflect.{ClassTag, classTag} 33 34case class BackendParams( 35 schdParams : Map[SchedulerType, SchdBlockParams], 36 pregParams : Seq[PregParams], 37 iqWakeUpParams : Seq[WakeUpConfig], 38) { 39 40 configChecks 41 42 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 43 def intSchdParams = schdParams.get(IntScheduler()) 44 def vfSchdParams = schdParams.get(VfScheduler()) 45 def memSchdParams = schdParams.get(MemScheduler()) 46 def allSchdParams: Seq[SchdBlockParams] = 47 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 48 .filter(_.nonEmpty) 49 .map(_.get) 50 def allIssueParams: Seq[IssueBlockParams] = 51 allSchdParams.map(_.issueBlockParams).flatten 52 def allExuParams: Seq[ExeUnitParams] = 53 allIssueParams.map(_.exuBlockParams).flatten 54 55 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 56 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 57 def getPregParams: Map[DataConfig, PregParams] = { 58 pregParams.map(x => (x.dataCfg, x)).toMap 59 } 60 61 def pregIdxWidth = pregParams.map(_.addrWidth).max 62 63 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 64 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 65 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 66 67 68 def AluCnt = allSchdParams.map(_.AluCnt).sum 69 def StaCnt = allSchdParams.map(_.StaCnt).sum 70 def StdCnt = allSchdParams.map(_.StdCnt).sum 71 def LduCnt = allSchdParams.map(_.LduCnt).sum 72 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 73 def LsExuCnt = StaCnt + LduCnt 74 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 75 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 76 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 77 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 78 79 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 80 def numTargetReadPort = allExuParams.count(x => x.needTarget) 81 82 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 83 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 84 85 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 86 def numExu = allSchdParams.map(_.numExu).sum 87 def vconfigPort = 0 // Todo: remove it 88 89 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 90 91 def numRedirect = allSchdParams.map(_.numRedirect).sum 92 93 def genIntWriteBackBundle(implicit p: Parameters) = { 94 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 95 } 96 97 def genVfWriteBackBundle(implicit p: Parameters) = { 98 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 99 } 100 101 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 102 genIntWriteBackBundle ++ genVfWriteBackBundle 103 } 104 105 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 106 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 107 } 108 109 def getIntWbArbiterParams: WbArbiterParams = { 110 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 111 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 112 } 113 114 def getVfWbArbiterParams: WbArbiterParams = { 115 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 116 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 117 } 118 119 /** 120 * Get regfile read port params 121 * 122 * @param dataCfg [[IntData]] or [[VecData]] 123 * @return Seq[port->Seq[(exuIdx, priority)] 124 */ 125 def getRdPortParams(dataCfg: DataConfig) = { 126 // port -> Seq[exuIdx, priority] 127 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 128 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 129 .filter { x => x._1.getDataConfig == dataCfg } 130 .map(x => (x._1.port, (x._2, x._1.priority))) 131 .groupBy(_._1) 132 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 133 .toSeq 134 .sortBy(_._1) 135 cfgs 136 } 137 138 /** 139 * Get regfile write back port params 140 * 141 * @param dataCfg [[IntData]] or [[VecData]] 142 * @return Seq[port->Seq[(exuIdx, priority)] 143 */ 144 def getWbPortParams(dataCfg: DataConfig) = { 145 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 146 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 147 .filter { x => x._1.dataCfg == dataCfg } 148 .map(x => (x._1.port, (x._2, x._1.priority))) 149 .groupBy(_._1) 150 .map(x => (x._1, x._2.map(_._2))) 151 .toSeq 152 .sortBy(_._1) 153 cfgs 154 } 155 156 def getRdPortIndices(dataCfg: DataConfig) = { 157 this.getRdPortParams(dataCfg).map(_._1) 158 } 159 160 def getWbPortIndices(dataCfg: DataConfig) = { 161 this.getWbPortParams(dataCfg).map(_._1) 162 } 163 164 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 165 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 166 _.exuBlockParams.map( 167 _.rfrPortConfigs.map( 168 _.collectFirst{ case x: T => x } 169 .getOrElse(NoRD()) 170 ) 171 ) 172 ) 173 rdCfgs 174 } 175 176 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 177 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 178 } 179 180 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 181 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 182 wbCfgs 183 } 184 185 /** 186 * Get size of read ports of int regfile 187 * 188 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 189 */ 190 def getIntRfReadSize = { 191 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 192 } 193 194 /** 195 * Get size of write ports of vf regfile 196 * 197 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 198 */ 199 def getIntRfWriteSize = { 200 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 201 } 202 203 /** 204 * Get size of read ports of int regfile 205 * 206 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 207 */ 208 def getVfRfReadSize = { 209 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 210 } 211 212 /** 213 * Get size of write ports of vf regfile 214 * 215 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 216 */ 217 def getVfRfWriteSize = { 218 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 219 } 220 221 def getRfReadSize(dataCfg: DataConfig) = { 222 this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 223 } 224 225 def getRfWriteSize(dataCfg: DataConfig) = { 226 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 227 } 228 229 def getExuIdx(name: String): Int = { 230 val exuParams = allExuParams 231 if (name != "WB") { 232 val foundExu = exuParams.find(_.name == name) 233 require(foundExu.nonEmpty, s"exu $name not find") 234 foundExu.get.exuIdx 235 } else 236 -1 237 } 238 239 def getExuName(idx: Int): String = { 240 val exuParams = allExuParams 241 exuParams(idx).name 242 } 243 244 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 245 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 246 247 private def isContinuous(portIndices: Seq[Int]): Boolean = { 248 val portIndicesSet = portIndices.toSet 249 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 250 } 251 252 def configChecks = { 253 checkReadPortContinuous 254 checkWritePortContinuous 255 configCheck 256 } 257 258 def checkReadPortContinuous = { 259 pregParams.foreach { x => 260 if (x.numRead.isEmpty) { 261 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 262 require(isContinuous(portIndices), 263 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 264 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 265 } 266 } 267 } 268 269 def checkWritePortContinuous = { 270 pregParams.foreach { x => 271 if (x.numWrite.isEmpty) { 272 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 273 require( 274 isContinuous(portIndices), 275 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 276 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 277 ) 278 } 279 } 280 } 281 282 def configCheck = { 283 // check 0 284 val maxPortSource = 4 285 286 allExuParams.map { 287 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 288 }.filter(_.isDefined).groupBy(_.get.port).foreach { 289 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 290 } 291 allExuParams.map { 292 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 293 }.filter(_.isDefined).groupBy(_.get.port).foreach { 294 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 295 } 296 297 // check 1 298 val wbTypes = Seq(IntWB(), VfWB()) 299 val rdTypes = Seq(IntRD(), VfRD()) 300 for(wbType <- wbTypes){ 301 for(rdType <- rdTypes){ 302 allExuParams.map { 303 case exuParam => 304 val wbPortConfigs = exuParam.wbPortConfigs 305 val wbConfigs = wbType match{ 306 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 307 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 308 case _ => None 309 } 310 val rfReadPortConfigs = exuParam.rfrPortConfigs 311 val rdConfigs = rdType match{ 312 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 313 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 314 case _ => Seq() 315 } 316 (wbConfigs, rdConfigs) 317 }.filter(_._1.isDefined) 318 .sortBy(_._1.get.priority) 319 .groupBy(_._1.get.port).map { 320 case (_, intWbRdPairs) => 321 intWbRdPairs.map(_._2).flatten 322 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 323 case (_, rdCfgs) => 324 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 325 }) 326 } 327 } 328 } 329} 330 331 332 333 334