1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30 31import scala.reflect.ClassTag 32 33case class BackendParams( 34 schdParams : Map[SchedulerType, SchdBlockParams], 35 pregParams : Seq[PregParams], 36 iqWakeUpParams : Seq[WakeUpConfig], 37) { 38 39 configChecks 40 41 def intSchdParams = schdParams.get(IntScheduler()) 42 def vfSchdParams = schdParams.get(VfScheduler()) 43 def memSchdParams = schdParams.get(MemScheduler()) 44 def allSchdParams: Seq[SchdBlockParams] = 45 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 46 .filter(_.nonEmpty) 47 .map(_.get) 48 def allIssueParams: Seq[IssueBlockParams] = 49 allSchdParams.map(_.issueBlockParams).flatten 50 def allExuParams: Seq[ExeUnitParams] = 51 allIssueParams.map(_.exuBlockParams).flatten 52 53 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 54 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 55 def pregIdxWidth = pregParams.map(_.addrWidth).max 56 57 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 58 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 59 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 60 61 62 def AluCnt = allSchdParams.map(_.AluCnt).sum 63 def StaCnt = allSchdParams.map(_.StaCnt).sum 64 def StdCnt = allSchdParams.map(_.StdCnt).sum 65 def LduCnt = allSchdParams.map(_.LduCnt).sum 66 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 67 def LsExuCnt = StaCnt + LduCnt 68 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 69 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 70 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 71 72 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 73 74 def numIntWb = intPregParams.numWrite 75 def numVfWb = vfPregParams.numWrite 76 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 77 def numExu = allSchdParams.map(_.numExu).sum 78 def numRfRead = 14 79 def numRfWrite = 8 80 def vconfigPort = 0 // Todo: remove it 81 82 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 83 84 def numRedirect = allSchdParams.map(_.numRedirect).sum 85 86 def genIntWriteBackBundle(implicit p: Parameters) = { 87 // Todo: limit write port 88 Seq.tabulate(numIntWb)(x => new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 89 } 90 91 def genVfWriteBackBundle(implicit p: Parameters) = { 92 // Todo: limit write port 93 Seq.tabulate(numVfWb)(x => new RfWritePortWithConfig(VecData(), intPregParams.addrWidth)) 94 } 95 96 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 97 genIntWriteBackBundle ++ genVfWriteBackBundle 98 } 99 100 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 101 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).reduce(_ ++ _)) 102 } 103 104 def getIntWbArbiterParams: WbArbiterParams = { 105 val intWbCfgs: Seq[WbConfig] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)) 106 datapath.WbArbiterParams(intWbCfgs, intPregParams) 107 } 108 109 def getVfWbArbiterParams: WbArbiterParams = { 110 val vfWbCfgs = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)) 111 datapath.WbArbiterParams(vfWbCfgs, vfPregParams) 112 } 113 114 /** 115 * Get regfile read port params 116 * @param tag ClassTag of T 117 * @tparam T [[IntRD]] or [[VfRD]] 118 * @return Seq[port->Seq[(exuIdx, priority)] 119 */ 120 def getRdPortParams[T <: RdConfig](implicit tag: ClassTag[T]): Seq[(Int, Seq[(Int, Int)])] = { 121 // port -> Seq[exuIdx, priority] 122 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 123 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 124 .filter { x => ClassTag(x._1.getClass) == tag } 125 .map(x => (x._1.port, (x._2, x._1.priority))) 126 .groupBy(_._1) 127 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 128 .toSeq 129 .sortBy(_._1) 130 cfgs 131 } 132 133 /** 134 * Get regfile write back port params 135 * 136 * @param tag ClassTag of T 137 * @tparam T [[IntWB]] or [[VfWB]] 138 * @return Seq[port->Seq[(exuIdx, priority)] 139 */ 140 def getWbPortParams[T <: PregWB](implicit tag: ClassTag[T]) = { 141 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 142 .flatMap(x => x.wbPortConfigs.map(xx => (xx.asInstanceOf[PregWB], x.exuIdx))) 143 .filter { x => ClassTag(x._1.getClass) == tag } 144 .map(x => (x._1.port, (x._2, x._1.priority))) 145 .groupBy(_._1) 146 .map(x => (x._1, x._2.map(_._2))) 147 .toSeq 148 .sortBy(_._1) 149 cfgs 150 } 151 152 def getExuIdx(name: String): Int = { 153 val exuParams = allExuParams 154 if (name != "WB") { 155 val foundExu = exuParams.find(_.name == name) 156 require(foundExu.nonEmpty, s"exu $name not find") 157 foundExu.get.exuIdx 158 } else 159 -1 160 } 161 162 def getExuName(idx: Int): String = { 163 val exuParams = allExuParams 164 exuParams(idx).name 165 } 166 167 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 168 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 169 170 def configChecks = { 171 // check 0 172 val maxPortSource = 2 173 174 allExuParams.map { 175 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 176 }.filter(_.isDefined).groupBy(_.get.port).foreach { 177 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 178 } 179 allExuParams.map { 180 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 181 }.filter(_.isDefined).groupBy(_.get.port).foreach { 182 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 183 } 184 185 // check 1 186 val wbTypes = Seq(IntWB(), VfWB()) 187 val rdTypes = Seq(IntRD(), VfRD()) 188 for(wbType <- wbTypes){ 189 for(rdType <- rdTypes){ 190 allExuParams.map { 191 case exuParam => 192 val wbPortConfigs = exuParam.wbPortConfigs 193 val wbConfigs = wbType match{ 194 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 195 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 196 case _ => None 197 } 198 val rfReadPortConfigs = exuParam.rfrPortConfigs 199 val rdConfigs = rdType match{ 200 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 201 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 202 case _ => Seq() 203 } 204 (wbConfigs, rdConfigs) 205 }.filter(_._1.isDefined) 206 .sortBy(_._1.get.priority) 207 .groupBy(_._1.get.port).map { 208 case (_, intWbRdPairs) => 209 intWbRdPairs.map(_._2).flatten 210 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 211 case (_, rdCfgs) => 212 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 213 }) 214 } 215 } 216 } 217} 218 219 220 221 222