1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.DebugOptionsKey 31 32import scala.reflect.{ClassTag, classTag} 33 34case class BackendParams( 35 schdParams : Map[SchedulerType, SchdBlockParams], 36 pregParams : Seq[PregParams], 37 iqWakeUpParams : Seq[WakeUpConfig], 38) { 39 40 configChecks 41 42 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 43 def intSchdParams = schdParams.get(IntScheduler()) 44 def vfSchdParams = schdParams.get(VfScheduler()) 45 def memSchdParams = schdParams.get(MemScheduler()) 46 def allSchdParams: Seq[SchdBlockParams] = 47 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 48 .filter(_.nonEmpty) 49 .map(_.get) 50 def allIssueParams: Seq[IssueBlockParams] = 51 allSchdParams.map(_.issueBlockParams).flatten 52 def allExuParams: Seq[ExeUnitParams] = 53 allIssueParams.map(_.exuBlockParams).flatten 54 55 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 56 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 57 def getPregParams: Map[DataConfig, PregParams] = { 58 pregParams.map(x => (x.dataCfg, x)).toMap 59 } 60 61 def pregIdxWidth = pregParams.map(_.addrWidth).max 62 63 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 64 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 65 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 66 67 68 def AluCnt = allSchdParams.map(_.AluCnt).sum 69 def StaCnt = allSchdParams.map(_.StaCnt).sum 70 def StdCnt = allSchdParams.map(_.StdCnt).sum 71 def LduCnt = allSchdParams.map(_.LduCnt).sum 72 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 73 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 74 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 75 def LsExuCnt = StaCnt + LduCnt + HyuCnt 76 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 77 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 78 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 79 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 80 81 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 82 def numTargetReadPort = allExuParams.count(x => x.needTarget) 83 84 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 85 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 86 87 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 88 def numExu = allSchdParams.map(_.numExu).sum 89 def vconfigPort = 0 // Todo: remove it 90 91 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 92 93 def numRedirect = allSchdParams.map(_.numRedirect).sum 94 95 def genIntWriteBackBundle(implicit p: Parameters) = { 96 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 97 } 98 99 def genVfWriteBackBundle(implicit p: Parameters) = { 100 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 101 } 102 103 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 104 genIntWriteBackBundle ++ genVfWriteBackBundle 105 } 106 107 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 108 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 109 } 110 111 def getIntWbArbiterParams: WbArbiterParams = { 112 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 113 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 114 } 115 116 def getVfWbArbiterParams: WbArbiterParams = { 117 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 118 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 119 } 120 121 /** 122 * Get regfile read port params 123 * 124 * @param dataCfg [[IntData]] or [[VecData]] 125 * @return Seq[port->Seq[(exuIdx, priority)] 126 */ 127 def getRdPortParams(dataCfg: DataConfig) = { 128 // port -> Seq[exuIdx, priority] 129 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 130 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 131 .filter { x => x._1.getDataConfig == dataCfg } 132 .map(x => (x._1.port, (x._2, x._1.priority))) 133 .groupBy(_._1) 134 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 135 .toSeq 136 .sortBy(_._1) 137 cfgs 138 } 139 140 /** 141 * Get regfile write back port params 142 * 143 * @param dataCfg [[IntData]] or [[VecData]] 144 * @return Seq[port->Seq[(exuIdx, priority)] 145 */ 146 def getWbPortParams(dataCfg: DataConfig) = { 147 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 148 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 149 .filter { x => x._1.dataCfg == dataCfg } 150 .map(x => (x._1.port, (x._2, x._1.priority))) 151 .groupBy(_._1) 152 .map(x => (x._1, x._2.map(_._2))) 153 .toSeq 154 .sortBy(_._1) 155 cfgs 156 } 157 158 def getRdPortIndices(dataCfg: DataConfig) = { 159 this.getRdPortParams(dataCfg).map(_._1) 160 } 161 162 def getWbPortIndices(dataCfg: DataConfig) = { 163 this.getWbPortParams(dataCfg).map(_._1) 164 } 165 166 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 167 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 168 _.exuBlockParams.map( 169 _.rfrPortConfigs.map( 170 _.collectFirst{ case x: T => x } 171 .getOrElse(NoRD()) 172 ) 173 ) 174 ) 175 rdCfgs 176 } 177 178 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 179 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 180 } 181 182 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 183 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 184 wbCfgs 185 } 186 187 /** 188 * Get size of read ports of int regfile 189 * 190 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 191 */ 192 def getIntRfReadSize = { 193 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 194 } 195 196 /** 197 * Get size of write ports of vf regfile 198 * 199 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 200 */ 201 def getIntRfWriteSize = { 202 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 203 } 204 205 /** 206 * Get size of read ports of int regfile 207 * 208 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 209 */ 210 def getVfRfReadSize = { 211 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 212 } 213 214 /** 215 * Get size of write ports of vf regfile 216 * 217 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 218 */ 219 def getVfRfWriteSize = { 220 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 221 } 222 223 def getRfReadSize(dataCfg: DataConfig) = { 224 this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 225 } 226 227 def getRfWriteSize(dataCfg: DataConfig) = { 228 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 229 } 230 231 def getExuIdx(name: String): Int = { 232 val exuParams = allExuParams 233 if (name != "WB") { 234 val foundExu = exuParams.find(_.name == name) 235 require(foundExu.nonEmpty, s"exu $name not find") 236 foundExu.get.exuIdx 237 } else 238 -1 239 } 240 241 def getExuName(idx: Int): String = { 242 val exuParams = allExuParams 243 exuParams(idx).name 244 } 245 246 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 247 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 248 249 private def isContinuous(portIndices: Seq[Int]): Boolean = { 250 val portIndicesSet = portIndices.toSet 251 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 252 } 253 254 def configChecks = { 255 checkReadPortContinuous 256 checkWritePortContinuous 257 configCheck 258 } 259 260 def checkReadPortContinuous = { 261 pregParams.foreach { x => 262 if (x.numRead.isEmpty) { 263 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 264 require(isContinuous(portIndices), 265 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 266 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 267 } 268 } 269 } 270 271 def checkWritePortContinuous = { 272 pregParams.foreach { x => 273 if (x.numWrite.isEmpty) { 274 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 275 require( 276 isContinuous(portIndices), 277 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 278 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 279 ) 280 } 281 } 282 } 283 284 def configCheck = { 285 // check 0 286 val maxPortSource = 4 287 288 allExuParams.map { 289 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 290 }.filter(_.isDefined).groupBy(_.get.port).foreach { 291 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 292 } 293 allExuParams.map { 294 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 295 }.filter(_.isDefined).groupBy(_.get.port).foreach { 296 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 297 } 298 299 // check 1 300 val wbTypes = Seq(IntWB(), VfWB()) 301 val rdTypes = Seq(IntRD(), VfRD()) 302 for(wbType <- wbTypes){ 303 for(rdType <- rdTypes){ 304 allExuParams.map { 305 case exuParam => 306 val wbPortConfigs = exuParam.wbPortConfigs 307 val wbConfigs = wbType match{ 308 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 309 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 310 case _ => None 311 } 312 val rfReadPortConfigs = exuParam.rfrPortConfigs 313 val rdConfigs = rdType match{ 314 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 315 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 316 case _ => Seq() 317 } 318 (wbConfigs, rdConfigs) 319 }.filter(_._1.isDefined) 320 .sortBy(_._1.get.priority) 321 .groupBy(_._1.get.port).map { 322 case (_, intWbRdPairs) => 323 intWbRdPairs.map(_._2).flatten 324 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 325 case (_, rdCfgs) => 326 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 327 }) 328 } 329 } 330 } 331} 332