1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.RdConfig._ 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.{FuConfig, FuType} 29import xiangshan.backend.issue._ 30import xiangshan.backend.regfile._ 31 32case class BackendParams( 33 schdParams : Map[SchedulerType, SchdBlockParams], 34 pregParams : Seq[PregParams], 35 iqWakeUpParams : Seq[WakeUpConfig], 36) { 37 38 configChecks 39 40 def intSchdParams = schdParams.get(IntScheduler()) 41 def vfSchdParams = schdParams.get(VfScheduler()) 42 def memSchdParams = schdParams.get(MemScheduler()) 43 def allSchdParams: Seq[SchdBlockParams] = 44 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 45 .filter(_.nonEmpty) 46 .map(_.get) 47 def allIssueParams: Seq[IssueBlockParams] = 48 allSchdParams.map(_.issueBlockParams).flatten 49 def allExuParams: Seq[ExeUnitParams] = 50 allIssueParams.map(_.exuBlockParams).flatten 51 52 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 53 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 54 55 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 56 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 57 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 58 59 60 def AluCnt = allSchdParams.map(_.AluCnt).sum 61 def StaCnt = allSchdParams.map(_.StaCnt).sum 62 def StdCnt = allSchdParams.map(_.StdCnt).sum 63 def LduCnt = allSchdParams.map(_.LduCnt).sum 64 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 65 def LsExuCnt = StaCnt + LduCnt 66 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 67 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 68 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 69 70 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 71 72 def numIntWb = intPregParams.numWrite 73 def numVfWb = vfPregParams.numWrite 74 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 75 def numExu = allSchdParams.map(_.numExu).sum 76 def numRfRead = 14 77 def numRfWrite = 8 78 def vconfigPort = 0 // Todo: remove it 79 80 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 81 82 def numRedirect = allSchdParams.map(_.numRedirect).sum 83 84 def genIntWriteBackBundle(implicit p: Parameters) = { 85 // Todo: limit write port 86 Seq.tabulate(numIntWb)(x => new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 87 } 88 89 def genVfWriteBackBundle(implicit p: Parameters) = { 90 // Todo: limit write port 91 Seq.tabulate(numVfWb)(x => new RfWritePortWithConfig(VecData(), intPregParams.addrWidth)) 92 } 93 94 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 95 genIntWriteBackBundle ++ genVfWriteBackBundle 96 } 97 98 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 99 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).reduce(_ ++ _)) 100 } 101 102 def getIntWbArbiterParams: WbArbiterParams = { 103 val intWbCfgs: Seq[WbConfig] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)) 104 datapath.WbArbiterParams(intWbCfgs, intPregParams) 105 } 106 107 def getVfWbArbiterParams: WbArbiterParams = { 108 val vfWbCfgs = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)) 109 datapath.WbArbiterParams(vfWbCfgs, vfPregParams) 110 } 111 112 def getExuIdx(name: String): Int = { 113 val exuParams = allExuParams 114 if (name != "WB") 115 exuParams.find(_.name == name).get.exuIdx 116 else 117 -1 118 } 119 120 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 121 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 122 123 def configChecks = { 124 // check 0 125 val maxPortSource = 2 126 127 allExuParams.map { 128 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 129 }.filter(_.isDefined).groupBy(_.get.port).foreach { 130 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 131 } 132 allExuParams.map { 133 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 134 }.filter(_.isDefined).groupBy(_.get.port).foreach { 135 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 136 } 137 138 // check 1 139 val wbTypes = Seq(IntWB(), VfWB()) 140 val rdTypes = Seq(IntRD(), VfRD()) 141 for(wbType <- wbTypes){ 142 for(rdType <- rdTypes){ 143 allExuParams.map { 144 case exuParam => 145 val wbPortConfigs = exuParam.wbPortConfigs 146 val wbConfigs = wbType match{ 147 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 148 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 149 case _ => None 150 } 151 val rfReadPortConfigs = exuParam.rfrPortConfigs 152 val rdConfigs = rdType match{ 153 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 154 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 155 case _ => Seq() 156 } 157 (wbConfigs, rdConfigs) 158 }.filter(_._1.isDefined) 159 .sortBy(_._1.get.priority) 160 .groupBy(_._1.get.port).map { 161 case (_, intWbRdPairs) => 162 intWbRdPairs.map(_._2).flatten 163 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 164 case (_, rdCfgs) => 165 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 166 }) 167 } 168 } 169 } 170} 171 172 173 174 175