1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30import xiangshan.DebugOptionsKey 31 32import scala.reflect.{ClassTag, classTag} 33 34case class BackendParams( 35 schdParams : Map[SchedulerType, SchdBlockParams], 36 pregParams : Seq[PregParams], 37 iqWakeUpParams : Seq[WakeUpConfig], 38) { 39 40 configChecks 41 42 def debugEn(implicit p: Parameters): Boolean = p(DebugOptionsKey).AlwaysBasicDiff || p(DebugOptionsKey).EnableDifftest 43 def intSchdParams = schdParams.get(IntScheduler()) 44 def vfSchdParams = schdParams.get(VfScheduler()) 45 def memSchdParams = schdParams.get(MemScheduler()) 46 def allSchdParams: Seq[SchdBlockParams] = 47 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 48 .filter(_.nonEmpty) 49 .map(_.get) 50 def allIssueParams: Seq[IssueBlockParams] = 51 allSchdParams.map(_.issueBlockParams).flatten 52 def allExuParams: Seq[ExeUnitParams] = 53 allIssueParams.map(_.exuBlockParams).flatten 54 55 // filter not fake exu unit 56 def allRealExuParams = 57 allExuParams.filterNot(_.fakeUnit) 58 59 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 60 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 61 def getPregParams: Map[DataConfig, PregParams] = { 62 pregParams.map(x => (x.dataCfg, x)).toMap 63 } 64 65 def pregIdxWidth = pregParams.map(_.addrWidth).max 66 67 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 68 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 69 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 70 71 72 def AluCnt = allSchdParams.map(_.AluCnt).sum 73 def StaCnt = allSchdParams.map(_.StaCnt).sum 74 def StdCnt = allSchdParams.map(_.StdCnt).sum 75 def LduCnt = allSchdParams.map(_.LduCnt).sum 76 def HyuCnt = allSchdParams.map(_.HyuCnt).sum 77 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 78 def VstuCnt = allSchdParams.map(_.VstuCnt).sum 79 def LsExuCnt = StaCnt + LduCnt + HyuCnt 80 val LdExuCnt = LduCnt + HyuCnt 81 val StaExuCnt = StaCnt + HyuCnt 82 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 83 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 84 def CsrCnt = allSchdParams.map(_.CsrCnt).sum 85 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 86 87 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 88 def numTargetReadPort = allRealExuParams.count(x => x.needTarget) 89 90 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 91 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 92 93 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 94 def numExu = allSchdParams.map(_.numExu).sum 95 def vconfigPort = 0 // Todo: remove it 96 97 def numException = allRealExuParams.count(_.exceptionOut.nonEmpty) 98 99 def numRedirect = allSchdParams.map(_.numRedirect).sum 100 101 def genIntWriteBackBundle(implicit p: Parameters) = { 102 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 103 } 104 105 def genVfWriteBackBundle(implicit p: Parameters) = { 106 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 107 } 108 109 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 110 genIntWriteBackBundle ++ genVfWriteBackBundle 111 } 112 113 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 114 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).flatten) 115 } 116 117 def getIntWbArbiterParams: WbArbiterParams = { 118 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 119 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 120 } 121 122 def getVfWbArbiterParams: WbArbiterParams = { 123 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 124 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 125 } 126 127 /** 128 * Get regfile read port params 129 * 130 * @param dataCfg [[IntData]] or [[VecData]] 131 * @return Seq[port->Seq[(exuIdx, priority)] 132 */ 133 def getRdPortParams(dataCfg: DataConfig) = { 134 // port -> Seq[exuIdx, priority] 135 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 136 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 137 .filter { x => x._1.getDataConfig == dataCfg } 138 .map(x => (x._1.port, (x._2, x._1.priority))) 139 .groupBy(_._1) 140 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 141 .toSeq 142 .sortBy(_._1) 143 cfgs 144 } 145 146 /** 147 * Get regfile write back port params 148 * 149 * @param dataCfg [[IntData]] or [[VecData]] 150 * @return Seq[port->Seq[(exuIdx, priority)] 151 */ 152 def getWbPortParams(dataCfg: DataConfig) = { 153 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allRealExuParams 154 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 155 .filter { x => x._1.dataCfg == dataCfg } 156 .map(x => (x._1.port, (x._2, x._1.priority))) 157 .groupBy(_._1) 158 .map(x => (x._1, x._2.map(_._2))) 159 .toSeq 160 .sortBy(_._1) 161 cfgs 162 } 163 164 def getRdPortIndices(dataCfg: DataConfig) = { 165 this.getRdPortParams(dataCfg).map(_._1) 166 } 167 168 def getWbPortIndices(dataCfg: DataConfig) = { 169 this.getWbPortParams(dataCfg).map(_._1) 170 } 171 172 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 173 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 174 _.exuBlockParams.map( 175 _.rfrPortConfigs.map( 176 _.collectFirst{ case x: T => x } 177 .getOrElse(NoRD()) 178 ) 179 ) 180 ) 181 rdCfgs 182 } 183 184 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 185 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 186 } 187 188 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 189 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 190 wbCfgs 191 } 192 193 /** 194 * Get size of read ports of int regfile 195 * 196 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 197 */ 198 def getIntRfReadSize = { 199 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 200 } 201 202 /** 203 * Get size of write ports of vf regfile 204 * 205 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 206 */ 207 def getIntRfWriteSize = { 208 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 209 } 210 211 /** 212 * Get size of read ports of int regfile 213 * 214 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 215 */ 216 def getVfRfReadSize = { 217 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 218 } 219 220 /** 221 * Get size of write ports of vf regfile 222 * 223 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 224 */ 225 def getVfRfWriteSize = { 226 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 227 } 228 229 def getRfReadSize(dataCfg: DataConfig) = { 230 this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 231 } 232 233 def getRfWriteSize(dataCfg: DataConfig) = { 234 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 235 } 236 237 def getExuIdx(name: String): Int = { 238 val exuParams = allRealExuParams 239 if (name != "WB") { 240 val foundExu = exuParams.find(_.name == name) 241 require(foundExu.nonEmpty, s"exu $name not find") 242 foundExu.get.exuIdx 243 } else 244 -1 245 } 246 247 def getExuName(idx: Int): String = { 248 val exuParams = allRealExuParams 249 exuParams(idx).name 250 } 251 252 def getLdExuIdx(exu: ExeUnitParams): Int = { 253 val ldExuParams = allRealExuParams.filter(x => x.hasHyldaFu || x.hasLoadFu) 254 ldExuParams.indexOf(exu) 255 } 256 257 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 258 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allRealExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 259 260 private def isContinuous(portIndices: Seq[Int]): Boolean = { 261 val portIndicesSet = portIndices.toSet 262 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 263 } 264 265 def configChecks = { 266 checkReadPortContinuous 267 checkWritePortContinuous 268 configCheck 269 } 270 271 def checkReadPortContinuous = { 272 pregParams.foreach { x => 273 if (x.numRead.isEmpty) { 274 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 275 require(isContinuous(portIndices), 276 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 277 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 278 } 279 } 280 } 281 282 def checkWritePortContinuous = { 283 pregParams.foreach { x => 284 if (x.numWrite.isEmpty) { 285 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 286 require( 287 isContinuous(portIndices), 288 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 289 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 290 ) 291 } 292 } 293 } 294 295 def configCheck = { 296 // check 0 297 val maxPortSource = 4 298 299 allRealExuParams.map { 300 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 301 }.filter(_.isDefined).groupBy(_.get.port).foreach { 302 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 303 } 304 allRealExuParams.map { 305 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 306 }.filter(_.isDefined).groupBy(_.get.port).foreach { 307 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 308 } 309 310 // check 1 311 val wbTypes = Seq(IntWB(), VfWB()) 312 val rdTypes = Seq(IntRD(), VfRD()) 313 for(wbType <- wbTypes){ 314 for(rdType <- rdTypes){ 315 allRealExuParams.map { 316 case exuParam => 317 val wbPortConfigs = exuParam.wbPortConfigs 318 val wbConfigs = wbType match{ 319 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 320 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 321 case _ => None 322 } 323 val rfReadPortConfigs = exuParam.rfrPortConfigs 324 val rdConfigs = rdType match{ 325 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 326 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 327 case _ => Seq() 328 } 329 (wbConfigs, rdConfigs) 330 }.filter(_._1.isDefined) 331 .sortBy(_._1.get.priority) 332 .groupBy(_._1.get.port).map { 333 case (_, intWbRdPairs) => 334 intWbRdPairs.map(_._2).flatten 335 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 336 case (_, rdCfgs) => 337 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 338 }) 339 } 340 } 341 } 342} 343