bpu: support parameterizetion of path history length

bpu: add support for path hist

BPU: Add SC into BPU

backend: add ExuBlock to wrap execution units and RS (#903)

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
--> --> Scheduler --> RS

ras: add ras

bpu: Add Tage

Add Tage into Composer
Add global history manage logic in BPU
Modify CfiUpdate interface: sawNotTakenBranch -> br_hit

BPU: Fix Bim read idx bug

Fix Bim read idx bug
Remove valids in BranchPredictionResp
Modify out from Decoupled to Output in BasePredictorIO

[WIP]BPU: Move pipeline from Composer to BPU

[WIP]BPU: Fix composser popeline bugs

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

[WIP]BPU: Fix BPU cannot fire bugs

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: o

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

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ptw: update PTWRepeater to support multi-port by RRArbiter (#874)

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show

ptw: update PTWRepeater to support multi-port by RRArbiter (#874)

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show that: the filter is critical for perf
like mcf(5m):
old ptw:2.38
new ptw with repeater: 2.41
new ptw with filter: 2.58

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scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

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[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update s

[WIP] finish ftq logic and fix syntax errors

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

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[WIP] BPU: Modify interface name
add handshake between pipeline stage

ptw: update PTWRepeater to support multi-port by RRArbiter (#874)

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show

ptw: update PTWRepeater to support multi-port by RRArbiter (#874)

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show that: the filter is critical for perf
like mcf(5m):
old ptw:2.38
new ptw with repeater: 2.41
new ptw with filter: 2.58

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Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

PTW: rewrite ptw for multiple requests support (#811)

* PTW: add ptw multi-processing graph

* [WIP] PTW: try to add miss queue, failed for complexity and not very useful

* [WIP] PTW: rewrite p

PTW: rewrite ptw for multiple requests support (#811)

* PTW: add ptw multi-processing graph

* [WIP] PTW: try to add miss queue, failed for complexity and not very useful

* [WIP] PTW: rewrite ptw for multi req support

* PTW: remove some assert, fix level init bug

* PTW: itlb has highter priority than dtlb

* PTW: fix bug that mix cache's resp logic

* PTW: fix stupid bug that mix .U and .W

* PTW: replay will not be blocked if fsm empty

* PTW: miss queue req may return miss queue

In the before design, only miss queue req can go into
fsm, and would not be blocked.
Now, to simplify design, miss queue req are just the
same with new req, may blocked, going to fsm or miss queue.

* PTW: fix ptw filter iss valid bug

* PTW.fsm: fix bug that should not mem.req when sfenceLatch

* PTW: fix ptw sfenceLatch's bug

* PTW: add some perf counters

* PTW: fix bug in filter enq ptr logic

* PTW: fix bug of sfence in ptw

* test: add current branch to ci-test, tmp

* PTW: fix bug of cache's hit logic and fsm's pf

* PTW: fix bug of filter's enq and block* signal

* PTW: fix bug of filter's pteResp filter

* PTW: add some assert of filter's counter

* PTW: fix bug of filter's enq logic

* PTW: set PTWMSHRSIZE 16

* PTW: fix naive perf counter's bug

* PTW: set PTWMSHRSIZE 8

* PTW: set PTWMSHRSIZE 32

* Revert "PTW: set PTWMSHRSIZE 32"

This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef.

* Revert "test: add current branch to ci-test, tmp"

This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.

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Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, Xian

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls

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backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup st

backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d14

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt

Co-authored-by: ZhangZifei <[email protected]>

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Disable L2 and L3 in MinimalConfig

Config: add MinimalConfig

MinimalConfig limited queues' size, disabled TAGE to limit generated
verilog size

Usage: change `config = DefaultConfig` to `config = MinimalConfig`
in Top.scala / SimTop.

Config: add MinimalConfig

MinimalConfig limited queues' size, disabled TAGE to limit generated
verilog size

Usage: change `config = DefaultConfig` to `config = MinimalConfig`
in Top.scala / SimTop.scala

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cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795)

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also a

cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795)

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

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parameters: set defualt value of EnableDebug to be true (#772)