1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan 17 18import chipsalliance.rocketchip.config.{Field, Parameters} 19import chisel3._ 20import chisel3.util._ 21import xiangshan.backend.exu._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.dispatch.DispatchParameters 25import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 26import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 27import xiangshan.frontend.{BIM, ICacheParameters ,BasePredictor, BranchPredictionResp, FTB, MicroBTB} 28 29case object XSCoreParamsKey extends Field[XSCoreParameters] 30 31case class XSCoreParameters 32( 33 HasPrefetch: Boolean = false, 34 HartId: Int = 0, 35 XLEN: Int = 64, 36 HasMExtension: Boolean = true, 37 HasCExtension: Boolean = true, 38 HasDiv: Boolean = true, 39 HasICache: Boolean = true, 40 HasDCache: Boolean = true, 41 AddrBits: Int = 64, 42 VAddrBits: Int = 39, 43 PAddrBits: Int = 40, 44 HasFPU: Boolean = true, 45 FetchWidth: Int = 8, 46 EnableBPU: Boolean = true, 47 EnableBPD: Boolean = true, 48 EnableRAS: Boolean = true, 49 EnableLB: Boolean = false, 50 EnableLoop: Boolean = true, 51 EnableSC: Boolean = true, 52 EnbaleTlbDebug: Boolean = false, 53 EnableJal: Boolean = false, 54 EnableUBTB: Boolean = true, 55 HistoryLength: Int = 64, 56 BtbSize: Int = 2048, 57 JbtacSize: Int = 1024, 58 JbtacBanks: Int = 8, 59 RasSize: Int = 16, 60 CacheLineSize: Int = 512, 61 UBtbWays: Int = 16, 62 BtbWays: Int = 2, 63 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 64 ((resp_in: BranchPredictionResp, p: Parameters) => { 65 // val loop = Module(new LoopPredictor) 66 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 67 // else Module(new Tage) } 68 // else { Module(new FakeTage) }) 69 val ftb = Module(new FTB()(p)) 70 val ubtb = Module(new MicroBTB()(p)) 71 val bim = Module(new BIM()(p)) 72 // val fake = Module(new FakePredictor()) 73 74 // val preds = Seq(loop, tage, btb, ubtb, bim) 75 val preds = Seq(ftb, ubtb, bim) 76 preds.map(_.io := DontCare) 77 78 // ubtb.io.resp_in(0) := resp_in 79 // bim.io.resp_in(0) := ubtb.io.resp 80 // btb.io.resp_in(0) := bim.io.resp 81 // tage.io.resp_in(0) := btb.io.resp 82 // loop.io.resp_in(0) := tage.io.resp 83 ubtb.io.in.bits.resp_in(0) := resp_in 84 bim.io.in.bits.resp_in(0) := ubtb.io.out.bits.resp 85 ftb.io.in.bits.resp_in(0) := bim.io.out.bits.resp 86 87 (preds, ftb.io.out.bits.resp) 88 }), 89 90 91 EnableL1plusPrefetcher: Boolean = true, 92 IBufSize: Int = 48, 93 DecodeWidth: Int = 6, 94 RenameWidth: Int = 6, 95 CommitWidth: Int = 6, 96 BrqSize: Int = 32, 97 FtqSize: Int = 48, 98 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 99 IssQueSize: Int = 16, 100 NRPhyRegs: Int = 160, 101 NRIntReadPorts: Int = 14, 102 NRIntWritePorts: Int = 8, 103 NRFpReadPorts: Int = 14, 104 NRFpWritePorts: Int = 8, 105 LoadQueueSize: Int = 64, 106 StoreQueueSize: Int = 48, 107 RoqSize: Int = 192, 108 dpParams: DispatchParameters = DispatchParameters( 109 IntDqSize = 16, 110 FpDqSize = 16, 111 LsDqSize = 16, 112 IntDqDeqWidth = 4, 113 FpDqDeqWidth = 4, 114 LsDqDeqWidth = 4 115 ), 116 exuParameters: ExuParameters = ExuParameters( 117 JmpCnt = 1, 118 AluCnt = 4, 119 MulCnt = 0, 120 MduCnt = 2, 121 FmacCnt = 4, 122 FmiscCnt = 2, 123 FmiscDivSqrtCnt = 0, 124 LduCnt = 2, 125 StuCnt = 2 126 ), 127 LoadPipelineWidth: Int = 2, 128 StorePipelineWidth: Int = 2, 129 StoreBufferSize: Int = 16, 130 StoreBufferThreshold: Int = 7, 131 RefillSize: Int = 512, 132 TlbEntrySize: Int = 32, 133 TlbSPEntrySize: Int = 4, 134 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 135 PtwSPEntrySize: Int = 16, 136 PtwL1EntrySize: Int = 16, 137 PtwL2EntrySize: Int = 2048, //(256 * 8) 138 PtwMissQueueSize: Int = 8, 139 NumPerfCounters: Int = 16, 140 icacheParameters: ICacheParameters = ICacheParameters( 141 tagECC = Some("parity"), 142 dataECC = Some("parity"), 143 replacer = Some("setplru"), 144 nMissEntries = 2 145 ), 146 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 147 tagECC = Some("secded"), 148 dataECC = Some("secded"), 149 replacer = Some("setplru"), 150 nMissEntries = 8 151 ), 152 dcacheParameters: DCacheParameters = DCacheParameters( 153 tagECC = Some("secded"), 154 dataECC = Some("secded"), 155 replacer = Some("setplru"), 156 nMissEntries = 16, 157 nProbeEntries = 16, 158 nReleaseEntries = 16, 159 nStoreReplayEntries = 16 160 ), 161 L2Size: Int = 512 * 1024, // 512KB 162 L2NWays: Int = 8, 163 useFakePTW: Boolean = false, 164 useFakeDCache: Boolean = false, 165 useFakeL1plusCache: Boolean = false, 166 useFakeL2Cache: Boolean = false 167){ 168 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 169 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 170 171 val intExuConfigs = JumpExeUnitCfg +: ( 172 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++ 173 Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) 174 ) 175 176 val fpExuConfigs = 177 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 178 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 179 180 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 181} 182 183case object DebugOptionsKey extends Field[DebugOptions] 184 185case class DebugOptions 186( 187 FPGAPlatform: Boolean = true, 188 EnableDebug: Boolean = true, 189 EnablePerfDebug: Boolean = true, 190 UseDRAMSim: Boolean = false 191) 192 193trait HasXSParameter { 194 195 implicit val p: Parameters 196 197 val coreParams = p(XSCoreParamsKey) 198 val env = p(DebugOptionsKey) 199 200 val XLEN = coreParams.XLEN 201 val hardId = coreParams.HartId 202 val minFLen = 32 203 val fLen = 64 204 def xLen = XLEN 205 206 val HasMExtension = coreParams.HasMExtension 207 val HasCExtension = coreParams.HasCExtension 208 val HasDiv = coreParams.HasDiv 209 val HasIcache = coreParams.HasICache 210 val HasDcache = coreParams.HasDCache 211 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 212 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 213 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 214 val AddrBytes = AddrBits / 8 // unused 215 val DataBits = XLEN 216 val DataBytes = DataBits / 8 217 val HasFPU = coreParams.HasFPU 218 val FetchWidth = coreParams.FetchWidth 219 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 220 val EnableBPU = coreParams.EnableBPU 221 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 222 val EnableRAS = coreParams.EnableRAS 223 val EnableLB = coreParams.EnableLB 224 val EnableLoop = coreParams.EnableLoop 225 val EnableSC = coreParams.EnableSC 226 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 227 val HistoryLength = coreParams.HistoryLength 228 val BtbSize = coreParams.BtbSize 229 // val BtbWays = 4 230 val BtbBanks = PredictWidth 231 // val BtbSets = BtbSize / BtbWays 232 val JbtacSize = coreParams.JbtacSize 233 val JbtacBanks = coreParams.JbtacBanks 234 val RasSize = coreParams.RasSize 235 236 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 237 coreParams.branchPredictor(resp_in, p) 238 } 239 240 val CacheLineSize = coreParams.CacheLineSize 241 val CacheLineHalfWord = CacheLineSize / 16 242 val ExtHistoryLength = HistoryLength + 64 243 val UBtbWays = coreParams.UBtbWays 244 val BtbWays = coreParams.BtbWays 245 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 246 val IBufSize = coreParams.IBufSize 247 val DecodeWidth = coreParams.DecodeWidth 248 val RenameWidth = coreParams.RenameWidth 249 val CommitWidth = coreParams.CommitWidth 250 val BrqSize = coreParams.BrqSize 251 val FtqSize = coreParams.FtqSize 252 val IssQueSize = coreParams.IssQueSize 253 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 254 val BrTagWidth = log2Up(BrqSize) 255 val NRPhyRegs = coreParams.NRPhyRegs 256 val PhyRegIdxWidth = log2Up(NRPhyRegs) 257 val RoqSize = coreParams.RoqSize 258 val LoadQueueSize = coreParams.LoadQueueSize 259 val StoreQueueSize = coreParams.StoreQueueSize 260 val dpParams = coreParams.dpParams 261 val exuParameters = coreParams.exuParameters 262 val NRIntReadPorts = coreParams.NRIntReadPorts 263 val NRIntWritePorts = coreParams.NRIntWritePorts 264 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 265 val NRFpReadPorts = coreParams.NRFpReadPorts 266 val NRFpWritePorts = coreParams.NRFpWritePorts 267 val LoadPipelineWidth = coreParams.LoadPipelineWidth 268 val StorePipelineWidth = coreParams.StorePipelineWidth 269 val StoreBufferSize = coreParams.StoreBufferSize 270 val StoreBufferThreshold = coreParams.StoreBufferThreshold 271 val RefillSize = coreParams.RefillSize 272 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 273 val TlbEntrySize = coreParams.TlbEntrySize 274 val TlbSPEntrySize = coreParams.TlbSPEntrySize 275 val PtwL3EntrySize = coreParams.PtwL3EntrySize 276 val PtwSPEntrySize = coreParams.PtwSPEntrySize 277 val PtwL1EntrySize = coreParams.PtwL1EntrySize 278 val PtwL2EntrySize = coreParams.PtwL2EntrySize 279 val PtwMissQueueSize = coreParams.PtwMissQueueSize 280 val NumPerfCounters = coreParams.NumPerfCounters 281 282 val instBytes = if (HasCExtension) 2 else 4 283 val instOffsetBits = log2Ceil(instBytes) 284 285 val icacheParameters = coreParams.icacheParameters 286 val l1plusCacheParameters = coreParams.l1plusCacheParameters 287 val dcacheParameters = coreParams.dcacheParameters 288 289 val LRSCCycles = 100 290 291 292 // cache hierarchy configurations 293 val l1BusDataWidth = 256 294 295 val useFakeDCache = coreParams.useFakeDCache 296 val useFakePTW = coreParams.useFakePTW 297 val useFakeL1plusCache = coreParams.useFakeL1plusCache 298 // L2 configurations 299 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 300 val L1BusWidth = 256 301 val L2Size = coreParams.L2Size 302 val L2BlockSize = 64 303 val L2NWays = coreParams.L2NWays 304 val L2NSets = L2Size / L2BlockSize / L2NWays 305 306 // L3 configurations 307 val L2BusWidth = 256 308 309 // icache prefetcher 310 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 311 enable = true, 312 _type = "stream", 313 streamParams = StreamPrefetchParameters( 314 streamCnt = 2, 315 streamSize = 4, 316 ageWidth = 4, 317 blockBytes = l1plusCacheParameters.blockBytes, 318 reallocStreamOnMissInstantly = true, 319 cacheName = "icache" 320 ) 321 ) 322 323 // dcache prefetcher 324 val l2PrefetcherParameters = L2PrefetcherParameters( 325 enable = true, 326 _type = "bop", // "stream" or "bop" 327 streamParams = StreamPrefetchParameters( 328 streamCnt = 4, 329 streamSize = 4, 330 ageWidth = 4, 331 blockBytes = L2BlockSize, 332 reallocStreamOnMissInstantly = true, 333 cacheName = "dcache" 334 ), 335 bopParams = BOPParameters( 336 rrTableEntries = 256, 337 rrTagBits = 12, 338 scoreBits = 5, 339 roundMax = 50, 340 badScore = 1, 341 blockBytes = L2BlockSize, 342 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 343 ), 344 ) 345 346 // load violation predict 347 val ResetTimeMax2Pow = 20 //1078576 348 val ResetTimeMin2Pow = 10 //1024 349 // wait table parameters 350 val WaitTableSize = 1024 351 val MemPredPCWidth = log2Up(WaitTableSize) 352 val LWTUse2BitCounter = true 353 // store set parameters 354 val SSITSize = WaitTableSize 355 val LFSTSize = 32 356 val SSIDWidth = log2Up(LFSTSize) 357 val LFSTWidth = 4 358 val StoreSetEnable = true // LWT will be disabled if SS is enabled 359 360 val loadExuConfigs = coreParams.loadExuConfigs 361 val storeExuConfigs = coreParams.storeExuConfigs 362 363 val intExuConfigs = coreParams.intExuConfigs 364 365 val fpExuConfigs = coreParams.fpExuConfigs 366 367 val exuConfigs = coreParams.exuConfigs 368 369} 370