1package xiangshan 2 3import chipsalliance.rocketchip.config.{Field, Parameters} 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.exu._ 7import xiangshan.backend.fu._ 8import xiangshan.backend.fu.fpu._ 9import xiangshan.backend.dispatch.DispatchParameters 10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 11import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 12 13case object XSCoreParamsKey extends Field[XSCoreParameters] 14 15case class XSCoreParameters 16( 17 HasL2Cache: Boolean = false, 18 HasPrefetch: Boolean = false, 19 HartId: Int = 0, 20 XLEN: Int = 64, 21 HasMExtension: Boolean = true, 22 HasCExtension: Boolean = true, 23 HasDiv: Boolean = true, 24 HasICache: Boolean = true, 25 HasDCache: Boolean = true, 26 AddrBits: Int = 64, 27 VAddrBits: Int = 39, 28 PAddrBits: Int = 40, 29 HasFPU: Boolean = true, 30 FetchWidth: Int = 8, 31 EnableBPU: Boolean = true, 32 EnableBPD: Boolean = true, 33 EnableRAS: Boolean = true, 34 EnableLB: Boolean = false, 35 EnableLoop: Boolean = true, 36 EnableSC: Boolean = true, 37 EnbaleTlbDebug: Boolean = false, 38 EnableJal: Boolean = false, 39 EnableUBTB: Boolean = true, 40 HistoryLength: Int = 64, 41 BtbSize: Int = 2048, 42 JbtacSize: Int = 1024, 43 JbtacBanks: Int = 8, 44 RasSize: Int = 16, 45 CacheLineSize: Int = 512, 46 UBtbWays: Int = 16, 47 BtbWays: Int = 2, 48 49 EnableL1plusPrefetcher: Boolean = true, 50 IBufSize: Int = 48, 51 DecodeWidth: Int = 6, 52 RenameWidth: Int = 6, 53 CommitWidth: Int = 6, 54 BrqSize: Int = 32, 55 FtqSize: Int = 48, 56 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 57 IssQueSize: Int = 16, 58 NRPhyRegs: Int = 160, 59 NRIntReadPorts: Int = 14, 60 NRIntWritePorts: Int = 8, 61 NRFpReadPorts: Int = 14, 62 NRFpWritePorts: Int = 8, 63 LoadQueueSize: Int = 64, 64 StoreQueueSize: Int = 48, 65 RoqSize: Int = 192, 66 dpParams: DispatchParameters = DispatchParameters( 67 IntDqSize = 16, 68 FpDqSize = 16, 69 LsDqSize = 16, 70 IntDqDeqWidth = 4, 71 FpDqDeqWidth = 4, 72 LsDqDeqWidth = 4 73 ), 74 exuParameters: ExuParameters = ExuParameters( 75 JmpCnt = 1, 76 AluCnt = 4, 77 MulCnt = 0, 78 MduCnt = 2, 79 FmacCnt = 4, 80 FmiscCnt = 2, 81 FmiscDivSqrtCnt = 0, 82 LduCnt = 2, 83 StuCnt = 2 84 ), 85 LoadPipelineWidth: Int = 2, 86 StorePipelineWidth: Int = 2, 87 StoreBufferSize: Int = 16, 88 RefillSize: Int = 512, 89 TlbEntrySize: Int = 32, 90 TlbSPEntrySize: Int = 4, 91 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 92 PtwSPEntrySize: Int = 16, 93 PtwL1EntrySize: Int = 16, 94 PtwL2EntrySize: Int = 2048, //(256 * 8) 95 NumPerfCounters: Int = 16, 96){ 97 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 98 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 99 100 val intExuConfigs = JumpExeUnitCfg +: ( 101 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++ 102 Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) 103 ) 104 105 val fpExuConfigs = 106 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 107 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 108 109 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 110} 111 112case object DebugOptionsKey extends Field[DebugOptions] 113 114case class DebugOptions 115( 116 FPGAPlatform: Boolean = true, 117 EnableDebug: Boolean = true, 118 EnablePerfDebug: Boolean = true, 119 UseDRAMSim: Boolean = false 120) 121 122trait HasXSParameter { 123 124 implicit val p: Parameters 125 126 val coreParams = p(XSCoreParamsKey) 127 val env = p(DebugOptionsKey) 128 129 val XLEN = coreParams.XLEN 130 val hardId = coreParams.HartId 131 val minFLen = 32 132 val fLen = 64 133 def xLen = XLEN 134 135 val HasMExtension = coreParams.HasMExtension 136 val HasCExtension = coreParams.HasCExtension 137 val HasDiv = coreParams.HasDiv 138 val HasIcache = coreParams.HasICache 139 val HasDcache = coreParams.HasDCache 140 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 141 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 142 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 143 val AddrBytes = AddrBits / 8 // unused 144 val DataBits = XLEN 145 val DataBytes = DataBits / 8 146 val HasFPU = coreParams.HasFPU 147 val FetchWidth = coreParams.FetchWidth 148 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 149 val EnableBPU = coreParams.EnableBPU 150 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 151 val EnableRAS = coreParams.EnableRAS 152 val EnableLB = coreParams.EnableLB 153 val EnableLoop = coreParams.EnableLoop 154 val EnableSC = coreParams.EnableSC 155 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 156 val HistoryLength = coreParams.HistoryLength 157 val BtbSize = coreParams.BtbSize 158 // val BtbWays = 4 159 val BtbBanks = PredictWidth 160 // val BtbSets = BtbSize / BtbWays 161 val JbtacSize = coreParams.JbtacSize 162 val JbtacBanks = coreParams.JbtacBanks 163 val RasSize = coreParams.RasSize 164 val CacheLineSize = coreParams.CacheLineSize 165 val CacheLineHalfWord = CacheLineSize / 16 166 val ExtHistoryLength = HistoryLength + 64 167 val UBtbWays = coreParams.UBtbWays 168 val BtbWays = coreParams.BtbWays 169 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 170 val IBufSize = coreParams.IBufSize 171 val DecodeWidth = coreParams.DecodeWidth 172 val RenameWidth = coreParams.RenameWidth 173 val CommitWidth = coreParams.CommitWidth 174 val BrqSize = coreParams.BrqSize 175 val FtqSize = coreParams.FtqSize 176 val IssQueSize = coreParams.IssQueSize 177 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 178 val BrTagWidth = log2Up(BrqSize) 179 val NRPhyRegs = coreParams.NRPhyRegs 180 val PhyRegIdxWidth = log2Up(NRPhyRegs) 181 val RoqSize = coreParams.RoqSize 182 val LoadQueueSize = coreParams.LoadQueueSize 183 val StoreQueueSize = coreParams.StoreQueueSize 184 val dpParams = coreParams.dpParams 185 val exuParameters = coreParams.exuParameters 186 val NRIntReadPorts = coreParams.NRIntReadPorts 187 val NRIntWritePorts = coreParams.NRIntWritePorts 188 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 189 val NRFpReadPorts = coreParams.NRFpReadPorts 190 val NRFpWritePorts = coreParams.NRFpWritePorts 191 val LoadPipelineWidth = coreParams.LoadPipelineWidth 192 val StorePipelineWidth = coreParams.StorePipelineWidth 193 val StoreBufferSize = coreParams.StoreBufferSize 194 val RefillSize = coreParams.RefillSize 195 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 196 val TlbEntrySize = coreParams.TlbEntrySize 197 val TlbSPEntrySize = coreParams.TlbSPEntrySize 198 val useFakePTW = false 199 val PtwL3EntrySize = coreParams.PtwL3EntrySize 200 val PtwSPEntrySize = coreParams.PtwSPEntrySize 201 val PtwL1EntrySize = coreParams.PtwL1EntrySize 202 val PtwL2EntrySize = coreParams.PtwL2EntrySize 203 val NumPerfCounters = coreParams.NumPerfCounters 204 205 val instBytes = if (HasCExtension) 2 else 4 206 val instOffsetBits = log2Ceil(instBytes) 207 208 val icacheParameters = ICacheParameters( 209 tagECC = Some("parity"), 210 dataECC = Some("parity"), 211 replacer = Some("setplru"), 212 nMissEntries = 2 213 ) 214 215 val useFakeL1plusCache = false 216 val l1plusCacheParameters = L1plusCacheParameters( 217 tagECC = Some("secded"), 218 dataECC = Some("secded"), 219 replacer = Some("setplru"), 220 nMissEntries = 8 221 ) 222 223 val useFakeDCache = false 224 val dcacheParameters = DCacheParameters( 225 tagECC = Some("secded"), 226 dataECC = Some("secded"), 227 replacer = Some("setplru"), 228 nMissEntries = 16, 229 nProbeEntries = 16, 230 nReleaseEntries = 16, 231 nStoreReplayEntries = 16 232 ) 233 234 val LRSCCycles = 100 235 236 237 // cache hierarchy configurations 238 val l1BusDataWidth = 256 239 240 // L2 configurations 241 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache 242 val L1BusWidth = 256 243 val L2Size = 512 * 1024 // 512KB 244 val L2BlockSize = 64 245 val L2NWays = 8 246 val L2NSets = L2Size / L2BlockSize / L2NWays 247 248 // L3 configurations 249 val L2BusWidth = 256 250 251 // icache prefetcher 252 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 253 enable = true, 254 _type = "stream", 255 streamParams = StreamPrefetchParameters( 256 streamCnt = 2, 257 streamSize = 4, 258 ageWidth = 4, 259 blockBytes = l1plusCacheParameters.blockBytes, 260 reallocStreamOnMissInstantly = true, 261 cacheName = "icache" 262 ) 263 ) 264 265 // dcache prefetcher 266 val l2PrefetcherParameters = L2PrefetcherParameters( 267 enable = true, 268 _type = "bop", // "stream" or "bop" 269 streamParams = StreamPrefetchParameters( 270 streamCnt = 4, 271 streamSize = 4, 272 ageWidth = 4, 273 blockBytes = L2BlockSize, 274 reallocStreamOnMissInstantly = true, 275 cacheName = "dcache" 276 ), 277 bopParams = BOPParameters( 278 rrTableEntries = 256, 279 rrTagBits = 12, 280 scoreBits = 5, 281 roundMax = 50, 282 badScore = 1, 283 blockBytes = L2BlockSize, 284 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 285 ), 286 ) 287 288 val loadExuConfigs = coreParams.loadExuConfigs 289 val storeExuConfigs = coreParams.storeExuConfigs 290 291 val intExuConfigs = coreParams.intExuConfigs 292 293 val fpExuConfigs = coreParams.fpExuConfigs 294 295 val exuConfigs = coreParams.exuConfigs 296 297} 298