1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan 17 18import chipsalliance.rocketchip.config.{Field, Parameters} 19import chisel3._ 20import chisel3.util._ 21import xiangshan.backend.exu._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.dispatch.DispatchParameters 25import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 26import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, Tage_SC} 28 29case object XSCoreParamsKey extends Field[XSCoreParameters] 30 31case class XSCoreParameters 32( 33 HasPrefetch: Boolean = false, 34 HartId: Int = 0, 35 XLEN: Int = 64, 36 HasMExtension: Boolean = true, 37 HasCExtension: Boolean = true, 38 HasDiv: Boolean = true, 39 HasICache: Boolean = true, 40 HasDCache: Boolean = true, 41 AddrBits: Int = 64, 42 VAddrBits: Int = 39, 43 PAddrBits: Int = 40, 44 HasFPU: Boolean = true, 45 FetchWidth: Int = 8, 46 EnableBPU: Boolean = true, 47 EnableBPD: Boolean = true, 48 EnableRAS: Boolean = true, 49 EnableLB: Boolean = false, 50 EnableLoop: Boolean = true, 51 EnableSC: Boolean = true, 52 EnbaleTlbDebug: Boolean = false, 53 EnableJal: Boolean = false, 54 EnableUBTB: Boolean = true, 55 HistoryLength: Int = 64, 56 BtbSize: Int = 2048, 57 JbtacSize: Int = 1024, 58 JbtacBanks: Int = 8, 59 RasSize: Int = 16, 60 CacheLineSize: Int = 512, 61 UBtbWays: Int = 16, 62 BtbWays: Int = 2, 63 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 64 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 65 // val loop = Module(new LoopPredictor) 66 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 67 // else Module(new Tage) } 68 // else { Module(new FakeTage) }) 69 val ftb = Module(new FTB()(p)) 70 val ubtb = Module(new MicroBTB()(p)) 71 val bim = Module(new BIM()(p)) 72 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 73 val ras = Module(new RAS()(p)) 74 // val tage = Module(new Tage()(p)) 75 // val fake = Module(new FakePredictor()(p)) 76 77 // val preds = Seq(loop, tage, btb, ubtb, bim) 78 val preds = Seq(ubtb, bim, ftb, tage, ras) 79 preds.map(_.io := DontCare) 80 81 // ubtb.io.resp_in(0) := resp_in 82 // bim.io.resp_in(0) := ubtb.io.resp 83 // btb.io.resp_in(0) := bim.io.resp 84 // tage.io.resp_in(0) := btb.io.resp 85 // loop.io.resp_in(0) := tage.io.resp 86 ubtb.io.in.bits.resp_in(0) := resp_in 87 bim.io.in.bits.resp_in(0) := ubtb.io.out.resp 88 ftb.io.in.bits.resp_in(0) := bim.io.out.resp 89 tage.io.in.bits.resp_in(0) := ftb.io.out.resp 90 ras.io.in.bits.resp_in(0) := tage.io.out.resp 91 92 (preds, ras.io.out.resp) 93 }), 94 95 96 EnableL1plusPrefetcher: Boolean = true, 97 IBufSize: Int = 48, 98 DecodeWidth: Int = 6, 99 RenameWidth: Int = 6, 100 CommitWidth: Int = 6, 101 BrqSize: Int = 32, 102 FtqSize: Int = 48, 103 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 104 IssQueSize: Int = 16, 105 NRPhyRegs: Int = 160, 106 NRIntReadPorts: Int = 14, 107 NRIntWritePorts: Int = 8, 108 NRFpReadPorts: Int = 14, 109 NRFpWritePorts: Int = 8, 110 LoadQueueSize: Int = 64, 111 StoreQueueSize: Int = 48, 112 RoqSize: Int = 192, 113 dpParams: DispatchParameters = DispatchParameters( 114 IntDqSize = 16, 115 FpDqSize = 16, 116 LsDqSize = 16, 117 IntDqDeqWidth = 4, 118 FpDqDeqWidth = 4, 119 LsDqDeqWidth = 4 120 ), 121 exuParameters: ExuParameters = ExuParameters( 122 JmpCnt = 1, 123 AluCnt = 4, 124 MulCnt = 0, 125 MduCnt = 2, 126 FmacCnt = 4, 127 FmiscCnt = 2, 128 FmiscDivSqrtCnt = 0, 129 LduCnt = 2, 130 StuCnt = 2 131 ), 132 LoadPipelineWidth: Int = 2, 133 StorePipelineWidth: Int = 2, 134 StoreBufferSize: Int = 16, 135 StoreBufferThreshold: Int = 7, 136 RefillSize: Int = 512, 137 TlbEntrySize: Int = 32, 138 TlbSPEntrySize: Int = 4, 139 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 140 PtwSPEntrySize: Int = 16, 141 PtwL1EntrySize: Int = 16, 142 PtwL2EntrySize: Int = 2048, //(256 * 8) 143 PtwMissQueueSize: Int = 8, 144 NumPerfCounters: Int = 16, 145 icacheParameters: ICacheParameters = ICacheParameters( 146 tagECC = Some("parity"), 147 dataECC = Some("parity"), 148 replacer = Some("setplru"), 149 nMissEntries = 2 150 ), 151 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 152 tagECC = Some("secded"), 153 dataECC = Some("secded"), 154 replacer = Some("setplru"), 155 nMissEntries = 8 156 ), 157 dcacheParameters: DCacheParameters = DCacheParameters( 158 tagECC = Some("secded"), 159 dataECC = Some("secded"), 160 replacer = Some("setplru"), 161 nMissEntries = 16, 162 nProbeEntries = 16, 163 nReleaseEntries = 16, 164 nStoreReplayEntries = 16 165 ), 166 L2Size: Int = 512 * 1024, // 512KB 167 L2NWays: Int = 8, 168 usePTWRepeater: Boolean = false, 169 useFakePTW: Boolean = false, 170 useFakeDCache: Boolean = false, 171 useFakeL1plusCache: Boolean = false, 172 useFakeL2Cache: Boolean = false 173){ 174 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 175 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 176 177 val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 178 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpExeUnitCfg 179 180 val fpExuConfigs = 181 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 182 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 183 184 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 185} 186 187case object DebugOptionsKey extends Field[DebugOptions] 188 189case class DebugOptions 190( 191 FPGAPlatform: Boolean = true, 192 EnableDebug: Boolean = true, 193 EnablePerfDebug: Boolean = true, 194 UseDRAMSim: Boolean = false 195) 196 197trait HasXSParameter { 198 199 implicit val p: Parameters 200 201 val coreParams = p(XSCoreParamsKey) 202 val env = p(DebugOptionsKey) 203 204 val XLEN = coreParams.XLEN 205 val hardId = coreParams.HartId 206 val minFLen = 32 207 val fLen = 64 208 def xLen = XLEN 209 210 val HasMExtension = coreParams.HasMExtension 211 val HasCExtension = coreParams.HasCExtension 212 val HasDiv = coreParams.HasDiv 213 val HasIcache = coreParams.HasICache 214 val HasDcache = coreParams.HasDCache 215 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 216 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 217 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 218 val AddrBytes = AddrBits / 8 // unused 219 val DataBits = XLEN 220 val DataBytes = DataBits / 8 221 val HasFPU = coreParams.HasFPU 222 val FetchWidth = coreParams.FetchWidth 223 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 224 val EnableBPU = coreParams.EnableBPU 225 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 226 val EnableRAS = coreParams.EnableRAS 227 val EnableLB = coreParams.EnableLB 228 val EnableLoop = coreParams.EnableLoop 229 val EnableSC = coreParams.EnableSC 230 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 231 val HistoryLength = coreParams.HistoryLength 232 val BtbSize = coreParams.BtbSize 233 // val BtbWays = 4 234 val BtbBanks = PredictWidth 235 // val BtbSets = BtbSize / BtbWays 236 val JbtacSize = coreParams.JbtacSize 237 val JbtacBanks = coreParams.JbtacBanks 238 val RasSize = coreParams.RasSize 239 240 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 241 coreParams.branchPredictor(resp_in, p, enableSC) 242 } 243 244 val CacheLineSize = coreParams.CacheLineSize 245 val CacheLineHalfWord = CacheLineSize / 16 246 val ExtHistoryLength = HistoryLength + 64 247 val UBtbWays = coreParams.UBtbWays 248 val BtbWays = coreParams.BtbWays 249 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 250 val IBufSize = coreParams.IBufSize 251 val DecodeWidth = coreParams.DecodeWidth 252 val RenameWidth = coreParams.RenameWidth 253 val CommitWidth = coreParams.CommitWidth 254 val BrqSize = coreParams.BrqSize 255 val FtqSize = coreParams.FtqSize 256 val IssQueSize = coreParams.IssQueSize 257 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 258 val BrTagWidth = log2Up(BrqSize) 259 val NRPhyRegs = coreParams.NRPhyRegs 260 val PhyRegIdxWidth = log2Up(NRPhyRegs) 261 val RoqSize = coreParams.RoqSize 262 val LoadQueueSize = coreParams.LoadQueueSize 263 val StoreQueueSize = coreParams.StoreQueueSize 264 val dpParams = coreParams.dpParams 265 val exuParameters = coreParams.exuParameters 266 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 267 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 268 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 269 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 270 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 271 val LoadPipelineWidth = coreParams.LoadPipelineWidth 272 val StorePipelineWidth = coreParams.StorePipelineWidth 273 val StoreBufferSize = coreParams.StoreBufferSize 274 val StoreBufferThreshold = coreParams.StoreBufferThreshold 275 val RefillSize = coreParams.RefillSize 276 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 277 val TlbEntrySize = coreParams.TlbEntrySize 278 val TlbSPEntrySize = coreParams.TlbSPEntrySize 279 val PtwL3EntrySize = coreParams.PtwL3EntrySize 280 val PtwSPEntrySize = coreParams.PtwSPEntrySize 281 val PtwL1EntrySize = coreParams.PtwL1EntrySize 282 val PtwL2EntrySize = coreParams.PtwL2EntrySize 283 val PtwMissQueueSize = coreParams.PtwMissQueueSize 284 val NumPerfCounters = coreParams.NumPerfCounters 285 286 val instBytes = if (HasCExtension) 2 else 4 287 val instOffsetBits = log2Ceil(instBytes) 288 289 val icacheParameters = coreParams.icacheParameters 290 val l1plusCacheParameters = coreParams.l1plusCacheParameters 291 val dcacheParameters = coreParams.dcacheParameters 292 293 val LRSCCycles = 100 294 295 296 // cache hierarchy configurations 297 val l1BusDataWidth = 256 298 299 val usePTWRepeater = coreParams.usePTWRepeater 300 val useFakeDCache = coreParams.useFakeDCache 301 val useFakePTW = coreParams.useFakePTW 302 val useFakeL1plusCache = coreParams.useFakeL1plusCache 303 // L2 configurations 304 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 305 val L1BusWidth = 256 306 val L2Size = coreParams.L2Size 307 val L2BlockSize = 64 308 val L2NWays = coreParams.L2NWays 309 val L2NSets = L2Size / L2BlockSize / L2NWays 310 311 // L3 configurations 312 val L2BusWidth = 256 313 314 // icache prefetcher 315 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 316 enable = true, 317 _type = "stream", 318 streamParams = StreamPrefetchParameters( 319 streamCnt = 2, 320 streamSize = 4, 321 ageWidth = 4, 322 blockBytes = l1plusCacheParameters.blockBytes, 323 reallocStreamOnMissInstantly = true, 324 cacheName = "icache" 325 ) 326 ) 327 328 // dcache prefetcher 329 val l2PrefetcherParameters = L2PrefetcherParameters( 330 enable = true, 331 _type = "bop", // "stream" or "bop" 332 streamParams = StreamPrefetchParameters( 333 streamCnt = 4, 334 streamSize = 4, 335 ageWidth = 4, 336 blockBytes = L2BlockSize, 337 reallocStreamOnMissInstantly = true, 338 cacheName = "dcache" 339 ), 340 bopParams = BOPParameters( 341 rrTableEntries = 256, 342 rrTagBits = 12, 343 scoreBits = 5, 344 roundMax = 50, 345 badScore = 1, 346 blockBytes = L2BlockSize, 347 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 348 ), 349 ) 350 351 // load violation predict 352 val ResetTimeMax2Pow = 20 //1078576 353 val ResetTimeMin2Pow = 10 //1024 354 // wait table parameters 355 val WaitTableSize = 1024 356 val MemPredPCWidth = log2Up(WaitTableSize) 357 val LWTUse2BitCounter = true 358 // store set parameters 359 val SSITSize = WaitTableSize 360 val LFSTSize = 32 361 val SSIDWidth = log2Up(LFSTSize) 362 val LFSTWidth = 4 363 val StoreSetEnable = true // LWT will be disabled if SS is enabled 364 365 val loadExuConfigs = coreParams.loadExuConfigs 366 val storeExuConfigs = coreParams.storeExuConfigs 367 368 val intExuConfigs = coreParams.intExuConfigs 369 370 val fpExuConfigs = coreParams.fpExuConfigs 371 372 val exuConfigs = coreParams.exuConfigs 373 374} 375