1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan 17 18import chipsalliance.rocketchip.config.{Field, Parameters} 19import chisel3._ 20import chisel3.util._ 21import xiangshan.backend.exu._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.dispatch.DispatchParameters 25import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 26import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, Tage} 28import xiangshan.frontend.RAS 29 30case object XSCoreParamsKey extends Field[XSCoreParameters] 31 32case class XSCoreParameters 33( 34 HasPrefetch: Boolean = false, 35 HartId: Int = 0, 36 XLEN: Int = 64, 37 HasMExtension: Boolean = true, 38 HasCExtension: Boolean = true, 39 HasDiv: Boolean = true, 40 HasICache: Boolean = true, 41 HasDCache: Boolean = true, 42 AddrBits: Int = 64, 43 VAddrBits: Int = 39, 44 PAddrBits: Int = 40, 45 HasFPU: Boolean = true, 46 FetchWidth: Int = 8, 47 EnableBPU: Boolean = true, 48 EnableBPD: Boolean = true, 49 EnableRAS: Boolean = true, 50 EnableLB: Boolean = false, 51 EnableLoop: Boolean = true, 52 EnableSC: Boolean = true, 53 EnbaleTlbDebug: Boolean = false, 54 EnableJal: Boolean = false, 55 EnableUBTB: Boolean = true, 56 HistoryLength: Int = 64, 57 BtbSize: Int = 2048, 58 JbtacSize: Int = 1024, 59 JbtacBanks: Int = 8, 60 RasSize: Int = 16, 61 CacheLineSize: Int = 512, 62 UBtbWays: Int = 16, 63 BtbWays: Int = 2, 64 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 65 ((resp_in: BranchPredictionResp, p: Parameters) => { 66 // val loop = Module(new LoopPredictor) 67 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 68 // else Module(new Tage) } 69 // else { Module(new FakeTage) }) 70 val ftb = Module(new FTB()(p)) 71 val ubtb = Module(new MicroBTB()(p)) 72 val bim = Module(new BIM()(p)) 73 val tage = Module(new Tage()(p)) 74 val ras = Module(new RAS()(p)) 75 // val tage = Module(new Tage()(p)) 76 // val fake = Module(new FakePredictor()(p)) 77 78 // val preds = Seq(loop, tage, btb, ubtb, bim) 79 val preds = Seq(ubtb, bim, ftb, tage, ras) 80 preds.map(_.io := DontCare) 81 82 // ubtb.io.resp_in(0) := resp_in 83 // bim.io.resp_in(0) := ubtb.io.resp 84 // btb.io.resp_in(0) := bim.io.resp 85 // tage.io.resp_in(0) := btb.io.resp 86 // loop.io.resp_in(0) := tage.io.resp 87 ubtb.io.in.bits.resp_in(0) := resp_in 88 bim.io.in.bits.resp_in(0) := ubtb.io.out.resp 89 ftb.io.in.bits.resp_in(0) := bim.io.out.resp 90 tage.io.in.bits.resp_in(0) := ftb.io.out.resp 91 ras.io.in.bits.resp_in(0) := tage.io.out.resp 92 93 (preds, ras.io.out.resp) 94 }), 95 96 97 EnableL1plusPrefetcher: Boolean = true, 98 IBufSize: Int = 48, 99 DecodeWidth: Int = 6, 100 RenameWidth: Int = 6, 101 CommitWidth: Int = 6, 102 BrqSize: Int = 32, 103 FtqSize: Int = 48, 104 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 105 IssQueSize: Int = 16, 106 NRPhyRegs: Int = 160, 107 NRIntReadPorts: Int = 14, 108 NRIntWritePorts: Int = 8, 109 NRFpReadPorts: Int = 14, 110 NRFpWritePorts: Int = 8, 111 LoadQueueSize: Int = 64, 112 StoreQueueSize: Int = 48, 113 RoqSize: Int = 192, 114 dpParams: DispatchParameters = DispatchParameters( 115 IntDqSize = 16, 116 FpDqSize = 16, 117 LsDqSize = 16, 118 IntDqDeqWidth = 4, 119 FpDqDeqWidth = 4, 120 LsDqDeqWidth = 4 121 ), 122 exuParameters: ExuParameters = ExuParameters( 123 JmpCnt = 1, 124 AluCnt = 4, 125 MulCnt = 0, 126 MduCnt = 2, 127 FmacCnt = 4, 128 FmiscCnt = 2, 129 FmiscDivSqrtCnt = 0, 130 LduCnt = 2, 131 StuCnt = 2 132 ), 133 LoadPipelineWidth: Int = 2, 134 StorePipelineWidth: Int = 2, 135 StoreBufferSize: Int = 16, 136 StoreBufferThreshold: Int = 7, 137 RefillSize: Int = 512, 138 TlbEntrySize: Int = 32, 139 TlbSPEntrySize: Int = 4, 140 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 141 PtwSPEntrySize: Int = 16, 142 PtwL1EntrySize: Int = 16, 143 PtwL2EntrySize: Int = 2048, //(256 * 8) 144 PtwMissQueueSize: Int = 8, 145 NumPerfCounters: Int = 16, 146 icacheParameters: ICacheParameters = ICacheParameters( 147 tagECC = Some("parity"), 148 dataECC = Some("parity"), 149 replacer = Some("setplru"), 150 nMissEntries = 2 151 ), 152 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 153 tagECC = Some("secded"), 154 dataECC = Some("secded"), 155 replacer = Some("setplru"), 156 nMissEntries = 8 157 ), 158 dcacheParameters: DCacheParameters = DCacheParameters( 159 tagECC = Some("secded"), 160 dataECC = Some("secded"), 161 replacer = Some("setplru"), 162 nMissEntries = 16, 163 nProbeEntries = 16, 164 nReleaseEntries = 16, 165 nStoreReplayEntries = 16 166 ), 167 L2Size: Int = 512 * 1024, // 512KB 168 L2NWays: Int = 8, 169 usePTWRepeater: Boolean = false, 170 useFakePTW: Boolean = false, 171 useFakeDCache: Boolean = false, 172 useFakeL1plusCache: Boolean = false, 173 useFakeL2Cache: Boolean = false 174){ 175 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 176 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 177 178 val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 179 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpExeUnitCfg 180 181 val fpExuConfigs = 182 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 183 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 184 185 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 186} 187 188case object DebugOptionsKey extends Field[DebugOptions] 189 190case class DebugOptions 191( 192 FPGAPlatform: Boolean = true, 193 EnableDebug: Boolean = true, 194 EnablePerfDebug: Boolean = true, 195 UseDRAMSim: Boolean = false 196) 197 198trait HasXSParameter { 199 200 implicit val p: Parameters 201 202 val coreParams = p(XSCoreParamsKey) 203 val env = p(DebugOptionsKey) 204 205 val XLEN = coreParams.XLEN 206 val hardId = coreParams.HartId 207 val minFLen = 32 208 val fLen = 64 209 def xLen = XLEN 210 211 val HasMExtension = coreParams.HasMExtension 212 val HasCExtension = coreParams.HasCExtension 213 val HasDiv = coreParams.HasDiv 214 val HasIcache = coreParams.HasICache 215 val HasDcache = coreParams.HasDCache 216 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 217 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 218 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 219 val AddrBytes = AddrBits / 8 // unused 220 val DataBits = XLEN 221 val DataBytes = DataBits / 8 222 val HasFPU = coreParams.HasFPU 223 val FetchWidth = coreParams.FetchWidth 224 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 225 val EnableBPU = coreParams.EnableBPU 226 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 227 val EnableRAS = coreParams.EnableRAS 228 val EnableLB = coreParams.EnableLB 229 val EnableLoop = coreParams.EnableLoop 230 val EnableSC = coreParams.EnableSC 231 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 232 val HistoryLength = coreParams.HistoryLength 233 val BtbSize = coreParams.BtbSize 234 // val BtbWays = 4 235 val BtbBanks = PredictWidth 236 // val BtbSets = BtbSize / BtbWays 237 val JbtacSize = coreParams.JbtacSize 238 val JbtacBanks = coreParams.JbtacBanks 239 val RasSize = coreParams.RasSize 240 241 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 242 coreParams.branchPredictor(resp_in, p) 243 } 244 245 val CacheLineSize = coreParams.CacheLineSize 246 val CacheLineHalfWord = CacheLineSize / 16 247 val ExtHistoryLength = HistoryLength + 64 248 val UBtbWays = coreParams.UBtbWays 249 val BtbWays = coreParams.BtbWays 250 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 251 val IBufSize = coreParams.IBufSize 252 val DecodeWidth = coreParams.DecodeWidth 253 val RenameWidth = coreParams.RenameWidth 254 val CommitWidth = coreParams.CommitWidth 255 val BrqSize = coreParams.BrqSize 256 val FtqSize = coreParams.FtqSize 257 val IssQueSize = coreParams.IssQueSize 258 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 259 val BrTagWidth = log2Up(BrqSize) 260 val NRPhyRegs = coreParams.NRPhyRegs 261 val PhyRegIdxWidth = log2Up(NRPhyRegs) 262 val RoqSize = coreParams.RoqSize 263 val LoadQueueSize = coreParams.LoadQueueSize 264 val StoreQueueSize = coreParams.StoreQueueSize 265 val dpParams = coreParams.dpParams 266 val exuParameters = coreParams.exuParameters 267 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 268 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 269 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 270 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 271 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 272 val LoadPipelineWidth = coreParams.LoadPipelineWidth 273 val StorePipelineWidth = coreParams.StorePipelineWidth 274 val StoreBufferSize = coreParams.StoreBufferSize 275 val StoreBufferThreshold = coreParams.StoreBufferThreshold 276 val RefillSize = coreParams.RefillSize 277 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 278 val TlbEntrySize = coreParams.TlbEntrySize 279 val TlbSPEntrySize = coreParams.TlbSPEntrySize 280 val PtwL3EntrySize = coreParams.PtwL3EntrySize 281 val PtwSPEntrySize = coreParams.PtwSPEntrySize 282 val PtwL1EntrySize = coreParams.PtwL1EntrySize 283 val PtwL2EntrySize = coreParams.PtwL2EntrySize 284 val PtwMissQueueSize = coreParams.PtwMissQueueSize 285 val NumPerfCounters = coreParams.NumPerfCounters 286 287 val instBytes = if (HasCExtension) 2 else 4 288 val instOffsetBits = log2Ceil(instBytes) 289 290 val icacheParameters = coreParams.icacheParameters 291 val l1plusCacheParameters = coreParams.l1plusCacheParameters 292 val dcacheParameters = coreParams.dcacheParameters 293 294 val LRSCCycles = 100 295 296 297 // cache hierarchy configurations 298 val l1BusDataWidth = 256 299 300 val usePTWRepeater = coreParams.usePTWRepeater 301 val useFakeDCache = coreParams.useFakeDCache 302 val useFakePTW = coreParams.useFakePTW 303 val useFakeL1plusCache = coreParams.useFakeL1plusCache 304 // L2 configurations 305 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 306 val L1BusWidth = 256 307 val L2Size = coreParams.L2Size 308 val L2BlockSize = 64 309 val L2NWays = coreParams.L2NWays 310 val L2NSets = L2Size / L2BlockSize / L2NWays 311 312 // L3 configurations 313 val L2BusWidth = 256 314 315 // icache prefetcher 316 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 317 enable = true, 318 _type = "stream", 319 streamParams = StreamPrefetchParameters( 320 streamCnt = 2, 321 streamSize = 4, 322 ageWidth = 4, 323 blockBytes = l1plusCacheParameters.blockBytes, 324 reallocStreamOnMissInstantly = true, 325 cacheName = "icache" 326 ) 327 ) 328 329 // dcache prefetcher 330 val l2PrefetcherParameters = L2PrefetcherParameters( 331 enable = true, 332 _type = "bop", // "stream" or "bop" 333 streamParams = StreamPrefetchParameters( 334 streamCnt = 4, 335 streamSize = 4, 336 ageWidth = 4, 337 blockBytes = L2BlockSize, 338 reallocStreamOnMissInstantly = true, 339 cacheName = "dcache" 340 ), 341 bopParams = BOPParameters( 342 rrTableEntries = 256, 343 rrTagBits = 12, 344 scoreBits = 5, 345 roundMax = 50, 346 badScore = 1, 347 blockBytes = L2BlockSize, 348 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 349 ), 350 ) 351 352 // load violation predict 353 val ResetTimeMax2Pow = 20 //1078576 354 val ResetTimeMin2Pow = 10 //1024 355 // wait table parameters 356 val WaitTableSize = 1024 357 val MemPredPCWidth = log2Up(WaitTableSize) 358 val LWTUse2BitCounter = true 359 // store set parameters 360 val SSITSize = WaitTableSize 361 val LFSTSize = 32 362 val SSIDWidth = log2Up(LFSTSize) 363 val LFSTWidth = 4 364 val StoreSetEnable = true // LWT will be disabled if SS is enabled 365 366 val loadExuConfigs = coreParams.loadExuConfigs 367 val storeExuConfigs = coreParams.storeExuConfigs 368 369 val intExuConfigs = coreParams.intExuConfigs 370 371 val fpExuConfigs = coreParams.fpExuConfigs 372 373 val exuConfigs = coreParams.exuConfigs 374 375} 376