1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan 17 18import chipsalliance.rocketchip.config.{Field, Parameters} 19import chisel3._ 20import chisel3.util._ 21import xiangshan.backend.exu._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.dispatch.DispatchParameters 25import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 26import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, Tage} 28 29case object XSCoreParamsKey extends Field[XSCoreParameters] 30 31case class XSCoreParameters 32( 33 HasPrefetch: Boolean = false, 34 HartId: Int = 0, 35 XLEN: Int = 64, 36 HasMExtension: Boolean = true, 37 HasCExtension: Boolean = true, 38 HasDiv: Boolean = true, 39 HasICache: Boolean = true, 40 HasDCache: Boolean = true, 41 AddrBits: Int = 64, 42 VAddrBits: Int = 39, 43 PAddrBits: Int = 40, 44 HasFPU: Boolean = true, 45 FetchWidth: Int = 8, 46 EnableBPU: Boolean = true, 47 EnableBPD: Boolean = true, 48 EnableRAS: Boolean = true, 49 EnableLB: Boolean = false, 50 EnableLoop: Boolean = true, 51 EnableSC: Boolean = true, 52 EnbaleTlbDebug: Boolean = false, 53 EnableJal: Boolean = false, 54 EnableUBTB: Boolean = true, 55 HistoryLength: Int = 64, 56 BtbSize: Int = 2048, 57 JbtacSize: Int = 1024, 58 JbtacBanks: Int = 8, 59 RasSize: Int = 16, 60 CacheLineSize: Int = 512, 61 UBtbWays: Int = 16, 62 BtbWays: Int = 2, 63 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 64 ((resp_in: BranchPredictionResp, p: Parameters) => { 65 // val loop = Module(new LoopPredictor) 66 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 67 // else Module(new Tage) } 68 // else { Module(new FakeTage) }) 69 val ftb = Module(new FTB()(p)) 70 val ubtb = Module(new MicroBTB()(p)) 71 val bim = Module(new BIM()(p)) 72 val tage = Module(new Tage()(p)) 73 // val fake = Module(new FakePredictor()(p)) 74 75 // val preds = Seq(loop, tage, btb, ubtb, bim) 76 val preds = Seq(ubtb, bim, ftb, tage) 77 preds.map(_.io := DontCare) 78 79 // ubtb.io.resp_in(0) := resp_in 80 // bim.io.resp_in(0) := ubtb.io.resp 81 // btb.io.resp_in(0) := bim.io.resp 82 // tage.io.resp_in(0) := btb.io.resp 83 // loop.io.resp_in(0) := tage.io.resp 84 ubtb.io.in.bits.resp_in(0) := resp_in 85 bim.io.in.bits.resp_in(0) := ubtb.io.out.resp 86 ftb.io.in.bits.resp_in(0) := bim.io.out.resp 87 tage.io.in.bits.resp_in(0) := ftb.io.out.resp 88 89 (preds, tage.io.out.resp) 90 // (preds, ftb.io.out.resp) 91 }), 92 93 94 EnableL1plusPrefetcher: Boolean = true, 95 IBufSize: Int = 48, 96 DecodeWidth: Int = 6, 97 RenameWidth: Int = 6, 98 CommitWidth: Int = 6, 99 BrqSize: Int = 32, 100 FtqSize: Int = 48, 101 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 102 IssQueSize: Int = 16, 103 NRPhyRegs: Int = 160, 104 NRIntReadPorts: Int = 14, 105 NRIntWritePorts: Int = 8, 106 NRFpReadPorts: Int = 14, 107 NRFpWritePorts: Int = 8, 108 LoadQueueSize: Int = 64, 109 StoreQueueSize: Int = 48, 110 RoqSize: Int = 192, 111 dpParams: DispatchParameters = DispatchParameters( 112 IntDqSize = 16, 113 FpDqSize = 16, 114 LsDqSize = 16, 115 IntDqDeqWidth = 4, 116 FpDqDeqWidth = 4, 117 LsDqDeqWidth = 4 118 ), 119 exuParameters: ExuParameters = ExuParameters( 120 JmpCnt = 1, 121 AluCnt = 4, 122 MulCnt = 0, 123 MduCnt = 2, 124 FmacCnt = 4, 125 FmiscCnt = 2, 126 FmiscDivSqrtCnt = 0, 127 LduCnt = 2, 128 StuCnt = 2 129 ), 130 LoadPipelineWidth: Int = 2, 131 StorePipelineWidth: Int = 2, 132 StoreBufferSize: Int = 16, 133 StoreBufferThreshold: Int = 7, 134 RefillSize: Int = 512, 135 TlbEntrySize: Int = 32, 136 TlbSPEntrySize: Int = 4, 137 PtwL3EntrySize: Int = 4096, //(256 * 16) or 512 138 PtwSPEntrySize: Int = 16, 139 PtwL1EntrySize: Int = 16, 140 PtwL2EntrySize: Int = 2048, //(256 * 8) 141 PtwMissQueueSize: Int = 8, 142 NumPerfCounters: Int = 16, 143 icacheParameters: ICacheParameters = ICacheParameters( 144 tagECC = Some("parity"), 145 dataECC = Some("parity"), 146 replacer = Some("setplru"), 147 nMissEntries = 2 148 ), 149 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 150 tagECC = Some("secded"), 151 dataECC = Some("secded"), 152 replacer = Some("setplru"), 153 nMissEntries = 8 154 ), 155 dcacheParameters: DCacheParameters = DCacheParameters( 156 tagECC = Some("secded"), 157 dataECC = Some("secded"), 158 replacer = Some("setplru"), 159 nMissEntries = 16, 160 nProbeEntries = 16, 161 nReleaseEntries = 16, 162 nStoreReplayEntries = 16 163 ), 164 L2Size: Int = 512 * 1024, // 512KB 165 L2NWays: Int = 8, 166 usePTWRepeater: Boolean = false, 167 useFakePTW: Boolean = false, 168 useFakeDCache: Boolean = false, 169 useFakeL1plusCache: Boolean = false, 170 useFakeL2Cache: Boolean = false 171){ 172 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 173 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg) 174 175 val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 176 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpExeUnitCfg 177 178 val fpExuConfigs = 179 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 180 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 181 182 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 183} 184 185case object DebugOptionsKey extends Field[DebugOptions] 186 187case class DebugOptions 188( 189 FPGAPlatform: Boolean = true, 190 EnableDebug: Boolean = true, 191 EnablePerfDebug: Boolean = true, 192 UseDRAMSim: Boolean = false 193) 194 195trait HasXSParameter { 196 197 implicit val p: Parameters 198 199 val coreParams = p(XSCoreParamsKey) 200 val env = p(DebugOptionsKey) 201 202 val XLEN = coreParams.XLEN 203 val hardId = coreParams.HartId 204 val minFLen = 32 205 val fLen = 64 206 def xLen = XLEN 207 208 val HasMExtension = coreParams.HasMExtension 209 val HasCExtension = coreParams.HasCExtension 210 val HasDiv = coreParams.HasDiv 211 val HasIcache = coreParams.HasICache 212 val HasDcache = coreParams.HasDCache 213 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 214 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 215 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 216 val AddrBytes = AddrBits / 8 // unused 217 val DataBits = XLEN 218 val DataBytes = DataBits / 8 219 val HasFPU = coreParams.HasFPU 220 val FetchWidth = coreParams.FetchWidth 221 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 222 val EnableBPU = coreParams.EnableBPU 223 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 224 val EnableRAS = coreParams.EnableRAS 225 val EnableLB = coreParams.EnableLB 226 val EnableLoop = coreParams.EnableLoop 227 val EnableSC = coreParams.EnableSC 228 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 229 val HistoryLength = coreParams.HistoryLength 230 val BtbSize = coreParams.BtbSize 231 // val BtbWays = 4 232 val BtbBanks = PredictWidth 233 // val BtbSets = BtbSize / BtbWays 234 val JbtacSize = coreParams.JbtacSize 235 val JbtacBanks = coreParams.JbtacBanks 236 val RasSize = coreParams.RasSize 237 238 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 239 coreParams.branchPredictor(resp_in, p) 240 } 241 242 val CacheLineSize = coreParams.CacheLineSize 243 val CacheLineHalfWord = CacheLineSize / 16 244 val ExtHistoryLength = HistoryLength + 64 245 val UBtbWays = coreParams.UBtbWays 246 val BtbWays = coreParams.BtbWays 247 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 248 val IBufSize = coreParams.IBufSize 249 val DecodeWidth = coreParams.DecodeWidth 250 val RenameWidth = coreParams.RenameWidth 251 val CommitWidth = coreParams.CommitWidth 252 val BrqSize = coreParams.BrqSize 253 val FtqSize = coreParams.FtqSize 254 val IssQueSize = coreParams.IssQueSize 255 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 256 val BrTagWidth = log2Up(BrqSize) 257 val NRPhyRegs = coreParams.NRPhyRegs 258 val PhyRegIdxWidth = log2Up(NRPhyRegs) 259 val RoqSize = coreParams.RoqSize 260 val LoadQueueSize = coreParams.LoadQueueSize 261 val StoreQueueSize = coreParams.StoreQueueSize 262 val dpParams = coreParams.dpParams 263 val exuParameters = coreParams.exuParameters 264 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 265 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 266 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 267 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 268 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 269 val LoadPipelineWidth = coreParams.LoadPipelineWidth 270 val StorePipelineWidth = coreParams.StorePipelineWidth 271 val StoreBufferSize = coreParams.StoreBufferSize 272 val StoreBufferThreshold = coreParams.StoreBufferThreshold 273 val RefillSize = coreParams.RefillSize 274 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 275 val TlbEntrySize = coreParams.TlbEntrySize 276 val TlbSPEntrySize = coreParams.TlbSPEntrySize 277 val PtwL3EntrySize = coreParams.PtwL3EntrySize 278 val PtwSPEntrySize = coreParams.PtwSPEntrySize 279 val PtwL1EntrySize = coreParams.PtwL1EntrySize 280 val PtwL2EntrySize = coreParams.PtwL2EntrySize 281 val PtwMissQueueSize = coreParams.PtwMissQueueSize 282 val NumPerfCounters = coreParams.NumPerfCounters 283 284 val instBytes = if (HasCExtension) 2 else 4 285 val instOffsetBits = log2Ceil(instBytes) 286 287 val icacheParameters = coreParams.icacheParameters 288 val l1plusCacheParameters = coreParams.l1plusCacheParameters 289 val dcacheParameters = coreParams.dcacheParameters 290 291 val LRSCCycles = 100 292 293 294 // cache hierarchy configurations 295 val l1BusDataWidth = 256 296 297 val usePTWRepeater = coreParams.usePTWRepeater 298 val useFakeDCache = coreParams.useFakeDCache 299 val useFakePTW = coreParams.useFakePTW 300 val useFakeL1plusCache = coreParams.useFakeL1plusCache 301 // L2 configurations 302 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 303 val L1BusWidth = 256 304 val L2Size = coreParams.L2Size 305 val L2BlockSize = 64 306 val L2NWays = coreParams.L2NWays 307 val L2NSets = L2Size / L2BlockSize / L2NWays 308 309 // L3 configurations 310 val L2BusWidth = 256 311 312 // icache prefetcher 313 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 314 enable = true, 315 _type = "stream", 316 streamParams = StreamPrefetchParameters( 317 streamCnt = 2, 318 streamSize = 4, 319 ageWidth = 4, 320 blockBytes = l1plusCacheParameters.blockBytes, 321 reallocStreamOnMissInstantly = true, 322 cacheName = "icache" 323 ) 324 ) 325 326 // dcache prefetcher 327 val l2PrefetcherParameters = L2PrefetcherParameters( 328 enable = true, 329 _type = "bop", // "stream" or "bop" 330 streamParams = StreamPrefetchParameters( 331 streamCnt = 4, 332 streamSize = 4, 333 ageWidth = 4, 334 blockBytes = L2BlockSize, 335 reallocStreamOnMissInstantly = true, 336 cacheName = "dcache" 337 ), 338 bopParams = BOPParameters( 339 rrTableEntries = 256, 340 rrTagBits = 12, 341 scoreBits = 5, 342 roundMax = 50, 343 badScore = 1, 344 blockBytes = L2BlockSize, 345 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 346 ), 347 ) 348 349 // load violation predict 350 val ResetTimeMax2Pow = 20 //1078576 351 val ResetTimeMin2Pow = 10 //1024 352 // wait table parameters 353 val WaitTableSize = 1024 354 val MemPredPCWidth = log2Up(WaitTableSize) 355 val LWTUse2BitCounter = true 356 // store set parameters 357 val SSITSize = WaitTableSize 358 val LFSTSize = 32 359 val SSIDWidth = log2Up(LFSTSize) 360 val LFSTWidth = 4 361 val StoreSetEnable = true // LWT will be disabled if SS is enabled 362 363 val loadExuConfigs = coreParams.loadExuConfigs 364 val storeExuConfigs = coreParams.storeExuConfigs 365 366 val intExuConfigs = coreParams.intExuConfigs 367 368 val fpExuConfigs = coreParams.fpExuConfigs 369 370 val exuConfigs = coreParams.exuConfigs 371 372} 373