xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 4d586ba1add0efc1317683a0227d24dbe6a5a8d2) 
1package xiangshan
2
3import chipsalliance.rocketchip.config.{Field, Parameters}
4import chisel3._
5import chisel3.util._
6import xiangshan.backend.exu._
7import xiangshan.backend.fu._
8import xiangshan.backend.fu.fpu._
9import xiangshan.backend.dispatch.DispatchParameters
10import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters}
11import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
12
13case object XSCoreParamsKey extends Field[XSCoreParameters]
14
15case class XSCoreParameters
16(
17  HasPrefetch: Boolean = false,
18  HartId: Int = 0,
19  XLEN: Int = 64,
20  HasMExtension: Boolean = true,
21  HasCExtension: Boolean = true,
22  HasDiv: Boolean = true,
23  HasICache: Boolean = true,
24  HasDCache: Boolean = true,
25  AddrBits: Int = 64,
26  VAddrBits: Int = 39,
27  PAddrBits: Int = 40,
28  HasFPU: Boolean = true,
29  FetchWidth: Int = 8,
30  EnableBPU: Boolean = true,
31  EnableBPD: Boolean = true,
32  EnableRAS: Boolean = true,
33  EnableLB: Boolean = false,
34  EnableLoop: Boolean = true,
35  EnableSC: Boolean = true,
36  EnbaleTlbDebug: Boolean = false,
37  EnableJal: Boolean = false,
38  EnableUBTB: Boolean = true,
39  HistoryLength: Int = 64,
40  BtbSize: Int = 2048,
41  JbtacSize: Int = 1024,
42  JbtacBanks: Int = 8,
43  RasSize: Int = 16,
44  CacheLineSize: Int = 512,
45  UBtbWays: Int = 16,
46  BtbWays: Int = 2,
47
48  EnableL1plusPrefetcher: Boolean = true,
49  IBufSize: Int = 48,
50  DecodeWidth: Int = 6,
51  RenameWidth: Int = 6,
52  CommitWidth: Int = 6,
53  BrqSize: Int = 32,
54  FtqSize: Int = 48,
55  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
56  IssQueSize: Int = 16,
57  NRPhyRegs: Int = 160,
58  NRIntReadPorts: Int = 14,
59  NRIntWritePorts: Int = 8,
60  NRFpReadPorts: Int = 14,
61  NRFpWritePorts: Int = 8,
62  LoadQueueSize: Int = 64,
63  StoreQueueSize: Int = 48,
64  RoqSize: Int = 192,
65  dpParams: DispatchParameters = DispatchParameters(
66    IntDqSize = 16,
67    FpDqSize = 16,
68    LsDqSize = 16,
69    IntDqDeqWidth = 4,
70    FpDqDeqWidth = 4,
71    LsDqDeqWidth = 4
72  ),
73  exuParameters: ExuParameters = ExuParameters(
74    JmpCnt = 1,
75    AluCnt = 4,
76    MulCnt = 0,
77    MduCnt = 2,
78    FmacCnt = 4,
79    FmiscCnt = 2,
80    FmiscDivSqrtCnt = 0,
81    LduCnt = 2,
82    StuCnt = 2
83  ),
84  LoadPipelineWidth: Int = 2,
85  StorePipelineWidth: Int = 2,
86  StoreBufferSize: Int = 16,
87  StoreBufferThreshold: Int = 7,
88  RefillSize: Int = 512,
89  TlbEntrySize: Int = 32,
90  TlbSPEntrySize: Int = 4,
91  PtwL3EntrySize: Int = 4096, //(256 * 16) or 512
92  PtwSPEntrySize: Int = 16,
93  PtwL1EntrySize: Int = 16,
94  PtwL2EntrySize: Int = 2048, //(256 * 8)
95  PtwMissQueueSize: Int = 8,
96  NumPerfCounters: Int = 16,
97  icacheParameters: ICacheParameters = ICacheParameters(
98    tagECC = Some("parity"),
99    dataECC = Some("parity"),
100    replacer = Some("setplru"),
101    nMissEntries = 2
102  ),
103  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
104    tagECC = Some("secded"),
105    dataECC = Some("secded"),
106    replacer = Some("setplru"),
107    nMissEntries = 8
108  ),
109  dcacheParameters: DCacheParameters = DCacheParameters(
110    tagECC = Some("secded"),
111    dataECC = Some("secded"),
112    replacer = Some("setplru"),
113    nMissEntries = 16,
114    nProbeEntries = 16,
115    nReleaseEntries = 16,
116    nStoreReplayEntries = 16
117  ),
118  L2Size: Int = 512 * 1024, // 512KB
119  L2NWays: Int = 8,
120  useFakePTW: Boolean = false,
121  useFakeDCache: Boolean = false,
122  useFakeL1plusCache: Boolean = false,
123  useFakeL2Cache: Boolean = false
124){
125  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
126  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg)
127
128  val intExuConfigs = JumpExeUnitCfg +: (
129    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++
130      Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg)
131    )
132
133  val fpExuConfigs =
134    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
135      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
136
137  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
138}
139
140case object DebugOptionsKey extends Field[DebugOptions]
141
142case class DebugOptions
143(
144  FPGAPlatform: Boolean = true,
145  EnableDebug: Boolean = true,
146  EnablePerfDebug: Boolean = true,
147  UseDRAMSim: Boolean = false
148)
149
150trait HasXSParameter {
151
152  implicit val p: Parameters
153
154  val coreParams = p(XSCoreParamsKey)
155  val env = p(DebugOptionsKey)
156
157  val XLEN = coreParams.XLEN
158  val hardId = coreParams.HartId
159  val minFLen = 32
160  val fLen = 64
161  def xLen = XLEN
162
163  val HasMExtension = coreParams.HasMExtension
164  val HasCExtension = coreParams.HasCExtension
165  val HasDiv = coreParams.HasDiv
166  val HasIcache = coreParams.HasICache
167  val HasDcache = coreParams.HasDCache
168  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
169  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
170  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
171  val AddrBytes = AddrBits / 8 // unused
172  val DataBits = XLEN
173  val DataBytes = DataBits / 8
174  val HasFPU = coreParams.HasFPU
175  val FetchWidth = coreParams.FetchWidth
176  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
177  val EnableBPU = coreParams.EnableBPU
178  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
179  val EnableRAS = coreParams.EnableRAS
180  val EnableLB = coreParams.EnableLB
181  val EnableLoop = coreParams.EnableLoop
182  val EnableSC = coreParams.EnableSC
183  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
184  val HistoryLength = coreParams.HistoryLength
185  val BtbSize = coreParams.BtbSize
186  // val BtbWays = 4
187  val BtbBanks = PredictWidth
188  // val BtbSets = BtbSize / BtbWays
189  val JbtacSize = coreParams.JbtacSize
190  val JbtacBanks = coreParams.JbtacBanks
191  val RasSize = coreParams.RasSize
192  val CacheLineSize = coreParams.CacheLineSize
193  val CacheLineHalfWord = CacheLineSize / 16
194  val ExtHistoryLength = HistoryLength + 64
195  val UBtbWays = coreParams.UBtbWays
196  val BtbWays = coreParams.BtbWays
197  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
198  val IBufSize = coreParams.IBufSize
199  val DecodeWidth = coreParams.DecodeWidth
200  val RenameWidth = coreParams.RenameWidth
201  val CommitWidth = coreParams.CommitWidth
202  val BrqSize = coreParams.BrqSize
203  val FtqSize = coreParams.FtqSize
204  val IssQueSize = coreParams.IssQueSize
205  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
206  val BrTagWidth = log2Up(BrqSize)
207  val NRPhyRegs = coreParams.NRPhyRegs
208  val PhyRegIdxWidth = log2Up(NRPhyRegs)
209  val RoqSize = coreParams.RoqSize
210  val LoadQueueSize = coreParams.LoadQueueSize
211  val StoreQueueSize = coreParams.StoreQueueSize
212  val dpParams = coreParams.dpParams
213  val exuParameters = coreParams.exuParameters
214  val NRIntReadPorts = coreParams.NRIntReadPorts
215  val NRIntWritePorts = coreParams.NRIntWritePorts
216  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
217  val NRFpReadPorts = coreParams.NRFpReadPorts
218  val NRFpWritePorts = coreParams.NRFpWritePorts
219  val LoadPipelineWidth = coreParams.LoadPipelineWidth
220  val StorePipelineWidth = coreParams.StorePipelineWidth
221  val StoreBufferSize = coreParams.StoreBufferSize
222  val StoreBufferThreshold = coreParams.StoreBufferThreshold
223  val RefillSize = coreParams.RefillSize
224  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
225  val TlbEntrySize = coreParams.TlbEntrySize
226  val TlbSPEntrySize = coreParams.TlbSPEntrySize
227  val PtwL3EntrySize = coreParams.PtwL3EntrySize
228  val PtwSPEntrySize = coreParams.PtwSPEntrySize
229  val PtwL1EntrySize = coreParams.PtwL1EntrySize
230  val PtwL2EntrySize = coreParams.PtwL2EntrySize
231  val PtwMissQueueSize = coreParams.PtwMissQueueSize
232  val NumPerfCounters = coreParams.NumPerfCounters
233
234  val instBytes = if (HasCExtension) 2 else 4
235  val instOffsetBits = log2Ceil(instBytes)
236
237  val icacheParameters = coreParams.icacheParameters
238  val l1plusCacheParameters = coreParams.l1plusCacheParameters
239  val dcacheParameters = coreParams.dcacheParameters
240
241  val LRSCCycles = 100
242
243
244  // cache hierarchy configurations
245  val l1BusDataWidth = 256
246
247  val useFakeDCache = coreParams.useFakeDCache
248  val useFakePTW = coreParams.useFakePTW
249  val useFakeL1plusCache = coreParams.useFakeL1plusCache
250  // L2 configurations
251  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
252  val L1BusWidth = 256
253  val L2Size = coreParams.L2Size
254  val L2BlockSize = 64
255  val L2NWays = coreParams.L2NWays
256  val L2NSets = L2Size / L2BlockSize / L2NWays
257
258  // L3 configurations
259  val L2BusWidth = 256
260
261  // icache prefetcher
262  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
263    enable = true,
264    _type = "stream",
265    streamParams = StreamPrefetchParameters(
266      streamCnt = 2,
267      streamSize = 4,
268      ageWidth = 4,
269      blockBytes = l1plusCacheParameters.blockBytes,
270      reallocStreamOnMissInstantly = true,
271      cacheName = "icache"
272    )
273  )
274
275  // dcache prefetcher
276  val l2PrefetcherParameters = L2PrefetcherParameters(
277    enable = true,
278    _type = "bop", // "stream" or "bop"
279    streamParams = StreamPrefetchParameters(
280      streamCnt = 4,
281      streamSize = 4,
282      ageWidth = 4,
283      blockBytes = L2BlockSize,
284      reallocStreamOnMissInstantly = true,
285      cacheName = "dcache"
286    ),
287    bopParams = BOPParameters(
288      rrTableEntries = 256,
289      rrTagBits = 12,
290      scoreBits = 5,
291      roundMax = 50,
292      badScore = 1,
293      blockBytes = L2BlockSize,
294      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
295    ),
296  )
297
298  // load violation predict
299  val ResetTimeMax2Pow = 20 //1078576
300  val ResetTimeMin2Pow = 10 //1024
301  // wait table parameters
302  val WaitTableSize = 1024
303  val MemPredPCWidth = log2Up(WaitTableSize)
304  val LWTUse2BitCounter = true
305  // store set parameters
306  val SSITSize = WaitTableSize
307  val LFSTSize = 32
308  val SSIDWidth = log2Up(LFSTSize)
309  val LFSTWidth = 4
310  val StoreSetEnable = true // LWT will be disabled if SS is enabled
311
312  val loadExuConfigs = coreParams.loadExuConfigs
313  val storeExuConfigs = coreParams.storeExuConfigs
314
315  val intExuConfigs = coreParams.intExuConfigs
316
317  val fpExuConfigs = coreParams.fpExuConfigs
318
319  val exuConfigs = coreParams.exuConfigs
320
321}
322