lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict

lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict when compare SSID

* fix store data wakeup logic

Co-authored-by: Lyn <[email protected]>

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vector: add VImacU wrapper and configs

Decode: merge DecodeUnitComplex to DecodeUnitComp

VldIssue: backend support Vld issue

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitSt

lsu, mdp: using sq based SSID comparison instead of LFST (#2081)

This commit provides MDP adaptation for #2077

* fix mdp: disable LFST, ssing ssid comparison instead of LFST

* add loadWaitStrict when compare SSID

* fix store data wakeup logic

Co-authored-by: Lyn <[email protected]>

show more ...

Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu

# Conflicts:
# .gitmodules
# build.sc
# src/main/scala/top/Configs.scala
# src/main/scala/xiangshan/Bundle.scala
# src/

Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu

# Conflicts:
# .gitmodules
# build.sc
# src/main/scala/top/Configs.scala
# src/main/scala/xiangshan/Bundle.scala
# src/main/scala/xiangshan/Parameters.scala
# src/main/scala/xiangshan/XSCore.scala
# src/main/scala/xiangshan/backend/CtrlBlock.scala
# src/main/scala/xiangshan/backend/MemBlock.scala
# src/main/scala/xiangshan/backend/Scheduler.scala
# src/main/scala/xiangshan/backend/issue/ReservationStation.scala
# src/main/scala/xiangshan/backend/issue/StatusArray.scala
# src/main/scala/xiangshan/backend/rob/Rob.scala
# src/main/scala/xiangshan/mem/MemCommon.scala
# src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
# src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
# src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
# src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
# src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

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Merge coupledL2 into master (#2064)

* icache: Acquire -> Get to L2

* gitmodules: add coupledL2 as submodule

* cpl2: merge coupledL2 into master

* Changes includes:
* coupledL2 integratio

Merge coupledL2 into master (#2064)

* icache: Acquire -> Get to L2

* gitmodules: add coupledL2 as submodule

* cpl2: merge coupledL2 into master

* Changes includes:
* coupledL2 integration
* modify user&echo fields in i$/d$/ptw
* set d$ never always-releasedata
* remove hw perfcnt connection for L2

* bump utility

* icache: remove unused releaseUnit

* config: minimalconfig includes l2

* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem

* bump Utility

* bump coupledL2: fix bugs in dual-core

* bump coupledL2

* icache: set icache as non-coherent node

* bump coupledL2: fix dirty problem in L2 ProbeAckData

---------

Co-authored-by: guohongyu <[email protected]>
Co-authored-by: XiChen <[email protected]>

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bpu: history checker switch and code style

backend: update VfRD to avoid conflict with vconfig read port

vector: fix vconfig idx

vector: add VIAluFix wrapper and related parameters

lsu: split lq for larger ooo load window (#2077)

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay qu

lsu: split lq for larger ooo load window (#2077)

BREAKING CHANGE: new LSU/LQ architecture introduced in this PR

In this commit, we replace unified LQ with:
* virtual load queue
* load replay queue
* load rar queue
* load raw queue
* uncache buffer

It will provide larger ooo load window.

NOTE: IPC loss in this commit is caused by MDP problems, for previous MDP
does not fit new LSU architecture.
MDP update is not included in this commit, IPC loss will be fixed by MDP update later.

---------

Co-authored-by: Lyn <[email protected]>

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Merge pull request #2060 from Guo-HY/fdip-icache-migrate

ICache FDIP migrate

Merge branch 'dev-vector' into new-backend

backend: refactor vset and add rab support

Fix constant (#2071)

* constant: fix dead loop

* util: fix constant dynamic switch

* util: fix constant

isa-riscv,vector: add bundles and convert function

* Add class VType, VConfig
* Add object VSew, VLmul

add vset support

Co-authored-by: zhanglyGit <[email protected]>
Co-authored-by: Xuan Hu <[email protected]>

func(UopDivType): support VEC_RGATHER/VEC_RGATHER_VX/VEC_RGATHEREI16 of UopDivType

func(UopDivType): support VEC_VWW of UopDivType

atomic: support atomic instruction

backend: fix merge master error

Merge remote-tracking branch 'upstream/master' into new-backend

ICache : fix compile error & make itlb and pmp port num more configurable