1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 34 35import scala.math.min 36 37case object XSTileKey extends Field[Seq[XSCoreParameters]] 38 39case object XSCoreParamsKey extends Field[XSCoreParameters] 40 41case class XSCoreParameters 42( 43 HasPrefetch: Boolean = false, 44 HartId: Int = 0, 45 XLEN: Int = 64, 46 HasMExtension: Boolean = true, 47 HasCExtension: Boolean = true, 48 HasDiv: Boolean = true, 49 HasICache: Boolean = true, 50 HasDCache: Boolean = true, 51 AddrBits: Int = 64, 52 VAddrBits: Int = 39, 53 HasFPU: Boolean = true, 54 HasCustomCSRCacheOp: Boolean = true, 55 FetchWidth: Int = 8, 56 AsidLength: Int = 16, 57 EnableBPU: Boolean = true, 58 EnableBPD: Boolean = true, 59 EnableRAS: Boolean = true, 60 EnableLB: Boolean = false, 61 EnableLoop: Boolean = true, 62 EnableSC: Boolean = true, 63 EnbaleTlbDebug: Boolean = false, 64 EnableJal: Boolean = false, 65 EnableFauFTB: Boolean = true, 66 UbtbGHRLength: Int = 4, 67 // HistoryLength: Int = 512, 68 EnableGHistDiff: Boolean = true, 69 EnableCommitGHistDiff: Boolean = true, 70 UbtbSize: Int = 256, 71 FtbSize: Int = 2048, 72 RasSize: Int = 32, 73 CacheLineSize: Int = 512, 74 FtbWays: Int = 4, 75 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 76 // Sets Hist Tag 77 // Seq(( 2048, 2, 8), 78 // ( 2048, 9, 8), 79 // ( 2048, 13, 8), 80 // ( 2048, 20, 8), 81 // ( 2048, 26, 8), 82 // ( 2048, 44, 8), 83 // ( 2048, 73, 8), 84 // ( 2048, 256, 8)), 85 Seq(( 4096, 8, 8), 86 ( 4096, 13, 8), 87 ( 4096, 32, 8), 88 ( 4096, 119, 8)), 89 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 90 // Sets Hist Tag 91 Seq(( 256, 4, 9), 92 ( 256, 8, 9), 93 ( 512, 13, 9), 94 ( 512, 16, 9), 95 ( 512, 32, 9)), 96 SCNRows: Int = 512, 97 SCNTables: Int = 4, 98 SCCtrBits: Int = 6, 99 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 100 numBr: Int = 2, 101 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 102 ((resp_in: BranchPredictionResp, p: Parameters) => { 103 val ftb = Module(new FTB()(p)) 104 val ubtb =Module(new FauFTB()(p)) 105 // val bim = Module(new BIM()(p)) 106 val tage = Module(new Tage_SC()(p)) 107 val ras = Module(new RAS()(p)) 108 val ittage = Module(new ITTage()(p)) 109 val preds = Seq(ubtb, tage, ftb, ittage, ras) 110 preds.map(_.io := DontCare) 111 112 // ubtb.io.resp_in(0) := resp_in 113 // bim.io.resp_in(0) := ubtb.io.resp 114 // btb.io.resp_in(0) := bim.io.resp 115 // tage.io.resp_in(0) := btb.io.resp 116 // loop.io.resp_in(0) := tage.io.resp 117 ubtb.io.in.bits.resp_in(0) := resp_in 118 tage.io.in.bits.resp_in(0) := ubtb.io.out 119 ftb.io.in.bits.resp_in(0) := tage.io.out 120 ittage.io.in.bits.resp_in(0) := ftb.io.out 121 ras.io.in.bits.resp_in(0) := ittage.io.out 122 123 (preds, ras.io.out) 124 }), 125 IBufSize: Int = 48, 126 DecodeWidth: Int = 6, 127 RenameWidth: Int = 6, 128 CommitWidth: Int = 6, 129 FtqSize: Int = 64, 130 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 131 IssQueSize: Int = 16, 132 NRPhyRegs: Int = 192, 133 VirtualLoadQueueSize: Int = 80, 134 LoadQueueRARSize: Int = 80, 135 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 136 RollbackGroupSize: Int = 8, 137 LoadQueueReplaySize: Int = 80, 138 LoadUncacheBufferSize: Int = 20, 139 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 140 StoreQueueSize: Int = 64, 141 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 142 StoreQueueForwardWithMask: Boolean = true, 143 VlsQueueSize: Int = 8, 144 RobSize: Int = 256, 145 dpParams: DispatchParameters = DispatchParameters( 146 IntDqSize = 16, 147 FpDqSize = 16, 148 LsDqSize = 16, 149 IntDqDeqWidth = 4, 150 FpDqDeqWidth = 4, 151 LsDqDeqWidth = 4 152 ), 153 exuParameters: ExuParameters = ExuParameters( 154 JmpCnt = 1, 155 AluCnt = 4, 156 MulCnt = 0, 157 MduCnt = 2, 158 FmacCnt = 4, 159 FmiscCnt = 2, 160 FmiscDivSqrtCnt = 0, 161 LduCnt = 2, 162 StuCnt = 2 163 ), 164 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 165 LoadPipelineWidth: Int = 2, 166 StorePipelineWidth: Int = 2, 167 VecMemSrcInWidth: Int = 2, 168 VecMemInstWbWidth: Int = 1, 169 VecMemDispatchWidth: Int = 1, 170 StoreBufferSize: Int = 16, 171 StoreBufferThreshold: Int = 7, 172 EnsbufferWidth: Int = 2, 173 UncacheBufferSize: Int = 4, 174 EnableLoadToLoadForward: Boolean = true, 175 EnableFastForward: Boolean = false, 176 EnableLdVioCheckAfterReset: Boolean = true, 177 EnableSoftPrefetchAfterReset: Boolean = true, 178 EnableCacheErrorAfterReset: Boolean = true, 179 EnableDCacheWPU: Boolean = false, 180 EnableAccurateLoadError: Boolean = true, 181 EnableUncacheWriteOutstanding: Boolean = false, 182 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 183 ReSelectLen: Int = 7, // load replay queue replay select counter len 184 itlbParameters: TLBParameters = TLBParameters( 185 name = "itlb", 186 fetchi = true, 187 useDmode = false, 188 normalNWays = 32, 189 normalReplacer = Some("plru"), 190 superNWays = 4, 191 superReplacer = Some("plru") 192 ), 193 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 194 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 195 ldtlbParameters: TLBParameters = TLBParameters( 196 name = "ldtlb", 197 normalNSets = 64, 198 normalNWays = 1, 199 normalAssociative = "sa", 200 normalReplacer = Some("setplru"), 201 superNWays = 16, 202 normalAsVictim = true, 203 outReplace = false, 204 partialStaticPMP = true, 205 outsideRecvFlush = true, 206 saveLevel = true 207 ), 208 sttlbParameters: TLBParameters = TLBParameters( 209 name = "sttlb", 210 normalNSets = 64, 211 normalNWays = 1, 212 normalAssociative = "sa", 213 normalReplacer = Some("setplru"), 214 superNWays = 16, 215 normalAsVictim = true, 216 outReplace = false, 217 partialStaticPMP = true, 218 outsideRecvFlush = true, 219 saveLevel = true 220 ), 221 pftlbParameters: TLBParameters = TLBParameters( 222 name = "pftlb", 223 normalNSets = 64, 224 normalNWays = 1, 225 normalAssociative = "sa", 226 normalReplacer = Some("setplru"), 227 superNWays = 16, 228 normalAsVictim = true, 229 outReplace = false, 230 partialStaticPMP = true, 231 outsideRecvFlush = true, 232 saveLevel = true 233 ), 234 refillBothTlb: Boolean = false, 235 btlbParameters: TLBParameters = TLBParameters( 236 name = "btlb", 237 normalNSets = 1, 238 normalNWays = 64, 239 superNWays = 4, 240 ), 241 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 242 NumPerfCounters: Int = 16, 243 icacheParameters: ICacheParameters = ICacheParameters( 244 tagECC = Some("parity"), 245 dataECC = Some("parity"), 246 replacer = Some("setplru"), 247 nMissEntries = 2, 248 nProbeEntries = 2, 249 nPrefetchEntries = 12, 250 nPrefBufferEntries = 64, 251 hasPrefetch = true, 252 ), 253 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 254 tagECC = Some("secded"), 255 dataECC = Some("secded"), 256 replacer = Some("setplru"), 257 nMissEntries = 16, 258 nProbeEntries = 8, 259 nReleaseEntries = 18 260 )), 261 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 262 name = "l2", 263 level = 2, 264 ways = 8, 265 sets = 1024, // default 512KB L2 266 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 267 )), 268 L2NBanks: Int = 1, 269 usePTWRepeater: Boolean = false, 270 softTLB: Boolean = false, // dpi-c l1tlb debug only 271 softPTW: Boolean = false, // dpi-c l2tlb debug only 272 softPTWDelay: Int = 1 273){ 274 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 275 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 276 277 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 278 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 279 280 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 281 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 282 283 val fpExuConfigs = 284 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 285 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 286 287 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 288} 289 290case object DebugOptionsKey extends Field[DebugOptions] 291 292case class DebugOptions 293( 294 FPGAPlatform: Boolean = false, 295 EnableDifftest: Boolean = false, 296 AlwaysBasicDiff: Boolean = true, 297 EnableDebug: Boolean = false, 298 EnablePerfDebug: Boolean = true, 299 UseDRAMSim: Boolean = false, 300 EnableConstantin: Boolean = false, 301 EnableTopDown: Boolean = false 302) 303 304trait HasXSParameter { 305 306 implicit val p: Parameters 307 308 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 309 310 val coreParams = p(XSCoreParamsKey) 311 val env = p(DebugOptionsKey) 312 313 val XLEN = coreParams.XLEN 314 val minFLen = 32 315 val fLen = 64 316 def xLen = XLEN 317 318 val HasMExtension = coreParams.HasMExtension 319 val HasCExtension = coreParams.HasCExtension 320 val HasDiv = coreParams.HasDiv 321 val HasIcache = coreParams.HasICache 322 val HasDcache = coreParams.HasDCache 323 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 324 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 325 val AsidLength = coreParams.AsidLength 326 val ReSelectLen = coreParams.ReSelectLen 327 val AddrBytes = AddrBits / 8 // unused 328 val DataBits = XLEN 329 val DataBytes = DataBits / 8 330 val HasFPU = coreParams.HasFPU 331 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 332 val FetchWidth = coreParams.FetchWidth 333 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 334 val EnableBPU = coreParams.EnableBPU 335 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 336 val EnableRAS = coreParams.EnableRAS 337 val EnableLB = coreParams.EnableLB 338 val EnableLoop = coreParams.EnableLoop 339 val EnableSC = coreParams.EnableSC 340 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 341 val HistoryLength = coreParams.HistoryLength 342 val EnableGHistDiff = coreParams.EnableGHistDiff 343 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 344 val UbtbGHRLength = coreParams.UbtbGHRLength 345 val UbtbSize = coreParams.UbtbSize 346 val EnableFauFTB = coreParams.EnableFauFTB 347 val FtbSize = coreParams.FtbSize 348 val FtbWays = coreParams.FtbWays 349 val RasSize = coreParams.RasSize 350 351 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 352 coreParams.branchPredictor(resp_in, p) 353 } 354 val numBr = coreParams.numBr 355 val TageTableInfos = coreParams.TageTableInfos 356 val TageBanks = coreParams.numBr 357 val SCNRows = coreParams.SCNRows 358 val SCCtrBits = coreParams.SCCtrBits 359 val SCHistLens = coreParams.SCHistLens 360 val SCNTables = coreParams.SCNTables 361 362 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 363 case ((n, cb), h) => (n, cb, h) 364 } 365 val ITTageTableInfos = coreParams.ITTageTableInfos 366 type FoldedHistoryInfo = Tuple2[Int, Int] 367 val foldedGHistInfos = 368 (TageTableInfos.map{ case (nRows, h, t) => 369 if (h > 0) 370 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 371 else 372 Set[FoldedHistoryInfo]() 373 }.reduce(_++_).toSet ++ 374 SCTableInfos.map{ case (nRows, _, h) => 375 if (h > 0) 376 Set((h, min(log2Ceil(nRows/TageBanks), h))) 377 else 378 Set[FoldedHistoryInfo]() 379 }.reduce(_++_).toSet ++ 380 ITTageTableInfos.map{ case (nRows, h, t) => 381 if (h > 0) 382 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 383 else 384 Set[FoldedHistoryInfo]() 385 }.reduce(_++_) ++ 386 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 387 ).toList 388 389 390 391 val CacheLineSize = coreParams.CacheLineSize 392 val CacheLineHalfWord = CacheLineSize / 16 393 val ExtHistoryLength = HistoryLength + 64 394 val IBufSize = coreParams.IBufSize 395 val DecodeWidth = coreParams.DecodeWidth 396 val RenameWidth = coreParams.RenameWidth 397 val CommitWidth = coreParams.CommitWidth 398 val FtqSize = coreParams.FtqSize 399 val IssQueSize = coreParams.IssQueSize 400 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 401 val NRPhyRegs = coreParams.NRPhyRegs 402 val PhyRegIdxWidth = log2Up(NRPhyRegs) 403 val RobSize = coreParams.RobSize 404 val IntRefCounterWidth = log2Ceil(RobSize) 405 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 406 val LoadQueueRARSize = coreParams.LoadQueueRARSize 407 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 408 val RollbackGroupSize = coreParams.RollbackGroupSize 409 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 410 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 411 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 412 val StoreQueueSize = coreParams.StoreQueueSize 413 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 414 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 415 val VlsQueueSize = coreParams.VlsQueueSize 416 val dpParams = coreParams.dpParams 417 val exuParameters = coreParams.exuParameters 418 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 419 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 420 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 421 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 422 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 423 val LoadPipelineWidth = coreParams.LoadPipelineWidth 424 val StorePipelineWidth = coreParams.StorePipelineWidth 425 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 426 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 427 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 428 val StoreBufferSize = coreParams.StoreBufferSize 429 val StoreBufferThreshold = coreParams.StoreBufferThreshold 430 val EnsbufferWidth = coreParams.EnsbufferWidth 431 val UncacheBufferSize = coreParams.UncacheBufferSize 432 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 433 val EnableFastForward = coreParams.EnableFastForward 434 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 435 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 436 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 437 val EnableDCacheWPU = coreParams.EnableDCacheWPU 438 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 439 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 440 val asidLen = coreParams.MMUAsidLen 441 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 442 val refillBothTlb = coreParams.refillBothTlb 443 val itlbParams = coreParams.itlbParameters 444 val ldtlbParams = coreParams.ldtlbParameters 445 val sttlbParams = coreParams.sttlbParameters 446 val pftlbParams = coreParams.pftlbParameters 447 val btlbParams = coreParams.btlbParameters 448 val l2tlbParams = coreParams.l2tlbParameters 449 val NumPerfCounters = coreParams.NumPerfCounters 450 451 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 452 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 453 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 454 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 455 456 val instBytes = if (HasCExtension) 2 else 4 457 val instOffsetBits = log2Ceil(instBytes) 458 459 val icacheParameters = coreParams.icacheParameters 460 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 461 462 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 463 // for constrained LR/SC loop 464 val LRSCCycles = 64 465 // for lr storm 466 val LRSCBackOff = 8 467 468 // cache hierarchy configurations 469 val l1BusDataWidth = 256 470 471 // load violation predict 472 val ResetTimeMax2Pow = 20 //1078576 473 val ResetTimeMin2Pow = 10 //1024 474 // wait table parameters 475 val WaitTableSize = 1024 476 val MemPredPCWidth = log2Up(WaitTableSize) 477 val LWTUse2BitCounter = true 478 // store set parameters 479 val SSITSize = WaitTableSize 480 val LFSTSize = 32 481 val SSIDWidth = log2Up(LFSTSize) 482 val LFSTWidth = 4 483 val StoreSetEnable = true // LWT will be disabled if SS is enabled 484 val loadExuConfigs = coreParams.loadExuConfigs 485 val storeExuConfigs = coreParams.storeExuConfigs 486 487 val intExuConfigs = coreParams.intExuConfigs 488 489 val fpExuConfigs = coreParams.fpExuConfigs 490 491 val exuConfigs = coreParams.exuConfigs 492 493 val PCntIncrStep: Int = 6 494 val numPCntHc: Int = 25 495 val numPCntPtw: Int = 19 496 497 val numCSRPCntFrontend = 8 498 val numCSRPCntCtrl = 8 499 val numCSRPCntLsu = 8 500 val numCSRPCntHc = 5 501} 502