1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend._ 35import xiangshan.frontend.icache.ICacheParameters 36 37import freechips.rocketchip.diplomacy.AddressSet 38import system.SoCParamsKey 39import huancun._ 40import huancun.debug._ 41import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 42 43import scala.math.min 44 45case object XSTileKey extends Field[Seq[XSCoreParameters]] 46 47case object XSCoreParamsKey extends Field[XSCoreParameters] 48 49case class XSCoreParameters 50( 51 HasPrefetch: Boolean = false, 52 HartId: Int = 0, 53 XLEN: Int = 64, 54 VLEN: Int = 128, 55 ELEN: Int = 64, 56 HasMExtension: Boolean = true, 57 HasCExtension: Boolean = true, 58 HasDiv: Boolean = true, 59 HasICache: Boolean = true, 60 HasDCache: Boolean = true, 61 AddrBits: Int = 64, 62 VAddrBits: Int = 39, 63 HasFPU: Boolean = true, 64 HasVPU: Boolean = true, 65 HasCustomCSRCacheOp: Boolean = true, 66 FetchWidth: Int = 8, 67 AsidLength: Int = 16, 68 EnableBPU: Boolean = true, 69 EnableBPD: Boolean = true, 70 EnableRAS: Boolean = true, 71 EnableLB: Boolean = false, 72 EnableLoop: Boolean = true, 73 EnableSC: Boolean = true, 74 EnbaleTlbDebug: Boolean = false, 75 EnableJal: Boolean = false, 76 EnableFauFTB: Boolean = true, 77 UbtbGHRLength: Int = 4, 78 // HistoryLength: Int = 512, 79 EnableGHistDiff: Boolean = true, 80 UbtbSize: Int = 256, 81 FtbSize: Int = 2048, 82 RasSize: Int = 32, 83 CacheLineSize: Int = 512, 84 FtbWays: Int = 4, 85 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 86 // Sets Hist Tag 87 // Seq(( 2048, 2, 8), 88 // ( 2048, 9, 8), 89 // ( 2048, 13, 8), 90 // ( 2048, 20, 8), 91 // ( 2048, 26, 8), 92 // ( 2048, 44, 8), 93 // ( 2048, 73, 8), 94 // ( 2048, 256, 8)), 95 Seq(( 4096, 8, 8), 96 ( 4096, 13, 8), 97 ( 4096, 32, 8), 98 ( 4096, 119, 8)), 99 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 100 // Sets Hist Tag 101 Seq(( 256, 4, 9), 102 ( 256, 8, 9), 103 ( 512, 13, 9), 104 ( 512, 16, 9), 105 ( 512, 32, 9)), 106 SCNRows: Int = 512, 107 SCNTables: Int = 4, 108 SCCtrBits: Int = 6, 109 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 110 numBr: Int = 2, 111 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 112 ((resp_in: BranchPredictionResp, p: Parameters) => { 113 val ftb = Module(new FTB()(p)) 114 val ubtb =Module(new FauFTB()(p)) 115 // val bim = Module(new BIM()(p)) 116 val tage = Module(new Tage_SC()(p)) 117 val ras = Module(new RAS()(p)) 118 val ittage = Module(new ITTage()(p)) 119 val preds = Seq(ubtb, tage, ftb, ittage, ras) 120 preds.map(_.io := DontCare) 121 122 // ubtb.io.resp_in(0) := resp_in 123 // bim.io.resp_in(0) := ubtb.io.resp 124 // btb.io.resp_in(0) := bim.io.resp 125 // tage.io.resp_in(0) := btb.io.resp 126 // loop.io.resp_in(0) := tage.io.resp 127 ubtb.io.in.bits.resp_in(0) := resp_in 128 tage.io.in.bits.resp_in(0) := ubtb.io.out 129 ftb.io.in.bits.resp_in(0) := tage.io.out 130 ittage.io.in.bits.resp_in(0) := ftb.io.out 131 ras.io.in.bits.resp_in(0) := ittage.io.out 132 133 (preds, ras.io.out) 134 }), 135 IBufSize: Int = 48, 136 DecodeWidth: Int = 6, 137 RenameWidth: Int = 6, 138 CommitWidth: Int = 6, 139 MaxUopSize: Int = 65, 140 FtqSize: Int = 64, 141 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 142 IntLogicRegs: Int = 32, 143 FpLogicRegs: Int = 33, 144 VecLogicRegs: Int = 47, 145 NRPhyRegs: Int = 192, 146 IntPhyRegs: Int = 192, 147 VfPhyRegs: Int = 192, 148 LoadQueueSize: Int = 80, 149 LoadQueueNWriteBanks: Int = 8, 150 StoreQueueSize: Int = 64, 151 StoreQueueNWriteBanks: Int = 8, 152 VlsQueueSize: Int = 8, 153 RobSize: Int = 256, 154 RabSize: Int = 256, 155 dpParams: DispatchParameters = DispatchParameters( 156 IntDqSize = 16, 157 FpDqSize = 16, 158 LsDqSize = 16, 159 IntDqDeqWidth = 6, 160 FpDqDeqWidth = 6, 161 LsDqDeqWidth = 6, 162 ), 163 intPreg: PregParams = IntPregParams( 164 numEntries = 64, 165 numRead = 14, 166 numWrite = 8, 167 ), 168 vfPreg: VfPregParams = VfPregParams( 169 numEntries = 64, 170 numRead = 14, 171 numWrite = 8, 172 ), 173 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 174 LoadPipelineWidth: Int = 2, 175 StorePipelineWidth: Int = 2, 176 VecMemSrcInWidth: Int = 2, 177 VecMemInstWbWidth: Int = 1, 178 VecMemDispatchWidth: Int = 1, 179 StoreBufferSize: Int = 16, 180 StoreBufferThreshold: Int = 7, 181 EnsbufferWidth: Int = 2, 182 UncacheBufferSize: Int = 4, 183 EnableLoadToLoadForward: Boolean = true, 184 EnableFastForward: Boolean = false, 185 EnableLdVioCheckAfterReset: Boolean = true, 186 EnableSoftPrefetchAfterReset: Boolean = true, 187 EnableCacheErrorAfterReset: Boolean = true, 188 EnableDCacheWPU: Boolean = false, 189 EnableAccurateLoadError: Boolean = true, 190 EnableUncacheWriteOutstanding: Boolean = false, 191 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 192 ReSelectLen: Int = 7, // load replay queue replay select counter len 193 itlbParameters: TLBParameters = TLBParameters( 194 name = "itlb", 195 fetchi = true, 196 useDmode = false, 197 normalNWays = 32, 198 normalReplacer = Some("plru"), 199 superNWays = 4, 200 superReplacer = Some("plru") 201 ), 202 ldtlbParameters: TLBParameters = TLBParameters( 203 name = "ldtlb", 204 normalNSets = 64, 205 normalNWays = 1, 206 normalAssociative = "sa", 207 normalReplacer = Some("setplru"), 208 superNWays = 16, 209 normalAsVictim = true, 210 outReplace = false, 211 partialStaticPMP = true, 212 outsideRecvFlush = true, 213 saveLevel = true 214 ), 215 sttlbParameters: TLBParameters = TLBParameters( 216 name = "sttlb", 217 normalNSets = 64, 218 normalNWays = 1, 219 normalAssociative = "sa", 220 normalReplacer = Some("setplru"), 221 superNWays = 16, 222 normalAsVictim = true, 223 outReplace = false, 224 partialStaticPMP = true, 225 outsideRecvFlush = true, 226 saveLevel = true 227 ), 228 pftlbParameters: TLBParameters = TLBParameters( 229 name = "pftlb", 230 normalNSets = 64, 231 normalNWays = 1, 232 normalAssociative = "sa", 233 normalReplacer = Some("setplru"), 234 superNWays = 16, 235 normalAsVictim = true, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 refillBothTlb: Boolean = false, 242 btlbParameters: TLBParameters = TLBParameters( 243 name = "btlb", 244 normalNSets = 1, 245 normalNWays = 64, 246 superNWays = 4, 247 ), 248 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 249 NumPerfCounters: Int = 16, 250 icacheParameters: ICacheParameters = ICacheParameters( 251 tagECC = Some("parity"), 252 dataECC = Some("parity"), 253 replacer = Some("setplru"), 254 nMissEntries = 2, 255 nProbeEntries = 2, 256 nPrefetchEntries = 2, 257 hasPrefetch = true, 258 ), 259 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 260 tagECC = Some("secded"), 261 dataECC = Some("secded"), 262 replacer = Some("setplru"), 263 nMissEntries = 16, 264 nProbeEntries = 8, 265 nReleaseEntries = 18 266 )), 267 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 268 name = "l2", 269 level = 2, 270 ways = 8, 271 sets = 1024, // default 512KB L2 272 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 273 )), 274 L2NBanks: Int = 1, 275 usePTWRepeater: Boolean = false, 276 softTLB: Boolean = false, // dpi-c l1tlb debug only 277 softPTW: Boolean = false, // dpi-c l2tlb debug only 278 softPTWDelay: Int = 1 279){ 280 def vlWidth = log2Up(VLEN) + 1 281 282 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 283 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 284 285 def intSchdParams = { 286 implicit val schdType: SchedulerType = IntScheduler() 287 val pregBits = intPreg.addrWidth 288 val numRfRead = intPreg.numRead 289 val numRfWrite = intPreg.numWrite 290 SchdBlockParams(Seq( 291 IssueBlockParams(Seq( 292 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 293 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 294 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 295 IssueBlockParams(Seq( 296 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 297 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 298 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 299 IssueBlockParams(Seq( 300 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 301 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 302 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 303 IssueBlockParams(Seq( 304 ExeUnitParams(Seq(I2fCfg, VSetRiWiCfg, VSetRiWvfCfg), Seq(VecWB(port = 6, Int.MaxValue), IntWB(port = 7, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 305 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 306 ), 307 numPregs = intPreg.numEntries, 308 numRfReadWrite = Some((numRfRead, numRfWrite)), 309 numDeqOutside = 0, 310 schdType = schdType, 311 rfDataWidth = intPreg.dataCfg.dataWidth, 312 numUopIn = dpParams.IntDqDeqWidth, 313 ) 314 } 315 def vfSchdParams = { 316 implicit val schdType: SchedulerType = VfScheduler() 317 val pregBits = vfPreg.addrWidth 318 val numRfRead = vfPreg.numRead 319 val numRfWrite = vfPreg.numWrite 320 SchdBlockParams(Seq( 321 IssueBlockParams(Seq( 322 ExeUnitParams(Seq(VialuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 323 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 324 IssueBlockParams(Seq( 325 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 326 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 327 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 328 ), 329 numPregs = vfPreg.numEntries, 330 numRfReadWrite = Some((numRfRead, numRfWrite)), 331 numDeqOutside = 0, 332 schdType = schdType, 333 rfDataWidth = vfPreg.dataCfg.dataWidth, 334 numUopIn = dpParams.FpDqDeqWidth, 335 ) 336 } 337 def memSchdParams = { 338 implicit val schdType: SchedulerType = MemScheduler() 339 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 340 val rfDataWidth = 64 341 342 SchdBlockParams(Seq( 343 IssueBlockParams(Seq( 344 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 345 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 346 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 347 IssueBlockParams(Seq( 348 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 349 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 350 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 351 IssueBlockParams(Seq( 352 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 353 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 354 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 355 ), 356 numPregs = intPreg.numEntries max vfPreg.numEntries, 357 numRfReadWrite = None, 358 numDeqOutside = 0, 359 schdType = schdType, 360 rfDataWidth = rfDataWidth, 361 numUopIn = dpParams.LsDqDeqWidth, 362 ) 363 } 364 365 def backendParams: BackendParams = backend.BackendParams(Map( 366 IntScheduler() -> intSchdParams, 367 VfScheduler() -> vfSchdParams, 368 MemScheduler() -> memSchdParams, 369 ), Seq( 370 intPreg, 371 vfPreg, 372 )) 373} 374 375case object DebugOptionsKey extends Field[DebugOptions] 376 377case class DebugOptions 378( 379 FPGAPlatform: Boolean = false, 380 EnableDifftest: Boolean = false, 381 AlwaysBasicDiff: Boolean = true, 382 EnableDebug: Boolean = false, 383 EnablePerfDebug: Boolean = true, 384 UseDRAMSim: Boolean = false, 385 EnableTopDown: Boolean = false 386) 387 388trait HasXSParameter { 389 390 implicit val p: Parameters 391 392 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 393 394 val coreParams = p(XSCoreParamsKey) 395 val env = p(DebugOptionsKey) 396 397 val XLEN = coreParams.XLEN 398 val VLEN = coreParams.VLEN 399 val ELEN = coreParams.ELEN 400 val minFLen = 32 401 val fLen = 64 402 def xLen = XLEN 403 404 val HasMExtension = coreParams.HasMExtension 405 val HasCExtension = coreParams.HasCExtension 406 val HasDiv = coreParams.HasDiv 407 val HasIcache = coreParams.HasICache 408 val HasDcache = coreParams.HasDCache 409 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 410 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 411 val AsidLength = coreParams.AsidLength 412 val ReSelectLen = coreParams.ReSelectLen 413 val AddrBytes = AddrBits / 8 // unused 414 val DataBits = XLEN 415 val DataBytes = DataBits / 8 416 val HasFPU = coreParams.HasFPU 417 val HasVPU = coreParams.HasVPU 418 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 419 val FetchWidth = coreParams.FetchWidth 420 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 421 val EnableBPU = coreParams.EnableBPU 422 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 423 val EnableRAS = coreParams.EnableRAS 424 val EnableLB = coreParams.EnableLB 425 val EnableLoop = coreParams.EnableLoop 426 val EnableSC = coreParams.EnableSC 427 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 428 val HistoryLength = coreParams.HistoryLength 429 val EnableGHistDiff = coreParams.EnableGHistDiff 430 val UbtbGHRLength = coreParams.UbtbGHRLength 431 val UbtbSize = coreParams.UbtbSize 432 val EnableFauFTB = coreParams.EnableFauFTB 433 val FtbSize = coreParams.FtbSize 434 val FtbWays = coreParams.FtbWays 435 val RasSize = coreParams.RasSize 436 437 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 438 coreParams.branchPredictor(resp_in, p) 439 } 440 val numBr = coreParams.numBr 441 val TageTableInfos = coreParams.TageTableInfos 442 val TageBanks = coreParams.numBr 443 val SCNRows = coreParams.SCNRows 444 val SCCtrBits = coreParams.SCCtrBits 445 val SCHistLens = coreParams.SCHistLens 446 val SCNTables = coreParams.SCNTables 447 448 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 449 case ((n, cb), h) => (n, cb, h) 450 } 451 val ITTageTableInfos = coreParams.ITTageTableInfos 452 type FoldedHistoryInfo = Tuple2[Int, Int] 453 val foldedGHistInfos = 454 (TageTableInfos.map{ case (nRows, h, t) => 455 if (h > 0) 456 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 457 else 458 Set[FoldedHistoryInfo]() 459 }.reduce(_++_).toSet ++ 460 SCTableInfos.map{ case (nRows, _, h) => 461 if (h > 0) 462 Set((h, min(log2Ceil(nRows/TageBanks), h))) 463 else 464 Set[FoldedHistoryInfo]() 465 }.reduce(_++_).toSet ++ 466 ITTageTableInfos.map{ case (nRows, h, t) => 467 if (h > 0) 468 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 469 else 470 Set[FoldedHistoryInfo]() 471 }.reduce(_++_) ++ 472 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 473 ).toList 474 475 476 477 val CacheLineSize = coreParams.CacheLineSize 478 val CacheLineHalfWord = CacheLineSize / 16 479 val ExtHistoryLength = HistoryLength + 64 480 val IBufSize = coreParams.IBufSize 481 val DecodeWidth = coreParams.DecodeWidth 482 val RenameWidth = coreParams.RenameWidth 483 val CommitWidth = coreParams.CommitWidth 484 val MaxUopSize = coreParams.MaxUopSize 485 val FtqSize = coreParams.FtqSize 486 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 487 val IntLogicRegs = coreParams.IntLogicRegs 488 val FpLogicRegs = coreParams.FpLogicRegs 489 val VecLogicRegs = coreParams.VecLogicRegs 490 val NRPhyRegs = coreParams.NRPhyRegs 491 val PhyRegIdxWidth = log2Up(NRPhyRegs) 492 val IntPhyRegs = coreParams.IntPhyRegs 493 val VfPhyRegs = coreParams.VfPhyRegs 494 val IntPregIdxWidth = log2Up(IntPhyRegs) 495 val VfPregIdxWidth = log2Up(VfPhyRegs) 496 val RobSize = coreParams.RobSize 497 val RabSize = coreParams.RabSize 498 val IntRefCounterWidth = log2Ceil(RobSize) 499 val LoadQueueSize = coreParams.LoadQueueSize 500 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 501 val StoreQueueSize = coreParams.StoreQueueSize 502 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 503 val VlsQueueSize = coreParams.VlsQueueSize 504 val dpParams = coreParams.dpParams 505 506 def backendParams: BackendParams = coreParams.backendParams 507 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 508 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 509 val LoadPipelineWidth = coreParams.LoadPipelineWidth 510 val StorePipelineWidth = coreParams.StorePipelineWidth 511 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 512 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 513 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 514 val StoreBufferSize = coreParams.StoreBufferSize 515 val StoreBufferThreshold = coreParams.StoreBufferThreshold 516 val EnsbufferWidth = coreParams.EnsbufferWidth 517 val UncacheBufferSize = coreParams.UncacheBufferSize 518 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 519 val EnableFastForward = coreParams.EnableFastForward 520 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 521 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 522 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 523 val EnableDCacheWPU = coreParams.EnableDCacheWPU 524 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 525 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 526 val asidLen = coreParams.MMUAsidLen 527 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 528 val refillBothTlb = coreParams.refillBothTlb 529 val itlbParams = coreParams.itlbParameters 530 val ldtlbParams = coreParams.ldtlbParameters 531 val sttlbParams = coreParams.sttlbParameters 532 val pftlbParams = coreParams.pftlbParameters 533 val btlbParams = coreParams.btlbParameters 534 val l2tlbParams = coreParams.l2tlbParameters 535 val NumPerfCounters = coreParams.NumPerfCounters 536 537 val instBytes = if (HasCExtension) 2 else 4 538 val instOffsetBits = log2Ceil(instBytes) 539 540 val icacheParameters = coreParams.icacheParameters 541 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 542 543 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 544 // for constrained LR/SC loop 545 val LRSCCycles = 64 546 // for lr storm 547 val LRSCBackOff = 8 548 549 // cache hierarchy configurations 550 val l1BusDataWidth = 256 551 552 // load violation predict 553 val ResetTimeMax2Pow = 20 //1078576 554 val ResetTimeMin2Pow = 10 //1024 555 // wait table parameters 556 val WaitTableSize = 1024 557 val MemPredPCWidth = log2Up(WaitTableSize) 558 val LWTUse2BitCounter = true 559 // store set parameters 560 val SSITSize = WaitTableSize 561 val LFSTSize = 32 562 val SSIDWidth = log2Up(LFSTSize) 563 val LFSTWidth = 4 564 val StoreSetEnable = true // LWT will be disabled if SS is enabled 565 566 val PCntIncrStep: Int = 6 567 val numPCntHc: Int = 25 568 val numPCntPtw: Int = 19 569 570 val numCSRPCntFrontend = 8 571 val numCSRPCntCtrl = 8 572 val numCSRPCntLsu = 8 573 val numCSRPCntHc = 5 574} 575