Searched full:divider (Results 1 – 20 of 20) sorted by relevance
131 /* DDR clock divider register(DDCDR) */146 /*MACPHY clock divider Register (MACCDR)*/154 /* I2S device clock divider register(I2SCDR) */164 /* I2S device clock divider register(I2SCDR1) */170 /* LCD pix clock divider register(LPCDR) */181 /* MSC clock divider register(MSCCDR) */195 /* OTG PHY clock divider register(USBCDR) */205 /* SSI clock divider register(SSICDR) */214 /* CIM mclk clock divider register(CIMCDR) */225 /* PCM device clock divider register(PCMCDR) */[all …]
186 /* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */
153 #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */209 #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */218 #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */442 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */446 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */447 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */448 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */455 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */456 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */457 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */[all …]
161 PMC_DIV EQU (0xFF<<0) ; PLL Divider165 PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider179 ;// <o2.0..7> DIV: PLL Divider <0-255>186 ;// <o2.28..29> USBDIV: USB Clock Divider
158 PMC_DIV EQU (0xFF<<0) ; PLL Divider162 PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider176 ;// <o2.0..7> DIV: PLL Divider <0-255>183 ;// <o2.28..29> USBDIV: USB Clock Divider
129 CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset130 CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset139 ;// <o2.12..19> m: Main Divider m Value <9-256><#-8>141 ;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>143 ;// <o2.0..1> s: Post Divider s Value <0-3>148 ;// <o3.12..19> m: Main Divider m Value <8-263><#-8>150 ;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>152 ;// <o3.0..1> s: Post Divider s Value <0-3>180 ;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7>182 ;// <h> Clock Divider Control Register (CLKDIVN)[all …]
25 /* System clock divider FCLK:HCLK:PCLK=1:4:8 */
57 .equ CLKDIVN, 0x4c000014 /*Clock divider control */
103 #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control104 #define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
49 .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */51 …x00000024 /* <o1.0..4> MSEL: PLL Multiplier Selection,<o1.5..6> PSEL: PLL Divider Selection */
117 PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider124 ;// <o1.5..6> PSEL: PLL Divider Selection
108 /* VPB Divider */
38 /* Cycle counter divider */
131 CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset132 USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset172 ;// <o3.16..23> NSEL: PLL Divider Selection1193 ; Setup CPU clock divider1197 ; Setup USB clock divider
383 Phase Locked Loop, VPB divider, Power Control, External Interrupt, 402 /* Clock Divider */
158 ;// <o1.12..19> MDIV: Main divider <0x0-0xFF>160 ;// <o1.4..9> PDIV: Pre-divider <0x0-0x3F>162 ;// <o1.0..1> SDIV: Post Divider <0x0-0x03>173 ;// <o3.0..3> SLOW_VAL: Slow Clock divider <0x0-0x0F>
143 option allows specifying a divider, i.e. how many intervals
94 * @brief QSPI frequency divider values.
1393 // <o> NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider.