1;/* 2; * Copyright (c) 2006-2018, RT-Thread Development Team 3; * 4; * SPDX-License-Identifier: Apache-2.0 5; * 6; * Change Logs: 7; * Date Author Notes 8; */ 9; 10;/*****************************************************************************/ 11;/* LPC2400.S: Startup file for Philips LPC2400 device series */ 12;/*****************************************************************************/ 13;/* <<< Use Configuration Wizard in Context Menu >>> */ 14;/*****************************************************************************/ 15;/* This file is part of the uVision/ARM development tools. */ 16;/* Copyright (c) 2007-2008 Keil - An ARM Company. All rights reserved. */ 17;/* This software may only be used under the terms of a valid, current, */ 18;/* end user licence from KEIL for a compatible version of KEIL software */ 19;/* development tools. Nothing else gives you the right to use this software. */ 20;/*****************************************************************************/ 21 22;/* 23; * The LPC2400.S code is executed after CPU Reset. This file may be 24; * translated with the following SET symbols. In uVision these SET 25; * symbols are entered under Options - ASM - Define. 26; * 27; * NO_CLOCK_SETUP: when set the startup code will not initialize Clock 28; * (used mostly when clock is already initialized from script .ini 29; * file). 30; * 31; * NO_EMC_SETUP: when set the startup code will not initialize 32; * External Bus Controller. 33; * 34; * RAM_INTVEC: when set the startup code copies exception vectors 35; * from on-chip Flash to on-chip RAM. 36; * 37; * REMAP: when set the startup code initializes the register MEMMAP 38; * which overwrites the settings of the CPU configuration pins. The 39; * startup and interrupt vectors are remapped from: 40; * 0x00000000 default setting (not remapped) 41; * 0x40000000 when RAM_MODE is used 42; * 0x80000000 when EXTMEM_MODE is used 43; * 44; * EXTMEM_MODE: when set the device is configured for code execution 45; * from external memory starting at address 0x80000000. 46; * 47; * RAM_MODE: when set the device is configured for code execution 48; * from on-chip RAM starting at address 0x40000000. 49; */ 50 51 52; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs 53 54Mode_USR EQU 0x10 55Mode_FIQ EQU 0x11 56Mode_IRQ EQU 0x12 57Mode_SVC EQU 0x13 58Mode_ABT EQU 0x17 59Mode_UND EQU 0x1B 60Mode_SYS EQU 0x1F 61I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 62F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 63 64;----------------------- Memory Definitions ------------------------------------ 65 66; Internal Memory Base Addresses 67FLASH_BASE EQU 0x00000000 68RAM_BASE EQU 0x40000000 69EXTMEM_BASE EQU 0x80000000 70 71; External Memory Base Addresses 72STA_MEM0_BASE EQU 0x80000000 73STA_MEM1_BASE EQU 0x81000000 74STA_MEM2_BASE EQU 0x82000000 75STA_MEM3_BASE EQU 0x83000000 76DYN_MEM0_BASE EQU 0xA0000000 77DYN_MEM1_BASE EQU 0xB0000000 78DYN_MEM2_BASE EQU 0xC0000000 79DYN_MEM3_BASE EQU 0xD0000000 80 81 82;----------------------- Stack and Heap Definitions ---------------------------- 83 84;// <h> Stack Configuration (Stack Sizes in Bytes) 85;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> 86;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> 87;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> 88;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> 89;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> 90;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> 91;// </h> 92 93UND_Stack_Size EQU 0x00000000 94SVC_Stack_Size EQU 0x00000100 95ABT_Stack_Size EQU 0x00000000 96FIQ_Stack_Size EQU 0x00000000 97IRQ_Stack_Size EQU 0x00000100 98USR_Stack_Size EQU 0x00000100 99 100ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ 101 FIQ_Stack_Size + IRQ_Stack_Size) 102 103 AREA STACK, NOINIT, READWRITE, ALIGN=3 104 105Stack_Mem SPACE USR_Stack_Size 106__initial_sp SPACE ISR_Stack_Size 107 108Stack_Top 109 110 111;// <h> Heap Configuration 112;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> 113;// </h> 114 115Heap_Size EQU 0x00000000 116 117 AREA HEAP, NOINIT, READWRITE, ALIGN=3 118__heap_base 119Heap_Mem SPACE Heap_Size 120__heap_limit 121 122 123;----------------------- Clock Definitions ------------------------------------- 124 125; System Control Block (SCB) Module Definitions 126SCB_BASE EQU 0xE01FC000 ; SCB Base Address 127PLLCON_OFS EQU 0x80 ; PLL Control Offset 128PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset 129PLLSTAT_OFS EQU 0x88 ; PLL Status Offset 130PLLFEED_OFS EQU 0x8C ; PLL Feed Offset 131CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset 132USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset 133CLKSRCSEL_OFS EQU 0x10C ; Clock Source Sel Reg Offset 134SCS_OFS EQU 0x1A0 ; Sys Control and Status Reg Offset 135PCLKSEL0_OFS EQU 0x1A8 ; Periph Clock Sel Reg 0 Offset 136PCLKSEL1_OFS EQU 0x1AC ; Periph Clock Sel Reg 0 Offset 137 138PCON_OFS EQU 0x0C0 ; Power Mode Control Reg Offset 139PCONP_OFS EQU 0x0C4 ; Power Control for Periphs Reg Offset 140 141; Constants 142OSCRANGE EQU (1<<4) ; Oscillator Range Select 143OSCEN EQU (1<<5) ; Main oscillator Enable 144OSCSTAT EQU (1<<6) ; Main Oscillator Status 145PLLCON_PLLE EQU (1<<0) ; PLL Enable 146PLLCON_PLLC EQU (1<<1) ; PLL Connect 147PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value 148PLLSTAT_N EQU (0xFF<<16) ; PLL N Value 149PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status 150 151;// <e> Clock Setup 152;// <h> System Controls and Status Register (SYS) 153;// <o1.4> OSCRANGE: Main Oscillator Range Select 154;// <0=> 1 MHz to 20 MHz 155;// <1=> 15 MHz to 24 MHz 156;// <e1.5> OSCEN: Main Oscillator Enable 157;// </e> 158;// </h> 159;// 160;// <h> PLL Clock Source Select Register (CLKSRCSEL) 161;// <o2.0..1> CLKSRC: PLL Clock Source Selection 162;// <0=> Internal RC oscillator 163;// <1=> Main oscillator 164;// <2=> RTC oscillator 165;// </h> 166;// 167;// <h> PLL Configuration Register (PLLCFG) 168;// <i> PLL_clk = (2* M * PLL_clk_src) / N 169;// <o3.0..14> MSEL: PLL Multiplier Selection 170;// <1-32768><#-1> 171;// <i> M Value 172;// <o3.16..23> NSEL: PLL Divider Selection 173;// <1-256><#-1> 174;// <i> N Value 175;// </h> 176;// 177;// <h> CPU Clock Configuration Register (CCLKCFG) 178;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL 179;// <1-256><#-1> 180;// </h> 181;// 182;// <h> USB Clock Configuration Register (USBCLKCFG) 183;// <o5.0..3> USBSEL: Divide Value for USB Clock from PLL 184;// <1-16><#-1> 185;// </h> 186;// 187;// <h> Peripheral Clock Selection Register 0 (PCLKSEL0) 188;// <o6.0..1> PCLK_WDT: Peripheral Clock Selection for WDT 189;// <0=> Pclk = Cclk / 4 190;// <1=> Pclk = Cclk 191;// <2=> Pclk = Cclk / 2 192;// <3=> Pclk = Cclk / 8 193;// <o6.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 194;// <0=> Pclk = Cclk / 4 195;// <1=> Pclk = Cclk 196;// <2=> Pclk = Cclk / 2 197;// <3=> Pclk = Cclk / 8 198;// <o6.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 199;// <0=> Pclk = Cclk / 4 200;// <1=> Pclk = Cclk 201;// <2=> Pclk = Cclk / 2 202;// <3=> Pclk = Cclk / 8 203;// <o6.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 204;// <0=> Pclk = Cclk / 4 205;// <1=> Pclk = Cclk 206;// <2=> Pclk = Cclk / 2 207;// <3=> Pclk = Cclk / 8 208;// <o6.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 209;// <0=> Pclk = Cclk / 4 210;// <1=> Pclk = Cclk 211;// <2=> Pclk = Cclk / 2 212;// <3=> Pclk = Cclk / 8 213;// <o6.10..11> PCLK_PWM0: Peripheral Clock Selection for PWM0 214;// <0=> Pclk = Cclk / 4 215;// <1=> Pclk = Cclk 216;// <2=> Pclk = Cclk / 2 217;// <3=> Pclk = Cclk / 8 218;// <o6.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 219;// <0=> Pclk = Cclk / 4 220;// <1=> Pclk = Cclk 221;// <2=> Pclk = Cclk / 2 222;// <3=> Pclk = Cclk / 8 223;// <o6.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 224;// <0=> Pclk = Cclk / 4 225;// <1=> Pclk = Cclk 226;// <2=> Pclk = Cclk / 2 227;// <3=> Pclk = Cclk / 8 228;// <o6.16..17> PCLK_SPI: Peripheral Clock Selection for SPI 229;// <0=> Pclk = Cclk / 4 230;// <1=> Pclk = Cclk 231;// <2=> Pclk = Cclk / 2 232;// <3=> Pclk = Cclk / 8 233;// <o6.18..19> PCLK_RTC: Peripheral Clock Selection for RTC 234;// <0=> Pclk = Cclk / 4 235;// <1=> Pclk = Cclk 236;// <2=> Pclk = Cclk / 2 237;// <3=> Pclk = Cclk / 8 238;// <o6.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 239;// <0=> Pclk = Cclk / 4 240;// <1=> Pclk = Cclk 241;// <2=> Pclk = Cclk / 2 242;// <3=> Pclk = Cclk / 8 243;// <o6.22..23> PCLK_DAC: Peripheral Clock Selection for DAC 244;// <0=> Pclk = Cclk / 4 245;// <1=> Pclk = Cclk 246;// <2=> Pclk = Cclk / 2 247;// <3=> Pclk = Cclk / 8 248;// <o6.24..25> PCLK_ADC: Peripheral Clock Selection for ADC 249;// <0=> Pclk = Cclk / 4 250;// <1=> Pclk = Cclk 251;// <2=> Pclk = Cclk / 2 252;// <3=> Pclk = Cclk / 8 253;// <o6.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 254;// <0=> Pclk = Cclk / 4 255;// <1=> Pclk = Cclk 256;// <2=> Pclk = Cclk / 2 257;// <3=> Pclk = Cclk / 6 258;// <o6.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 259;// <0=> Pclk = Cclk / 4 260;// <1=> Pclk = Cclk 261;// <2=> Pclk = Cclk / 2 262;// <3=> Pclk = Cclk / 6 263;// <o6.30..31> PCLK_ACF: Peripheral Clock Selection for ACF 264;// <0=> Pclk = Cclk / 4 265;// <1=> Pclk = Cclk 266;// <2=> Pclk = Cclk / 2 267;// <3=> Pclk = Cclk / 6 268;// </h> 269;// 270;// <h> Peripheral Clock Selection Register 1 (PCLKSEL1) 271;// <o7.0..1> PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM 272;// <0=> Pclk = Cclk / 4 273;// <1=> Pclk = Cclk 274;// <2=> Pclk = Cclk / 2 275;// <3=> Pclk = Cclk / 8 276;// <o7.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs 277;// <0=> Pclk = Cclk / 4 278;// <1=> Pclk = Cclk 279;// <2=> Pclk = Cclk / 2 280;// <3=> Pclk = Cclk / 8 281;// <o7.4..5> PCLK_PCB: Peripheral Clock Selection for Pin Connect Block 282;// <0=> Pclk = Cclk / 4 283;// <1=> Pclk = Cclk 284;// <2=> Pclk = Cclk / 2 285;// <3=> Pclk = Cclk / 8 286;// <o7.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 287;// <0=> Pclk = Cclk / 4 288;// <1=> Pclk = Cclk 289;// <2=> Pclk = Cclk / 2 290;// <3=> Pclk = Cclk / 8 291;// <o7.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 292;// <0=> Pclk = Cclk / 4 293;// <1=> Pclk = Cclk 294;// <2=> Pclk = Cclk / 2 295;// <3=> Pclk = Cclk / 8 296;// <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 297;// <0=> Pclk = Cclk / 4 298;// <1=> Pclk = Cclk 299;// <2=> Pclk = Cclk / 2 300;// <3=> Pclk = Cclk / 8 301;// <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 302;// <0=> Pclk = Cclk / 4 303;// <1=> Pclk = Cclk 304;// <2=> Pclk = Cclk / 2 305;// <3=> Pclk = Cclk / 8 306;// <o7.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 307;// <0=> Pclk = Cclk / 4 308;// <1=> Pclk = Cclk 309;// <2=> Pclk = Cclk / 2 310;// <3=> Pclk = Cclk / 8 311;// <o7.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 312;// <0=> Pclk = Cclk / 4 313;// <1=> Pclk = Cclk 314;// <2=> Pclk = Cclk / 2 315;// <3=> Pclk = Cclk / 8 316;// <o7.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 317;// <0=> Pclk = Cclk / 4 318;// <1=> Pclk = Cclk 319;// <2=> Pclk = Cclk / 2 320;// <3=> Pclk = Cclk / 8 321;// <o7.22..23> PCLK_I2S: Peripheral Clock Selection for I2S 322;// <0=> Pclk = Cclk / 4 323;// <1=> Pclk = Cclk 324;// <2=> Pclk = Cclk / 2 325;// <3=> Pclk = Cclk / 8 326;// <o7.24..25> PCLK_MCI: Peripheral Clock Selection for MCI 327;// <0=> Pclk = Cclk / 4 328;// <1=> Pclk = Cclk 329;// <2=> Pclk = Cclk / 2 330;// <3=> Pclk = Cclk / 8 331;// <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block 332;// <0=> Pclk = Cclk / 4 333;// <1=> Pclk = Cclk 334;// <2=> Pclk = Cclk / 2 335;// <3=> Pclk = Cclk / 8 336;// </h> 337;// </e> 338CLOCK_SETUP EQU 1 339SCS_Val EQU 0x00000020 340CLKSRCSEL_Val EQU 0x00000001 341PLLCFG_Val EQU 0x0000000B 342CCLKCFG_Val EQU 0x00000004 343USBCLKCFG_Val EQU 0x00000005 344PCLKSEL0_Val EQU 0x00000000 345PCLKSEL1_Val EQU 0x00000000 346 347 348;----------------------- Memory Accelerator Module (MAM) Definitions ----------- 349 350MAM_BASE EQU 0xE01FC000 ; MAM Base Address 351MAMCR_OFS EQU 0x00 ; MAM Control Offset 352MAMTIM_OFS EQU 0x04 ; MAM Timing Offset 353 354;// <e> MAM Setup 355;// <o1.0..1> MAM Control 356;// <0=> Disabled 357;// <1=> Partially Enabled 358;// <2=> Fully Enabled 359;// <i> Mode 360;// <o2.0..2> MAM Timing 361;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 362;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 363;// <i> Fetch Cycles 364;// </e> 365MAM_SETUP EQU 1 366MAMCR_Val EQU 0x00000002 367MAMTIM_Val EQU 0x00000004 368 369 370;----------------------- Pin Connect Block Definitions ------------------------- 371 372PCB_BASE EQU 0xE002C000 ; PCB Base Address 373PINSEL0_OFS EQU 0x00 ; PINSEL0 Address Offset 374PINSEL1_OFS EQU 0x04 ; PINSEL1 Address Offset 375PINSEL2_OFS EQU 0x08 ; PINSEL2 Address Offset 376PINSEL3_OFS EQU 0x0C ; PINSEL3 Address Offset 377PINSEL4_OFS EQU 0x10 ; PINSEL4 Address Offset 378PINSEL5_OFS EQU 0x14 ; PINSEL5 Address Offset 379PINSEL6_OFS EQU 0x18 ; PINSEL6 Address Offset 380PINSEL7_OFS EQU 0x1C ; PINSEL7 Address Offset 381PINSEL8_OFS EQU 0x20 ; PINSEL8 Address Offset 382PINSEL9_OFS EQU 0x24 ; PINSEL9 Address Offset 383PINSEL10_OFS EQU 0x28 ; PINSEL10 Address Offset 384 385 386;----------------------- External Memory Controller (EMC) Definitons ----------- 387 388EMC_BASE EQU 0xFFE08000 ; EMC Base Address 389 390EMC_CTRL_OFS EQU 0x000 391EMC_STAT_OFS EQU 0x004 392EMC_CONFIG_OFS EQU 0x008 393EMC_DYN_CTRL_OFS EQU 0x020 394EMC_DYN_RFSH_OFS EQU 0x024 395EMC_DYN_RD_CFG_OFS EQU 0x028 396EMC_DYN_RP_OFS EQU 0x030 397EMC_DYN_RAS_OFS EQU 0x034 398EMC_DYN_SREX_OFS EQU 0x038 399EMC_DYN_APR_OFS EQU 0x03C 400EMC_DYN_DAL_OFS EQU 0x040 401EMC_DYN_WR_OFS EQU 0x044 402EMC_DYN_RC_OFS EQU 0x048 403EMC_DYN_RFC_OFS EQU 0x04C 404EMC_DYN_XSR_OFS EQU 0x050 405EMC_DYN_RRD_OFS EQU 0x054 406EMC_DYN_MRD_OFS EQU 0x058 407EMC_DYN_CFG0_OFS EQU 0x100 408EMC_DYN_RASCAS0_OFS EQU 0x104 409EMC_DYN_CFG1_OFS EQU 0x140 410EMC_DYN_RASCAS1_OFS EQU 0x144 411EMC_DYN_CFG2_OFS EQU 0x160 412EMC_DYN_RASCAS2_OFS EQU 0x164 413EMC_DYN_CFG3_OFS EQU 0x180 414EMC_DYN_RASCAS3_OFS EQU 0x184 415EMC_STA_CFG0_OFS EQU 0x200 416EMC_STA_WWEN0_OFS EQU 0x204 417EMC_STA_WOEN0_OFS EQU 0x208 418EMC_STA_WRD0_OFS EQU 0x20C 419EMC_STA_WPAGE0_OFS EQU 0x210 420EMC_STA_WWR0_OFS EQU 0x214 421EMC_STA_WTURN0_OFS EQU 0x218 422EMC_STA_CFG1_OFS EQU 0x220 423EMC_STA_WWEN1_OFS EQU 0x224 424EMC_STA_WOEN1_OFS EQU 0x228 425EMC_STA_WRD1_OFS EQU 0x22C 426EMC_STA_WPAGE1_OFS EQU 0x230 427EMC_STA_WWR1_OFS EQU 0x234 428EMC_STA_WTURN1_OFS EQU 0x238 429EMC_STA_CFG2_OFS EQU 0x240 430EMC_STA_WWEN2_OFS EQU 0x244 431EMC_STA_WOEN2_OFS EQU 0x248 432EMC_STA_WRD2_OFS EQU 0x24C 433EMC_STA_WPAGE2_OFS EQU 0x250 434EMC_STA_WWR2_OFS EQU 0x254 435EMC_STA_WTURN2_OFS EQU 0x258 436EMC_STA_CFG3_OFS EQU 0x260 437EMC_STA_WWEN3_OFS EQU 0x264 438EMC_STA_WOEN3_OFS EQU 0x268 439EMC_STA_WRD3_OFS EQU 0x26C 440EMC_STA_WPAGE3_OFS EQU 0x270 441EMC_STA_WWR3_OFS EQU 0x274 442EMC_STA_WTURN3_OFS EQU 0x278 443EMC_STA_EXT_W_OFS EQU 0x880 444 445; Constants 446NORMAL_CMD EQU (0x0 << 7) ; NORMAL Command 447MODE_CMD EQU (0x1 << 7) ; MODE Command 448PALL_CMD EQU (0x2 << 7) ; Precharge All Command 449NOP_CMD EQU (0x3 << 7) ; NOP Command 450 451BUFEN_Const EQU (1 << 19) ; Buffer enable bit 452EMC_PCONP_Const EQU (1 << 11) ; PCONP val to enable power for EMC 453 454; External Memory Pins definitions 455; pin functions for SDRAM, NOR and NAND flash interfacing 456EMC_PINSEL5_Val EQU 0x05010115 ; !CAS, !RAS, CLKOUT0, !DYCS0, DQMOUT0, DQMOUT1 457EMC_PINSEL6_Val EQU 0x55555555 ; D0 .. D15 458EMC_PINSEL8_Val EQU 0x55555555 ; A0 .. A15 459EMC_PINSEL9_Val EQU 0x50055555; ; A16 .. A23, !OE, !WE, !CS0, !CS1 460 461;// External Memory Controller Setup (EMC) --------------------------------- 462;// <e> External Memory Controller Setup (EMC) 463EMC_SETUP EQU 0 464 465;// <h> EMC Control Register (EMCControl) 466;// <i> Controls operation of the memory controller 467;// <o0.2> L: Low-power mode enable 468;// <o0.1> M: Address mirror enable 469;// <o0.0> E: EMC enable 470;// </h> 471EMC_CTRL_Val EQU 0x00000001 472 473;// <h> EMC Configuration Register (EMCConfig) 474;// <i> Configures operation of the memory controller 475;// <o0.8> CCLK: CLKOUT ratio 476;// <0=> 1:1 477;// <1=> 1:2 478;// <o0.0> Endian mode 479;// <0=> Little-endian 480;// <1=> Big-endian 481;// </h> 482EMC_CONFIG_Val EQU 0x00000000 483 484;// Dynamic Memory Interface Setup --------------------------------------- 485;// <e> Dynamic Memory Interface Setup 486EMC_DYNAMIC_SETUP EQU 1 487 488;// <h> Dynamic Memory Refresh Timer Register (EMCDynamicRefresh) 489;// <i> Configures dynamic memory refresh operation 490;// <o0.0..10> REFRESH: Refresh timer <0x000-0x7FF> 491;// <i> 0 = refresh disabled, 0x01-0x7FF: value * 16 CCLKS 492;// </h> 493EMC_DYN_RFSH_Val EQU 0x0000001C 494 495;// <h> Dynamic Memory Read Configuration Register (EMCDynamicReadConfig) 496;// <i> Configures the dynamic memory read strategy 497;// <o0.0..1> RD: Read data strategy 498;// <0=> Clock out delayed strategy 499;// <1=> Command delayed strategy 500;// <2=> Command delayed strategy plus one clock cycle 501;// <3=> Command delayed strategy plus two clock cycles 502;// </h> 503EMC_DYN_RD_CFG_Val EQU 0x00000001 504 505;// <h> Dynamic Memory Timings 506;// <h> Dynamic Memory Percentage Command Period Register (EMCDynamictRP) 507;// <o0.0..3> tRP: Precharge command period <1-16> <#-1> 508;// <i> The delay is in EMCCLK cycles 509;// <i> This value is normally found in SDRAM data sheets as tRP 510;// </h> 511;// <h> Dynamic Memory Active to Precharge Command Period Register (EMCDynamictRAS) 512;// <o1.0..3> tRAS: Active to precharge command period <1-16> <#-1> 513;// <i> The delay is in EMCCLK cycles 514;// <i> This value is normally found in SDRAM data sheets as tRAS 515;// </h> 516;// <h> Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX) 517;// <o2.0..3> tSREX: Self-refresh exit time <1-16> <#-1> 518;// <i> The delay is in CCLK cycles 519;// <i> This value is normally found in SDRAM data sheets as tSREX, 520;// <i> for devices without this parameter you use the same value as tXSR 521;// </h> 522;// <h> Dynamic Memory Last Data Out to Active Time Register (EMCDynamictAPR) 523;// <o3.0..3> tAPR: Last-data-out to active command time <1-16> <#-1> 524;// <i> The delay is in CCLK cycles 525;// <i> This value is normally found in SDRAM data sheets as tAPR 526;// </h> 527;// <h> Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL) 528;// <o4.0..3> tDAL: Data-in to active command time <1-16> <#-1> 529;// <i> The delay is in CCLK cycles 530;// <i> This value is normally found in SDRAM data sheets as tDAL or tAPW 531;// </h> 532;// <h> Dynamic Memory Write Recovery Time Register (EMCDynamictWR) 533;// <o5.0..3> tWR: Write recovery time <1-16> <#-1> 534;// <i> The delay is in CCLK cycles 535;// <i> This value is normally found in SDRAM data sheets as tWR, tDPL, tRWL, or tRDL 536;// </h> 537;// <h> Dynamic Memory Active to Active Command Period Register (EMCDynamictRC) 538;// <o6.0..4> tRC: Active to active command period <1-32> <#-1> 539;// <i> The delay is in CCLK cycles 540;// <i> This value is normally found in SDRAM data sheets as tRC 541;// </h> 542;// <h> Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC) 543;// <o7.0..4> tRFC: Auto-refresh period and auto-refresh to active command period <1-32> <#-1> 544;// <i> The delay is in CCLK cycles 545;// <i> This value is normally found in SDRAM data sheets as tRFC or tRC 546;// </h> 547;// <h> Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR) 548;// <o8.0..4> tXSR: Exit self-refresh to active command time <1-32> <#-1> 549;// <i> The delay is in CCLK cycles 550;// <i> This value is normally found in SDRAM data sheets as tXSR 551;// </h> 552;// <h> Dynamic Memory Active Bank A to Active Bank B Time Register (EMCDynamicRRD) 553;// <o9.0..3> tRRD: Active bank A to active bank B latency <1-16> <#-1> 554;// <i> The delay is in CCLK cycles 555;// <i> This value is normally found in SDRAM data sheets as tRRD 556;// </h> 557;// <h> Dynamic Memory Load Mode Register to Active Command Time (EMCDynamictMRD) 558;// <o10.0..3> tMRD: Load mode register to active command time <1-16> <#-1> 559;// <i> The delay is in CCLK cycles 560;// <i> This value is normally found in SDRAM data sheets as tMRD or tRSA 561;// </h> 562;// </h> 563EMC_DYN_RP_Val EQU 0x00000002 564EMC_DYN_RAS_Val EQU 0x00000003 565EMC_DYN_SREX_Val EQU 0x00000007 566EMC_DYN_APR_Val EQU 0x00000002 567EMC_DYN_DAL_Val EQU 0x00000005 568EMC_DYN_WR_Val EQU 0x00000001 569EMC_DYN_RC_Val EQU 0x00000005 570EMC_DYN_RFC_Val EQU 0x00000005 571EMC_DYN_XSR_Val EQU 0x00000007 572EMC_DYN_RRD_Val EQU 0x00000001 573EMC_DYN_MRD_Val EQU 0x00000002 574 575;// <e> Configure External Bus Behaviour for Dynamic CS0 Area 576EMC_DYNCS0_SETUP EQU 1 577 578;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig0) 579;// <i> Defines the configuration information for the dynamic memory CS0 580;// <o0.20> P: Write protect 581;// <o0.19> B: Buffer enable 582;// <o0.14> AM 14: External bus data width 583;// <0=> 16 bit 584;// <1=> 32 bit 585;// <o0.12> AM 12: External bus memory type 586;// <0=> High-performance 587;// <1=> Low-power SDRAM 588;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) 589;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 590;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 591;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 592;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 593;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 594;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 595;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 596;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 597;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 598;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 599;// <o0.3..4> MD: Memory device 600;// <0=> SDRAM 601;// <1=> Low-power SDRAM 602;// <2=> Micron SyncFlash 603;// </h> 604EMC_DYN_CFG0_Val EQU 0x00080680 605 606;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS0) 607;// <i> Controls the RAS and CAS latencies for the dynamic memory CS0 608;// <o0.8..9> CAS: CAS latency 609;// <1=> One CCLK cycle 610;// <2=> Two CCLK cycles 611;// <3=> Three CCLK cycles 612;// <o0.0..1> RAS: RAS latency (active to read/write delay) 613;// <1=> One CCLK cycle 614;// <2=> Two CCLK cycles 615;// <3=> Three CCLK cycles 616;// </h> 617EMC_DYN_RASCAS0_Val EQU 0x00000303 618 619;// </e> End of Dynamic Setup for CS0 Area 620 621 622;// <e> Configure External Bus Behaviour for Dynamic CS1 Area 623EMC_DYNCS1_SETUP EQU 0 624 625;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig1) 626;// <i> Defines the configuration information for the dynamic memory CS1 627;// <o0.20> P: Write protect 628;// <o0.19> B: Buffer enable 629;// <o0.14> AM 14: External bus data width 630;// <0=> 16 bit 631;// <1=> 32 bit 632;// <o0.12> AM 12: External bus memory type 633;// <0=> High-performance 634;// <1=> Low-power SDRAM 635;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) 636;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 637;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 638;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 639;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 640;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 641;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 642;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 643;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 644;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 645;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 646;// <o0.3..4> MD: Memory device 647;// <0=> SDRAM 648;// <1=> Low-power SDRAM 649;// <2=> Micron SyncFlash 650;// </h> 651EMC_DYN_CFG1_Val EQU 0x00000000 652 653;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1) 654;// <i> Controls the RAS and CAS latencies for the dynamic memory CS1 655;// <o0.8..9> CAS: CAS latency 656;// <1=> One CCLK cycle 657;// <2=> Two CCLK cycles 658;// <3=> Three CCLK cycles 659;// <o0.0..1> RAS: RAS latency (active to read/write delay) 660;// <1=> One CCLK cycle 661;// <2=> Two CCLK cycles 662;// <3=> Three CCLK cycles 663;// </h> 664EMC_DYN_RASCAS1_Val EQU 0x00000303 665 666;// </e> End of Dynamic Setup for CS1 Area 667 668;// <e> Configure External Bus Behaviour for Dynamic CS2 Area 669EMC_DYNCS2_SETUP EQU 0 670 671;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig2) 672;// <i> Defines the configuration information for the dynamic memory CS2 673;// <o0.20> P: Write protect 674;// <o0.19> B: Buffer enable 675;// <o0.14> AM 14: External bus data width 676;// <0=> 16 bit 677;// <1=> 32 bit 678;// <o0.12> AM 12: External bus memory type 679;// <0=> High-performance 680;// <1=> Low-power SDRAM 681;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) 682;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 683;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 684;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 685;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 686;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 687;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 688;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 689;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 690;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 691;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 692;// <o0.3..4> MD: Memory device 693;// <0=> SDRAM 694;// <1=> Low-power SDRAM 695;// <2=> Micron SyncFlash 696;// </h> 697EMC_DYN_CFG2_Val EQU 0x00000000 698 699;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS2) 700;// <i> Controls the RAS and CAS latencies for the dynamic memory CS2 701;// <o0.8..9> CAS: CAS latency 702;// <1=> One CCLK cycle 703;// <2=> Two CCLK cycles 704;// <3=> Three CCLK cycles 705;// <o0.0..1> RAS: RAS latency (active to read/write delay) 706;// <1=> One CCLK cycle 707;// <2=> Two CCLK cycles 708;// <3=> Three CCLK cycles 709;// </h> 710EMC_DYN_RASCAS2_Val EQU 0x00000303 711 712;// </e> End of Dynamic Setup for CS2 Area 713 714;// <e> Configure External Bus Behaviour for Dynamic CS3 Area 715EMC_DYNCS3_SETUP EQU 0 716 717;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig3) 718;// <i> Defines the configuration information for the dynamic memory CS3 719;// <o0.20> P: Write protect 720;// <o0.19> B: Buffer enable 721;// <o0.14> AM 14: External bus data width 722;// <0=> 16 bit 723;// <1=> 32 bit 724;// <o0.12> AM 12: External bus memory type 725;// <0=> High-performance 726;// <1=> Low-power SDRAM 727;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column) 728;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9 729;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8 730;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9 731;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8 732;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10 733;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9 734;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10 735;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9 736;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11 737;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10 738;// <o0.3..4> MD: Memory device 739;// <0=> SDRAM 740;// <1=> Low-power SDRAM 741;// <2=> Micron SyncFlash 742;// </h> 743EMC_DYN_CFG3_Val EQU 0x00000000 744 745;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS3) 746;// <i> Controls the RAS and CAS latencies for the dynamic memory CS3 747;// <o0.8..9> CAS: CAS latency 748;// <1=> One CCLK cycle 749;// <2=> Two CCLK cycles 750;// <3=> Three CCLK cycles 751;// <o0.0..1> RAS: RAS latency (active to read/write delay) 752;// <1=> One CCLK cycle 753;// <2=> Two CCLK cycles 754;// <3=> Three CCLK cycles 755;// </h> 756EMC_DYN_RASCAS3_Val EQU 0x00000303 757 758;// </e> End of Dynamic Setup for CS3 Area 759 760;// </e> End of Dynamic Setup 761 762;// Static Memory Interface Setup ---------------------------------------- 763;// <e> Static Memory Interface Setup 764EMC_STATIC_SETUP EQU 1 765 766;// Configure External Bus Behaviour for Static CS0 Area --------------- 767;// <e> Configure External Bus Behaviour for Static CS0 Area 768EMC_STACS0_SETUP EQU 1 769 770;// <h> Static Memory Configuration Register (EMCStaticConfig0) 771;// <i> Defines the configuration information for the static memory CS0 772;// <o0.20> WP: Write protect 773;// <o0.19> B: Buffer enable 774;// <o0.8> EW: Extended wait enable 775;// <o0.7> PB: Byte lane state 776;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW 777;// <1=> For reads BLSn are LOW, for writes BLSn are LOW 778;// <o0.6> PC: Chip select polarity 779;// <0=> Active LOW chip select 780;// <1=> Active HIGH chip select 781;// <o0.3> PM: Page mode enable 782;// <o0.0..1> MW: Memory width 783;// <0=> 8 bit 784;// <1=> 16 bit 785;// <2=> 32 bit 786;// </h> 787EMC_STA_CFG0_Val EQU 0x00000081 788 789;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0) 790;// <i> Selects the delay from CS0 to write enable 791;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> 792;// <i> The delay is in CCLK cycles 793;// </h> 794EMC_STA_WWEN0_Val EQU 0x00000002 795 796;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0) 797;// <i> Selects the delay from CS0 or address change, whichever is later, to output enable 798;// <o.0..3> WAITOEN: Wait output enable <0-15> 799;// <i> The delay is in CCLK cycles 800;// </h> 801EMC_STA_WOEN0_Val EQU 0x00000002 802 803;// <h> Static Memory Read Delay Register (EMCStaticWaitRd0) 804;// <i> Selects the delay from CS0 to a read access 805;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> 806;// <i> The delay is in CCLK cycles 807;// </h> 808EMC_STA_WRD0_Val EQU 0x0000001F 809 810;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) 811;// <i> Selects the delay for asynchronous page mode sequential accesses for CS0 812;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> 813;// <i> The delay is in CCLK cycles 814;// </h> 815EMC_STA_WPAGE0_Val EQU 0x0000001F 816 817;// <h> Static Memory Write Delay Register (EMCStaticWaitWr0) 818;// <i> Selects the delay from CS0 to a write access 819;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> 820;// <i> The delay is in CCLK cycles 821;// </h> 822EMC_STA_WWR0_Val EQU 0x0000001F 823 824;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0) 825;// <i> Selects the number of bus turnaround cycles for CS0 826;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> 827;// <i> The delay is in CCLK cycles 828;// </h> 829EMC_STA_WTURN0_Val EQU 0x0000000F 830 831;// </e> End of Static Setup for Static CS0 Area 832 833;// Configure External Bus Behaviour for Static CS1 Area --------------- 834;// <e> Configure External Bus Behaviour for Static CS1 Area 835EMC_STACS1_SETUP EQU 0 836 837;// <h> Static Memory Configuration Register (EMCStaticConfig1) 838;// <i> Defines the configuration information for the static memory CS1 839;// <o0.20> WP: Write protect 840;// <o0.19> B: Buffer enable 841;// <o0.8> EW: Extended wait enable 842;// <o0.7> PB: Byte lane state 843;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW 844;// <1=> For reads BLSn are LOW, for writes BLSn are LOW 845;// <o0.6> PC: Chip select polarity 846;// <0=> Active LOW chip select 847;// <1=> Active HIGH chip select 848;// <o0.3> PM: Page mode enable 849;// <o0.0..1> MW: Memory width 850;// <0=> 8 bit 851;// <1=> 16 bit 852;// <2=> 32 bit 853;// </h> 854EMC_STA_CFG1_Val EQU 0x00000000 855 856;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1) 857;// <i> Selects the delay from CS1 to write enable 858;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> 859;// <i> The delay is in CCLK cycles 860;// </h> 861EMC_STA_WWEN1_Val EQU 0x00000000 862 863;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1) 864;// <i> Selects the delay from CS1 or address change, whichever is later, to output enable 865;// <o.0..3> WAITOEN: Wait output enable <0-15> 866;// <i> The delay is in CCLK cycles 867;// </h> 868EMC_STA_WOEN1_Val EQU 0x00000000 869 870;// <h> Static Memory Read Delay Register (EMCStaticWaitRd1) 871;// <i> Selects the delay from CS1 to a read access 872;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> 873;// <i> The delay is in CCLK cycles 874;// </h> 875EMC_STA_WRD1_Val EQU 0x0000001F 876 877;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0) 878;// <i> Selects the delay for asynchronous page mode sequential accesses for CS1 879;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> 880;// <i> The delay is in CCLK cycles 881;// </h> 882EMC_STA_WPAGE1_Val EQU 0x0000001F 883 884;// <h> Static Memory Write Delay Register (EMCStaticWaitWr1) 885;// <i> Selects the delay from CS1 to a write access 886;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> 887;// <i> The delay is in CCLK cycles 888;// </h> 889EMC_STA_WWR1_Val EQU 0x0000001F 890 891;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1) 892;// <i> Selects the number of bus turnaround cycles for CS1 893;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> 894;// <i> The delay is in CCLK cycles 895;// </h> 896EMC_STA_WTURN1_Val EQU 0x0000000F 897 898;// </e> End of Static Setup for Static CS1 Area 899 900;// Configure External Bus Behaviour for Static CS2 Area --------------- 901;// <e> Configure External Bus Behaviour for Static CS2 Area 902EMC_STACS2_SETUP EQU 0 903 904;// <h> Static Memory Configuration Register (EMCStaticConfig2) 905;// <i> Defines the configuration information for the static memory CS2 906;// <o0.20> WP: Write protect 907;// <o0.19> B: Buffer enable 908;// <o0.8> EW: Extended wait enable 909;// <o0.7> PB: Byte lane state 910;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW 911;// <1=> For reads BLSn are LOW, for writes BLSn are LOW 912;// <o0.6> PC: Chip select polarity 913;// <0=> Active LOW chip select 914;// <1=> Active HIGH chip select 915;// <o0.3> PM: Page mode enable 916;// <o0.0..1> MW: Memory width 917;// <0=> 8 bit 918;// <1=> 16 bit 919;// <2=> 32 bit 920;// </h> 921EMC_STA_CFG2_Val EQU 0x00000000 922 923;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen2) 924;// <i> Selects the delay from CS2 to write enable 925;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> 926;// <i> The delay is in CCLK cycles 927;// </h> 928EMC_STA_WWEN2_Val EQU 0x00000000 929 930;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen2) 931;// <i> Selects the delay from CS2 or address change, whichever is later, to output enable 932;// <o.0..3> WAITOEN: Wait output enable <0-15> 933;// <i> The delay is in CCLK cycles 934;// </h> 935EMC_STA_WOEN2_Val EQU 0x00000000 936 937;// <h> Static Memory Read Delay Register (EMCStaticWaitRd2) 938;// <i> Selects the delay from CS2 to a read access 939;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> 940;// <i> The delay is in CCLK cycles 941;// </h> 942EMC_STA_WRD2_Val EQU 0x0000001F 943 944;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2) 945;// <i> Selects the delay for asynchronous page mode sequential accesses for CS2 946;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> 947;// <i> The delay is in CCLK cycles 948;// </h> 949EMC_STA_WPAGE2_Val EQU 0x0000001F 950 951;// <h> Static Memory Write Delay Register (EMCStaticWaitWr2) 952;// <i> Selects the delay from CS2 to a write access 953;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> 954;// <i> The delay is in CCLK cycles 955;// </h> 956EMC_STA_WWR2_Val EQU 0x0000001F 957 958;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn2) 959;// <i> Selects the number of bus turnaround cycles for CS2 960;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> 961;// <i> The delay is in CCLK cycles 962;// </h> 963EMC_STA_WTURN2_Val EQU 0x0000000F 964 965;// </e> End of Static Setup for Static CS2 Area 966 967;// Configure External Bus Behaviour for Static CS3 Area --------------- 968;// <e> Configure External Bus Behaviour for Static CS3 Area 969EMC_STACS3_SETUP EQU 0 970 971;// <h> Static Memory Configuration Register (EMCStaticConfig3) 972;// <i> Defines the configuration information for the static memory CS3 973;// <o0.20> WP: Write protect 974;// <o0.19> B: Buffer enable 975;// <o0.8> EW: Extended wait enable 976;// <o0.7> PB: Byte lane state 977;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW 978;// <1=> For reads BLSn are LOW, for writes BLSn are LOW 979;// <o0.6> PC: Chip select polarity 980;// <0=> Active LOW chip select 981;// <1=> Active HIGH chip select 982;// <o0.3> PM: Page mode enable 983;// <o0.0..1> MW: Memory width 984;// <0=> 8 bit 985;// <1=> 16 bit 986;// <2=> 32 bit 987;// </h> 988EMC_STA_CFG3_Val EQU 0x00000000 989 990;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen3) 991;// <i> Selects the delay from CS3 to write enable 992;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1> 993;// <i> The delay is in CCLK cycles 994;// </h> 995EMC_STA_WWEN3_Val EQU 0x00000000 996 997;// <h> Static Memory Output Enable Delay register (EMCStaticWaitOen3) 998;// <i> Selects the delay from CS3 or address change, whichever is later, to output enable 999;// <o.0..3> WAITOEN: Wait output enable <0-15> 1000;// <i> The delay is in CCLK cycles 1001;// </h> 1002EMC_STA_WOEN3_Val EQU 0x00000000 1003 1004;// <h> Static Memory Read Delay Register (EMCStaticWaitRd3) 1005;// <i> Selects the delay from CS3 to a read access 1006;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1> 1007;// <i> The delay is in CCLK cycles 1008;// </h> 1009EMC_STA_WRD3_Val EQU 0x0000001F 1010 1011;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage3) 1012;// <i> Selects the delay for asynchronous page mode sequential accesses for CS3 1013;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1> 1014;// <i> The delay is in CCLK cycles 1015;// </h> 1016EMC_STA_WPAGE3_Val EQU 0x0000001F 1017 1018;// <h> Static Memory Write Delay Register (EMCStaticWaitWr3) 1019;// <i> Selects the delay from CS3 to a write access 1020;// <o.0..4> WAITWR: Write wait states <2-33> <#-2> 1021;// <i> The delay is in CCLK cycles 1022;// </h> 1023EMC_STA_WWR3_Val EQU 0x0000001F 1024 1025;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn3) 1026;// <i> Selects the number of bus turnaround cycles for CS3 1027;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1> 1028;// <i> The delay is in CCLK cycles 1029;// </h> 1030EMC_STA_WTURN3_Val EQU 0x0000000F 1031 1032;// </e> End of Static Setup for Static CS3 Area 1033 1034;// <h> Static Memory Extended Wait Register (EMCStaticExtendedWait) 1035;// <i> Time long static memory read and write transfers 1036;// <o.0..9> EXTENDEDWAIT: Extended wait time out <0-1023> 1037;// <i> The delay is in (16 * CCLK) cycles 1038;// </h> 1039EMC_STA_EXT_W_Val EQU 0x00000000 1040 1041;// </e> End of Static Setup 1042 1043;// </e> End of EMC Setup 1044 1045 1046 PRESERVE8 1047 1048; Area Definition and Entry Point 1049; Startup Code must be linked first at Address at which it expects to run. 1050 1051 AREA RESET, CODE, READONLY 1052 ARM 1053 1054 1055; Exception Vectors 1056; Mapped to Address 0. 1057; Absolute addressing mode must be used. 1058; Dummy Handlers are implemented as infinite loops which can be modified. 1059 1060Vectors LDR PC, Reset_Addr 1061 LDR PC, Undef_Addr 1062 LDR PC, SWI_Addr 1063 LDR PC, PAbt_Addr 1064 LDR PC, DAbt_Addr 1065 NOP ; Reserved Vector 1066 LDR PC, IRQ_Addr 1067 LDR PC, FIQ_Addr 1068 1069Reset_Addr DCD Reset_Handler 1070Undef_Addr DCD Undef_Handler 1071SWI_Addr DCD SWI_Handler 1072PAbt_Addr DCD PAbt_Handler 1073DAbt_Addr DCD DAbt_Handler 1074 DCD 0 ; Reserved Address 1075IRQ_Addr DCD IRQ_Handler 1076FIQ_Addr DCD FIQ_Handler 1077 1078 1079; Exception Handler 1080 IMPORT rt_hw_trap_udef 1081 IMPORT rt_hw_trap_swi 1082 IMPORT rt_hw_trap_pabt 1083 IMPORT rt_hw_trap_dabt 1084 IMPORT rt_hw_trap_fiq 1085 1086; Prepare Fatal Context 1087 MACRO 1088 prepare_fatal 1089 STMFD sp!, {r0-r3} 1090 MOV r1, sp 1091 ADD sp, sp, #16 1092 SUB r2, lr, #4 1093 MRS r3, spsr 1094 1095 ; switch to SVC mode and no interrupt 1096 MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC 1097 1098 STMFD sp!, {r0} ; old r0 1099 ; get sp 1100 ADD r0, sp, #4 1101 STMFD sp!, {r3} ; cpsr 1102 STMFD sp!, {r2} ; pc 1103 STMFD sp!, {lr} ; lr 1104 STMFD sp!, {r0} ; sp 1105 STMFD sp!, {r4-r12} 1106 1107 MOV r4, r1 1108 1109 LDMFD r4!, {r0-r3} 1110 STMFD sp!, {r0-r3} 1111 1112 MOV r0, sp 1113 MEND 1114 1115Undef_Handler 1116 prepare_fatal 1117 BL rt_hw_trap_irq 1118 B . 1119 1120SWI_Handler 1121 prepare_fatal 1122 BL rt_hw_trap_swi 1123 B . 1124 1125PAbt_Handler 1126 prepare_fatal 1127 BL rt_hw_trap_pabt 1128 B . 1129 1130DAbt_Handler 1131 prepare_fatal 1132 BL rt_hw_trap_dabt 1133 B . 1134 1135FIQ_Handler 1136 prepare_fatal 1137 BL rt_hw_trap_fiq 1138 B . 1139 1140; Reset Handler 1141 1142 EXPORT Reset_Handler 1143Reset_Handler 1144 1145 1146; Clock Setup ------------------------------------------------------------------ 1147 1148 IF (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0) 1149 LDR R0, =SCB_BASE 1150 MOV R1, #0xAA 1151 MOV R2, #0x55 1152 1153; Configure and Enable PLL 1154 LDR R3, =SCS_Val ; Enable main oscillator 1155 STR R3, [R0, #SCS_OFS] 1156 1157 IF (SCS_Val:AND:OSCEN) != 0 1158OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabilize 1159 ANDS R3, R3, #OSCSTAT 1160 BEQ OSC_Loop 1161 ENDIF 1162 1163 LDR R3, =CLKSRCSEL_Val ; Select PLL source clock 1164 STR R3, [R0, #CLKSRCSEL_OFS] 1165 LDR R3, =PLLCFG_Val 1166 STR R3, [R0, #PLLCFG_OFS] 1167 STR R1, [R0, #PLLFEED_OFS] 1168 STR R2, [R0, #PLLFEED_OFS] 1169 MOV R3, #PLLCON_PLLE 1170 STR R3, [R0, #PLLCON_OFS] 1171 STR R1, [R0, #PLLFEED_OFS] 1172 STR R2, [R0, #PLLFEED_OFS] 1173 1174 IF (CLKSRCSEL_Val:AND:3) != 2 1175; Wait until PLL Locked (if source is not RTC oscillator) 1176PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] 1177 ANDS R3, R3, #PLLSTAT_PLOCK 1178 BEQ PLL_Loop 1179 ELSE 1180; Wait at least 200 cycles (if source is RTC oscillator) 1181 MOV R3, #(200/4) 1182PLL_Loop SUBS R3, R3, #1 1183 BNE PLL_Loop 1184 ENDIF 1185 1186M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] 1187 LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) 1188 AND R3, R3, R4 1189 LDR R4, =PLLCFG_Val 1190 EORS R3, R3, R4 1191 BNE M_N_Lock 1192 1193; Setup CPU clock divider 1194 MOV R3, #CCLKCFG_Val 1195 STR R3, [R0, #CCLKCFG_OFS] 1196 1197; Setup USB clock divider 1198 LDR R3, =USBCLKCFG_Val 1199 STR R3, [R0, #USBCLKCFG_OFS] 1200 1201; Setup Peripheral Clock 1202 LDR R3, =PCLKSEL0_Val 1203 STR R3, [R0, #PCLKSEL0_OFS] 1204 LDR R3, =PCLKSEL1_Val 1205 STR R3, [R0, #PCLKSEL1_OFS] 1206 1207; Switch to PLL Clock 1208 MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) 1209 STR R3, [R0, #PLLCON_OFS] 1210 STR R1, [R0, #PLLFEED_OFS] 1211 STR R2, [R0, #PLLFEED_OFS] 1212 ENDIF ; CLOCK_SETUP 1213 1214 1215; Setup Memory Accelerator Module ---------------------------------------------- 1216 1217 IF MAM_SETUP != 0 1218 LDR R0, =MAM_BASE 1219 MOV R1, #MAMTIM_Val 1220 STR R1, [R0, #MAMTIM_OFS] 1221 MOV R1, #MAMCR_Val 1222 STR R1, [R0, #MAMCR_OFS] 1223 ENDIF ; MAM_SETUP 1224 1225 1226; Setup External Memory Controller --------------------------------------------- 1227 1228 IF (:LNOT:(:DEF:NO_EMC_SETUP)):LAND:(EMC_SETUP != 0) 1229 LDR R0, =EMC_BASE 1230 LDR R1, =SCB_BASE 1231 LDR R2, =PCB_BASE 1232 1233 LDR R4, =EMC_PCONP_Const ; Enable EMC 1234 LDR R3, [R1, #PCONP_OFS] 1235 ORR R4, R4, R3 1236 STR R4, [R1, #PCONP_OFS] 1237 1238 LDR R4, =EMC_CTRL_Val 1239 STR R4, [R0, #EMC_CTRL_OFS] 1240 LDR R4, =EMC_CONFIG_Val 1241 STR R4, [R0, #EMC_CONFIG_OFS] 1242 1243; Setup pin functions for External Bus functionality 1244 LDR R4, =EMC_PINSEL5_Val 1245 STR R4, [R2, #PINSEL5_OFS] 1246 LDR R4, =EMC_PINSEL6_Val 1247 STR R4, [R2, #PINSEL6_OFS] 1248 LDR R4, =EMC_PINSEL8_Val 1249 STR R4, [R2, #PINSEL8_OFS] 1250 LDR R4, =EMC_PINSEL9_Val 1251 STR R4, [R2, #PINSEL9_OFS] 1252 1253; Setup Dynamic Memory Interface 1254 IF (EMC_DYNAMIC_SETUP != 0) 1255 1256 LDR R4, =EMC_DYN_RP_Val 1257 STR R4, [R0, #EMC_DYN_RP_OFS] 1258 LDR R4, =EMC_DYN_RAS_Val 1259 STR R4, [R0, #EMC_DYN_RAS_OFS] 1260 LDR R4, =EMC_DYN_SREX_Val 1261 STR R4, [R0, #EMC_DYN_SREX_OFS] 1262 LDR R4, =EMC_DYN_APR_Val 1263 STR R4, [R0, #EMC_DYN_APR_OFS] 1264 LDR R4, =EMC_DYN_DAL_Val 1265 STR R4, [R0, #EMC_DYN_DAL_OFS] 1266 LDR R4, =EMC_DYN_WR_Val 1267 STR R4, [R0, #EMC_DYN_WR_OFS] 1268 LDR R4, =EMC_DYN_RC_Val 1269 STR R4, [R0, #EMC_DYN_RC_OFS] 1270 LDR R4, =EMC_DYN_RFC_Val 1271 STR R4, [R0, #EMC_DYN_RFC_OFS] 1272 LDR R4, =EMC_DYN_XSR_Val 1273 STR R4, [R0, #EMC_DYN_XSR_OFS] 1274 LDR R4, =EMC_DYN_RRD_Val 1275 STR R4, [R0, #EMC_DYN_RRD_OFS] 1276 LDR R4, =EMC_DYN_MRD_Val 1277 STR R4, [R0, #EMC_DYN_MRD_OFS] 1278 1279 LDR R4, =EMC_DYN_RD_CFG_Val 1280 STR R4, [R0, #EMC_DYN_RD_CFG_OFS] 1281 1282 IF (EMC_DYNCS0_SETUP != 0) 1283 LDR R4, =EMC_DYN_RASCAS0_Val 1284 STR R4, [R0, #EMC_DYN_RASCAS0_OFS] 1285 LDR R4, =EMC_DYN_CFG0_Val 1286 MVN R5, #BUFEN_Const 1287 AND R4, R4, R5 1288 STR R4, [R0, #EMC_DYN_CFG0_OFS] 1289 ENDIF 1290 IF (EMC_DYNCS1_SETUP != 0) 1291 LDR R4, =EMC_DYN_RASCAS1_Val 1292 STR R4, [R0, #EMC_DYN_RASCAS1_OFS] 1293 LDR R4, =EMC_DYN_CFG1_Val 1294 MVN R5, =BUFEN_Const 1295 AND R4, R4, R5 1296 STR R4, [R0, #EMC_DYN_CFG1_OFS] 1297 ENDIF 1298 IF (EMC_DYNCS2_SETUP != 0) 1299 LDR R4, =EMC_DYN_RASCAS2_Val 1300 STR R4, [R0, #EMC_DYN_RASCAS2_OFS] 1301 LDR R4, =EMC_DYN_CFG2_Val 1302 MVN R5, =BUFEN_Const 1303 AND R4, R4, R5 1304 STR R4, [R0, #EMC_DYN_CFG2_OFS] 1305 ENDIF 1306 IF (EMC_DYNCS3_SETUP != 0) 1307 LDR R4, =EMC_DYN_RASCAS3_Val 1308 STR R4, [R0, #EMC_DYN_RASCAS3_OFS] 1309 LDR R4, =EMC_DYN_CFG3_Val 1310 MVN R5, =BUFEN_Const 1311 AND R4, R4, R5 1312 STR R4, [R0, #EMC_DYN_CFG3_OFS] 1313 ENDIF 1314 1315 LDR R6, =1440000 ; Number of cycles to delay 1316Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz 1317 BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc 1318 1319 LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command 1320 STR R4, [R0, #EMC_DYN_CTRL_OFS] 1321 1322 LDR R6, =2880000 ; Number of cycles to delay 1323Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz 1324 BNE Wait_1 1325 1326 LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command 1327 STR R4, [R0, #EMC_DYN_CTRL_OFS] 1328 1329 MOV R4, #2 1330 STR R4, [R0, #EMC_DYN_RFSH_OFS] 1331 1332 MOV R6, #64 ; Number of cycles to delay 1333Wait_2 SUBS R6, R6, #1 ; Delay 1334 BNE Wait_2 1335 1336 LDR R4, =EMC_DYN_RFSH_Val 1337 STR R4, [R0, #EMC_DYN_RFSH_OFS] 1338 1339 LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command 1340 STR R4, [R0, #EMC_DYN_CTRL_OFS] 1341 1342 ; Dummy read 1343 IF (EMC_DYNCS0_SETUP != 0) 1344 LDR R4, =DYN_MEM0_BASE 1345 MOV R5, #(0x33 << 12) 1346 ADD R4, R4, R5 1347 LDR R4, [R4, #0] 1348 ENDIF 1349 IF (EMC_DYNCS1_SETUP != 0) 1350 LDR R4, =DYN_MEM1_BASE 1351 MOV R5, #(0x33 << 12) 1352 ADD R4, R4, R5 1353 LDR R4, [R4, #0] 1354 ENDIF 1355 IF (EMC_DYNCS2_SETUP != 0) 1356 LDR R4, =DYN_MEM2_BASE 1357 MOV R5, #(0x33 << 12) 1358 ADD R4, R4, R5 1359 LDR R4, [R4, #0] 1360 ENDIF 1361 IF (EMC_DYNCS3_SETUP != 0) 1362 LDR R4, =DYN_MEM3_BASE 1363 MOV R5, #(0x33 << 12) 1364 ADD R4, R4, R5 1365 LDR R4, [R4, #0] 1366 ENDIF 1367 1368 LDR R4, =NORMAL_CMD ; Write NORMAL Command 1369 STR R4, [R0, #EMC_DYN_CTRL_OFS] 1370 1371 ; Enable buffer if requested by settings 1372 IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0) 1373 LDR R4, =EMC_DYN_CFG0_Val 1374 STR R4, [R0, #EMC_DYN_CFG0_OFS] 1375 ENDIF 1376 IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0) 1377 LDR R4, =EMC_DYN_CFG1_Val 1378 STR R4, [R0, #EMC_DYN_CFG1_OFS] 1379 ENDIF 1380 IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0) 1381 LDR R4, =EMC_DYN_CFG2_Val 1382 STR R4, [R0, #EMC_DYN_CFG2_OFS] 1383 ENDIF 1384 IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0) 1385 LDR R4, =EMC_DYN_CFG3_Val 1386 STR R4, [R0, #EMC_DYN_CFG3_OFS] 1387 ENDIF 1388 1389 LDR R6, =14400 ; Number of cycles to delay 1390Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz 1391 BNE Wait_3 1392 1393 ENDIF ; EMC_DYNAMIC_SETUP 1394 1395; Setup Static Memory Interface 1396 IF (EMC_STATIC_SETUP != 0) 1397 1398 LDR R6, =1440000 ; Number of cycles to delay 1399Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz 1400 BNE Wait_4 1401 1402 IF (EMC_STACS0_SETUP != 0) 1403 LDR R4, =EMC_STA_CFG0_Val 1404 STR R4, [R0, #EMC_STA_CFG0_OFS] 1405 LDR R4, =EMC_STA_WWEN0_Val 1406 STR R4, [R0, #EMC_STA_WWEN0_OFS] 1407 LDR R4, =EMC_STA_WOEN0_Val 1408 STR R4, [R0, #EMC_STA_WOEN0_OFS] 1409 LDR R4, =EMC_STA_WRD0_Val 1410 STR R4, [R0, #EMC_STA_WRD0_OFS] 1411 LDR R4, =EMC_STA_WPAGE0_Val 1412 STR R4, [R0, #EMC_STA_WPAGE0_OFS] 1413 LDR R4, =EMC_STA_WWR0_Val 1414 STR R4, [R0, #EMC_STA_WWR0_OFS] 1415 LDR R4, =EMC_STA_WTURN0_Val 1416 STR R4, [R0, #EMC_STA_WTURN0_OFS] 1417 ENDIF 1418 1419 IF (EMC_STACS1_SETUP != 0) 1420 LDR R4, =EMC_STA_CFG1_Val 1421 STR R4, [R0, #EMC_STA_CFG1_OFS] 1422 LDR R4, =EMC_STA_WWEN1_Val 1423 STR R4, [R0, #EMC_STA_WWEN1_OFS] 1424 LDR R4, =EMC_STA_WOEN1_Val 1425 STR R4, [R0, #EMC_STA_WOEN1_OFS] 1426 LDR R4, =EMC_STA_WRD1_Val 1427 STR R4, [R0, #EMC_STA_WRD1_OFS] 1428 LDR R4, =EMC_STA_WPAGE1_Val 1429 STR R4, [R0, #EMC_STA_WPAGE1_OFS] 1430 LDR R4, =EMC_STA_WWR1_Val 1431 STR R4, [R0, #EMC_STA_WWR1_OFS] 1432 LDR R4, =EMC_STA_WTURN1_Val 1433 STR R4, [R0, #EMC_STA_WTURN1_OFS] 1434 ENDIF 1435 1436 IF (EMC_STACS2_SETUP != 0) 1437 LDR R4, =EMC_STA_CFG2_Val 1438 STR R4, [R0, #EMC_STA_CFG2_OFS] 1439 LDR R4, =EMC_STA_WWEN2_Val 1440 STR R4, [R0, #EMC_STA_WWEN2_OFS] 1441 LDR R4, =EMC_STA_WOEN2_Val 1442 STR R4, [R0, #EMC_STA_WOEN2_OFS] 1443 LDR R4, =EMC_STA_WRD2_Val 1444 STR R4, [R0, #EMC_STA_WRD2_OFS] 1445 LDR R4, =EMC_STA_WPAGE2_Val 1446 STR R4, [R0, #EMC_STA_WPAGE2_OFS] 1447 LDR R4, =EMC_STA_WWR2_Val 1448 STR R4, [R0, #EMC_STA_WWR2_OFS] 1449 LDR R4, =EMC_STA_WTURN2_Val 1450 STR R4, [R0, #EMC_STA_WTURN2_OFS] 1451 ENDIF 1452 1453 IF (EMC_STACS3_SETUP != 0) 1454 LDR R4, =EMC_STA_CFG3_Val 1455 STR R4, [R0, #EMC_STA_CFG3_OFS] 1456 LDR R4, =EMC_STA_WWEN3_Val 1457 STR R4, [R0, #EMC_STA_WWEN3_OFS] 1458 LDR R4, =EMC_STA_WOEN3_Val 1459 STR R4, [R0, #EMC_STA_WOEN3_OFS] 1460 LDR R4, =EMC_STA_WRD3_Val 1461 STR R4, [R0, #EMC_STA_WRD3_OFS] 1462 LDR R4, =EMC_STA_WPAGE3_Val 1463 STR R4, [R0, #EMC_STA_WPAGE3_OFS] 1464 LDR R4, =EMC_STA_WWR3_Val 1465 STR R4, [R0, #EMC_STA_WWR3_OFS] 1466 LDR R4, =EMC_STA_WTURN3_Val 1467 STR R4, [R0, #EMC_STA_WTURN3_OFS] 1468 ENDIF 1469 1470 LDR R6, =144000 ; Number of cycles to delay 1471Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz 1472 BNE Wait_5 1473 1474 LDR R4, =EMC_STA_EXT_W_Val 1475 LDR R5, =EMC_STA_EXT_W_OFS 1476 ADD R5, R5, R0 1477 STR R4, [R5, #0] 1478 1479 ENDIF ; EMC_STATIC_SETUP 1480 1481 ENDIF ; EMC_SETUP 1482 1483 1484; Copy Exception Vectors to Internal RAM --------------------------------------- 1485 1486 IF :DEF:RAM_INTVEC 1487 ADR R8, Vectors ; Source 1488 LDR R9, =RAM_BASE ; Destination 1489 LDMIA R8!, {R0-R7} ; Load Vectors 1490 STMIA R9!, {R0-R7} ; Store Vectors 1491 LDMIA R8!, {R0-R7} ; Load Handler Addresses 1492 STMIA R9!, {R0-R7} ; Store Handler Addresses 1493 ENDIF 1494 1495 1496; Memory Mapping (when Interrupt Vectors are in RAM) --------------------------- 1497 1498MEMMAP EQU 0xE01FC040 ; Memory Mapping Control 1499 IF :DEF:REMAP 1500 LDR R0, =MEMMAP 1501 IF :DEF:EXTMEM_MODE 1502 MOV R1, #3 1503 ELIF :DEF:RAM_MODE 1504 MOV R1, #2 1505 ELSE 1506 MOV R1, #1 1507 ENDIF 1508 STR R1, [R0] 1509 ENDIF 1510 1511 1512; Setup Stack for each mode ---------------------------------------------------- 1513 1514 LDR R0, =Stack_Top 1515 1516; Enter Undefined Instruction Mode and set its Stack Pointer 1517 MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit 1518 MOV SP, R0 1519 SUB R0, R0, #UND_Stack_Size 1520 1521; Enter Abort Mode and set its Stack Pointer 1522 MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 1523 MOV SP, R0 1524 SUB R0, R0, #ABT_Stack_Size 1525 1526; Enter FIQ Mode and set its Stack Pointer 1527 MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit 1528 MOV SP, R0 1529 SUB R0, R0, #FIQ_Stack_Size 1530 1531; Enter IRQ Mode and set its Stack Pointer 1532 MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit 1533 MOV SP, R0 1534 SUB R0, R0, #IRQ_Stack_Size 1535 1536; Enter Supervisor Mode and set its Stack Pointer 1537 MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit 1538 MOV SP, R0 1539 SUB R0, R0, #SVC_Stack_Size 1540 1541 IF :DEF:__MICROLIB 1542 EXPORT __initial_sp 1543 ELSE 1544 ENDIF 1545 1546; Enter the C code ------------------------------------------------------------- 1547 1548 IMPORT __main 1549 LDR R0, =__main 1550 BX R0 1551 1552 IMPORT rt_interrupt_enter 1553 IMPORT rt_interrupt_leave 1554 IMPORT rt_thread_switch_interrupt_flag 1555 IMPORT rt_interrupt_from_thread 1556 IMPORT rt_interrupt_to_thread 1557 IMPORT rt_hw_trap_irq 1558 1559IRQ_Handler PROC 1560 EXPORT IRQ_Handler 1561 STMFD sp!, {r0-r12,lr} 1562 BL rt_interrupt_enter 1563 BL rt_hw_trap_irq 1564 BL rt_interrupt_leave 1565 1566 ; if rt_thread_switch_interrupt_flag set, jump to 1567 ; rt_hw_context_switch_interrupt_do and don't return 1568 LDR r0, =rt_thread_switch_interrupt_flag 1569 LDR r1, [r0] 1570 CMP r1, #1 1571 BEQ rt_hw_context_switch_interrupt_do 1572 1573 LDMFD sp!, {r0-r12,lr} 1574 SUBS pc, lr, #4 1575 ENDP 1576 1577; /* 1578; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) 1579; */ 1580rt_hw_context_switch_interrupt_do PROC 1581 EXPORT rt_hw_context_switch_interrupt_do 1582 MOV r1, #0 ; clear flag 1583 STR r1, [r0] 1584 1585 LDMFD sp!, {r0-r12,lr}; reload saved registers 1586 STMFD sp!, {r0-r3} ; save r0-r3 1587 MOV r1, sp 1588 ADD sp, sp, #16 ; restore sp 1589 SUB r2, lr, #4 ; save old task's pc to r2 1590 1591 MRS r3, spsr ; get cpsr of interrupt thread 1592 1593 ; switch to SVC mode and no interrupt 1594 MSR cpsr_c, #I_Bit :OR: F_Bit :OR: Mode_SVC 1595 1596 STMFD sp!, {r2} ; push old task's pc 1597 STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 1598 MOV r4, r1 ; Special optimised code below 1599 MOV r5, r3 1600 LDMFD r4!, {r0-r3} 1601 STMFD sp!, {r0-r3} ; push old task's r3-r0 1602 STMFD sp!, {r5} ; push old task's cpsr 1603 1604 LDR r4, =rt_interrupt_from_thread 1605 LDR r5, [r4] 1606 STR sp, [r5] ; store sp in preempted tasks's TCB 1607 1608 LDR r6, =rt_interrupt_to_thread 1609 LDR r6, [r6] 1610 LDR sp, [r6] ; get new task's stack pointer 1611 1612 LDMFD sp!, {r4} ; pop new task's cpsr to spsr 1613 MSR spsr_cxsf, r4 1614 BIC r4, r4, #0x20 ; must be ARM mode 1615 MSR cpsr_cxsf, r4 1616 1617 LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr 1618 ENDP 1619 1620 IF :DEF:__MICROLIB 1621 1622 EXPORT __heap_base 1623 EXPORT __heap_limit 1624 1625 ELSE 1626; User Initial Stack & Heap 1627 AREA |.text|, CODE, READONLY 1628 1629 IMPORT __use_two_region_memory 1630 EXPORT __user_initial_stackheap 1631__user_initial_stackheap 1632 1633 LDR R0, = Heap_Mem 1634 LDR R1, =(Stack_Mem + USR_Stack_Size) 1635 LDR R2, = (Heap_Mem + Heap_Size) 1636 LDR R3, = Stack_Mem 1637 BX LR 1638 ENDIF 1639 1640 1641 END 1642