1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2008-12-11 xuxinming first version 9 */ 10 11 #ifndef __LPC24xx_H 12 #define __LPC24xx_H 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define USERMODE 0x10 19 #define FIQMODE 0x11 20 #define IRQMODE 0x12 21 #define SVCMODE 0x13 22 #define ABORTMODE 0x17 23 #define UNDEFMODE 0x1b 24 #define MODEMASK 0x1f 25 #define NOINT 0xc0 26 27 #define MCLK (72000000) 28 29 /* Vectored Interrupt Controller (VIC) */ 30 #define VIC_BASE_ADDR 0xFFFFF000 31 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) 32 #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) 33 #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) 34 #define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) 35 #define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) 36 #define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) 37 #define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) 38 #define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) 39 #define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) 40 #define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) 41 42 #define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) 43 #define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) 44 #define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) 45 #define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) 46 #define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) 47 #define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) 48 #define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) 49 #define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) 50 #define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) 51 #define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) 52 #define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) 53 #define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) 54 #define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) 55 #define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) 56 #define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) 57 #define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) 58 #define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) 59 #define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) 60 #define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) 61 #define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) 62 #define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) 63 #define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) 64 #define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) 65 #define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) 66 #define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) 67 #define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) 68 #define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) 69 #define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) 70 #define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) 71 #define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) 72 #define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) 73 #define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) 74 75 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, 76 these registers are known as "VICVectPriority(x)". */ 77 #define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) 78 #define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) 79 #define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) 80 #define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) 81 #define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) 82 #define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) 83 #define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) 84 #define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) 85 #define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) 86 #define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) 87 #define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) 88 #define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) 89 #define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) 90 #define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) 91 #define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) 92 #define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) 93 #define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) 94 #define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) 95 #define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) 96 #define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) 97 #define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) 98 #define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) 99 #define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) 100 #define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) 101 #define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) 102 #define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) 103 #define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) 104 #define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) 105 #define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) 106 #define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) 107 #define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) 108 #define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) 109 110 #define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) 111 112 113 /* Pin Connect Block */ 114 #define PINSEL_BASE_ADDR 0xE002C000 115 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) 116 #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) 117 #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) 118 #define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) 119 #define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) 120 #define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) 121 #define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) 122 #define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) 123 #define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) 124 #define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) 125 #define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) 126 #define PINSEL11 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x2C)) 127 128 #define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) 129 #define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) 130 #define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) 131 #define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) 132 #define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) 133 #define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) 134 #define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) 135 #define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) 136 #define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) 137 #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) 138 139 /* General Purpose Input/Output (GPIO) */ 140 #define GPIO_BASE_ADDR 0xE0028000 141 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) 142 #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) 143 #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) 144 #define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) 145 #define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) 146 #define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) 147 #define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) 148 #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) 149 150 /* GPIO Interrupt Registers */ 151 #define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) 152 #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) 153 #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) 154 #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) 155 #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) 156 157 #define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) 158 #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) 159 #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) 160 #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) 161 #define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) 162 163 #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) 164 165 #define PARTCFG_BASE_ADDR 0x3FFF8000 166 #define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) 167 168 /* Fast I/O setup */ 169 #define FIO_BASE_ADDR 0x3FFFC000 170 #define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) 171 #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) 172 #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) 173 #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) 174 #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) 175 176 #define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) 177 #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) 178 #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) 179 #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) 180 #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) 181 182 #define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) 183 #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) 184 #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) 185 #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) 186 #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) 187 188 #define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) 189 #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) 190 #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) 191 #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) 192 #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) 193 194 #define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) 195 #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) 196 #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) 197 #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) 198 #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) 199 200 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ 201 #define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) 202 #define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) 203 #define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) 204 #define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) 205 #define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) 206 207 #define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) 208 #define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) 209 #define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) 210 #define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) 211 #define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) 212 213 #define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) 214 #define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) 215 #define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) 216 #define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) 217 #define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) 218 219 #define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) 220 #define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) 221 #define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) 222 #define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) 223 #define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) 224 225 #define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) 226 #define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) 227 #define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) 228 #define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) 229 #define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) 230 231 #define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) 232 #define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) 233 #define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) 234 #define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) 235 #define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) 236 237 #define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) 238 #define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) 239 #define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) 240 #define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) 241 #define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) 242 243 #define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) 244 #define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) 245 #define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) 246 #define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) 247 #define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) 248 249 #define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) 250 #define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) 251 #define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) 252 #define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) 253 #define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) 254 255 #define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) 256 #define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) 257 #define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) 258 #define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) 259 #define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) 260 261 #define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) 262 #define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) 263 #define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) 264 #define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) 265 #define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) 266 267 #define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) 268 #define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) 269 #define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) 270 #define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) 271 #define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) 272 273 #define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) 274 #define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) 275 #define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) 276 #define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) 277 #define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) 278 279 #define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) 280 #define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) 281 #define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) 282 #define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) 283 #define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) 284 285 #define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) 286 #define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) 287 #define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) 288 #define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) 289 #define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) 290 291 #define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) 292 #define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) 293 #define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) 294 #define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) 295 #define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) 296 297 #define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) 298 #define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) 299 #define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) 300 #define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) 301 #define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) 302 303 #define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) 304 #define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) 305 #define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) 306 #define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) 307 #define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) 308 309 #define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) 310 #define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) 311 #define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) 312 #define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) 313 #define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) 314 315 #define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) 316 #define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) 317 #define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) 318 #define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) 319 #define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) 320 321 #define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) 322 #define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) 323 #define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) 324 #define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) 325 #define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) 326 327 #define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) 328 #define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) 329 #define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) 330 #define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) 331 #define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) 332 333 #define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) 334 #define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) 335 #define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) 336 #define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) 337 #define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) 338 339 #define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) 340 #define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) 341 #define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) 342 #define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) 343 #define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) 344 345 #define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) 346 #define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) 347 #define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) 348 #define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) 349 #define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) 350 351 #define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) 352 #define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) 353 #define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) 354 #define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) 355 #define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) 356 357 #define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) 358 #define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) 359 #define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) 360 #define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) 361 #define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) 362 363 #define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) 364 #define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) 365 #define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) 366 #define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) 367 #define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) 368 369 #define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) 370 #define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) 371 #define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) 372 #define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) 373 #define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) 374 375 #define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) 376 #define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) 377 #define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) 378 #define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) 379 #define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) 380 381 382 /* System Control Block(SCB) modules include Memory Accelerator Module, 383 Phase Locked Loop, VPB divider, Power Control, External Interrupt, 384 Reset, and Code Security/Debugging */ 385 #define SCB_BASE_ADDR 0xE01FC000 386 387 /* Memory Accelerator Module (MAM) */ 388 #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) 389 #define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) 390 #define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) 391 392 /* Phase Locked Loop (PLL) */ 393 #define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) 394 #define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) 395 #define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) 396 #define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) 397 398 /* Power Control */ 399 #define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) 400 #define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) 401 402 /* Clock Divider */ 403 #define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) 404 #define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) 405 #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) 406 #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) 407 #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) 408 409 /* External Interrupts */ 410 #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) 411 #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) 412 #define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) 413 #define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) 414 415 /* Reset, reset source identification */ 416 #define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) 417 418 /* RSID, code security protection */ 419 #define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) 420 421 /* AHB configuration */ 422 #define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) 423 #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) 424 425 /* System Controls and Status */ 426 #define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) 427 428 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers 429 are for LPC24xx only. */ 430 #define STATIC_MEM0_BASE 0x80000000 431 #define STATIC_MEM1_BASE 0x81000000 432 #define STATIC_MEM2_BASE 0x82000000 433 #define STATIC_MEM3_BASE 0x83000000 434 435 #define DYNAMIC_MEM0_BASE 0xA0000000 436 #define DYNAMIC_MEM1_BASE 0xB0000000 437 #define DYNAMIC_MEM2_BASE 0xC0000000 438 #define DYNAMIC_MEM3_BASE 0xD0000000 439 440 /* External Memory Controller (EMC) */ 441 #define EMC_BASE_ADDR 0xFFE08000 442 #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) 443 #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) 444 #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) 445 446 /* Dynamic RAM access registers */ 447 #define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) 448 #define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) 449 #define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) 450 #define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) 451 #define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) 452 #define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) 453 #define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) 454 #define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) 455 #define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) 456 #define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) 457 #define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) 458 #define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) 459 #define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) 460 #define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) 461 462 #define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) 463 #define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) 464 #define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) 465 #define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) 466 #define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) 467 #define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) 468 #define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) 469 #define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) 470 471 /* static RAM access registers */ 472 #define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) 473 #define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) 474 #define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) 475 #define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) 476 #define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) 477 #define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) 478 #define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) 479 480 #define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) 481 #define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) 482 #define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) 483 #define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) 484 #define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) 485 #define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) 486 #define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) 487 488 #define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) 489 #define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) 490 #define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) 491 #define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) 492 #define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) 493 #define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) 494 #define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) 495 496 #define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) 497 #define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) 498 #define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) 499 #define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) 500 #define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) 501 #define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) 502 #define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) 503 504 #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) 505 506 507 /* Timer 0 */ 508 #define TMR0_BASE_ADDR 0xE0004000 509 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) 510 #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) 511 #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) 512 #define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) 513 #define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) 514 #define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) 515 #define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) 516 #define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) 517 #define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) 518 #define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) 519 #define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) 520 #define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) 521 #define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) 522 #define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) 523 #define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) 524 #define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) 525 #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) 526 527 /* Timer 1 */ 528 #define TMR1_BASE_ADDR 0xE0008000 529 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) 530 #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) 531 #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) 532 #define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) 533 #define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) 534 #define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) 535 #define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) 536 #define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) 537 #define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) 538 #define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) 539 #define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) 540 #define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) 541 #define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) 542 #define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) 543 #define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) 544 #define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) 545 #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) 546 547 /* Timer 2 */ 548 #define TMR2_BASE_ADDR 0xE0070000 549 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) 550 #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) 551 #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) 552 #define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) 553 #define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) 554 #define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) 555 #define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) 556 #define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) 557 #define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) 558 #define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) 559 #define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) 560 #define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) 561 #define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) 562 #define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) 563 #define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) 564 #define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) 565 #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) 566 567 /* Timer 3 */ 568 #define TMR3_BASE_ADDR 0xE0074000 569 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) 570 #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) 571 #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) 572 #define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) 573 #define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) 574 #define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) 575 #define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) 576 #define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) 577 #define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) 578 #define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) 579 #define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) 580 #define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) 581 #define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) 582 #define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) 583 #define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) 584 #define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) 585 #define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) 586 587 588 /* Pulse Width Modulator (PWM) */ 589 #define PWM0_BASE_ADDR 0xE0014000 590 #define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) 591 #define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) 592 #define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) 593 #define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) 594 #define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) 595 #define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) 596 #define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) 597 #define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) 598 #define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) 599 #define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) 600 #define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) 601 #define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) 602 #define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) 603 #define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) 604 #define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) 605 #define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) 606 #define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) 607 #define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) 608 #define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) 609 #define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) 610 #define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) 611 #define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) 612 613 #define PWM1_BASE_ADDR 0xE0018000 614 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) 615 #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) 616 #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) 617 #define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) 618 #define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) 619 #define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) 620 #define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) 621 #define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) 622 #define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) 623 #define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) 624 #define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) 625 #define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) 626 #define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) 627 #define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) 628 #define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) 629 #define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) 630 #define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) 631 #define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) 632 #define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) 633 #define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) 634 #define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) 635 #define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) 636 637 638 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ 639 #define UART0_BASE_ADDR 0xE000C000 640 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) 641 #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) 642 #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) 643 #define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) 644 #define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) 645 #define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) 646 #define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) 647 #define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) 648 #define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) 649 #define U0SCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x1C)) 650 #define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) 651 #define U0ICR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x24)) 652 #define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) 653 #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) 654 655 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ 656 #define UART1_BASE_ADDR 0xE0010000 657 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) 658 #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) 659 #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) 660 #define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) 661 #define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) 662 #define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) 663 #define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) 664 #define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) 665 #define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) 666 #define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) 667 #define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) 668 #define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) 669 #define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) 670 #define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) 671 #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) 672 673 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ 674 #define UART2_BASE_ADDR 0xE0078000 675 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) 676 #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) 677 #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) 678 #define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) 679 #define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) 680 #define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) 681 #define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) 682 #define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) 683 #define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) 684 #define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) 685 #define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) 686 #define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) 687 #define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) 688 #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) 689 690 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ 691 #define UART3_BASE_ADDR 0xE007C000 692 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) 693 #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) 694 #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) 695 #define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) 696 #define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) 697 #define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) 698 #define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) 699 #define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) 700 #define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) 701 #define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) 702 #define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) 703 #define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) 704 #define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) 705 #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) 706 707 /* I2C Interface 0 */ 708 #define I2C0_BASE_ADDR 0xE001C000 709 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) 710 #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) 711 #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) 712 #define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) 713 #define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) 714 #define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) 715 #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) 716 717 /* I2C Interface 1 */ 718 #define I2C1_BASE_ADDR 0xE005C000 719 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) 720 #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) 721 #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) 722 #define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) 723 #define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) 724 #define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) 725 #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) 726 727 /* I2C Interface 2 */ 728 #define I2C2_BASE_ADDR 0xE0080000 729 #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) 730 #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) 731 #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) 732 #define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) 733 #define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) 734 #define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) 735 #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) 736 737 /* SPI0 (Serial Peripheral Interface 0) */ 738 #define SPI0_BASE_ADDR 0xE0020000 739 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) 740 #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) 741 #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) 742 #define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) 743 #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) 744 745 /* SSP0 Controller */ 746 #define SSP0_BASE_ADDR 0xE0068000 747 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) 748 #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) 749 #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) 750 #define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) 751 #define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) 752 #define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) 753 #define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) 754 #define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) 755 #define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) 756 #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) 757 758 /* SSP1 Controller */ 759 #define SSP1_BASE_ADDR 0xE0030000 760 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) 761 #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) 762 #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) 763 #define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) 764 #define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) 765 #define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) 766 #define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) 767 #define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) 768 #define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) 769 #define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) 770 771 772 /* Real Time Clock */ 773 #define RTC_BASE_ADDR 0xE0024000 774 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) 775 #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) 776 #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) 777 #define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) 778 #define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) 779 #define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) 780 #define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) 781 #define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) 782 #define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) 783 #define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) 784 #define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) 785 #define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) 786 #define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) 787 #define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) 788 #define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) 789 #define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) 790 #define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) 791 #define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) 792 #define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) 793 #define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) 794 #define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) 795 #define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) 796 #define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) 797 #define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) 798 #define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) 799 #define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) 800 #define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) 801 802 803 /* A/D Converter 0 (AD0) */ 804 #define AD0_BASE_ADDR 0xE0034000 805 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) 806 #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) 807 #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) 808 #define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) 809 #define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) 810 #define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) 811 #define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) 812 #define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) 813 #define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) 814 #define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) 815 #define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) 816 #define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) 817 818 819 /* D/A Converter */ 820 #define DAC_BASE_ADDR 0xE006C000 821 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) 822 823 824 /* Watchdog */ 825 #define WDG_BASE_ADDR 0xE0000000 826 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) 827 #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) 828 #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) 829 #define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) 830 #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) 831 832 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ 833 #define CAN_ACCEPT_BASE_ADDR 0xE003C000 834 #define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) 835 #define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) 836 #define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) 837 #define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) 838 #define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) 839 #define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) 840 #define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) 841 #define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) 842 843 #define CAN_CENTRAL_BASE_ADDR 0xE0040000 844 #define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) 845 #define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) 846 #define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) 847 848 #define CAN1_BASE_ADDR 0xE0044000 849 #define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) 850 #define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) 851 #define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) 852 #define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) 853 #define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) 854 #define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) 855 #define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) 856 #define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) 857 #define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) 858 #define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) 859 #define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) 860 #define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) 861 862 #define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) 863 #define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) 864 #define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) 865 #define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) 866 #define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) 867 #define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) 868 #define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) 869 #define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) 870 #define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) 871 #define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) 872 #define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) 873 #define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) 874 875 #define CAN2_BASE_ADDR 0xE0048000 876 #define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) 877 #define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) 878 #define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) 879 #define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) 880 #define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) 881 #define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) 882 #define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) 883 #define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) 884 #define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) 885 #define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) 886 #define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) 887 #define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) 888 889 #define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) 890 #define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) 891 #define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) 892 #define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) 893 #define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) 894 #define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) 895 #define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) 896 #define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) 897 #define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) 898 #define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) 899 #define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) 900 #define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) 901 902 903 /* MultiMedia Card Interface(MCI) Controller */ 904 #define MCI_BASE_ADDR 0xE008C000 905 #define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) 906 #define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) 907 #define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) 908 #define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) 909 #define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) 910 #define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) 911 #define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) 912 #define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) 913 #define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) 914 #define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) 915 #define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) 916 #define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) 917 #define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) 918 #define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) 919 #define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) 920 #define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) 921 #define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) 922 #define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) 923 #define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) 924 925 926 /* I2S Interface Controller (I2S) */ 927 #define I2S_BASE_ADDR 0xE0088000 928 #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) 929 #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) 930 #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) 931 #define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) 932 #define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) 933 #define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) 934 #define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) 935 #define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) 936 #define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) 937 #define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) 938 939 940 /* General-purpose DMA Controller */ 941 #define DMA_BASE_ADDR 0xFFE04000 942 #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) 943 #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) 944 #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) 945 #define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) 946 #define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) 947 #define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) 948 #define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) 949 #define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) 950 #define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) 951 #define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) 952 #define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) 953 #define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) 954 #define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) 955 #define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) 956 957 /* DMA channel 0 registers */ 958 #define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) 959 #define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) 960 #define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) 961 #define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) 962 #define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) 963 964 /* DMA channel 1 registers */ 965 #define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) 966 #define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) 967 #define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) 968 #define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) 969 #define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) 970 971 972 /* USB Controller */ 973 #define USB_INT_BASE_ADDR 0xE01FC1C0 974 #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ 975 976 #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) 977 978 /* USB Device Interrupt Registers */ 979 #define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) 980 #define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) 981 #define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) 982 #define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) 983 #define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) 984 985 /* USB Device Endpoint Interrupt Registers */ 986 #define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) 987 #define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) 988 #define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) 989 #define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) 990 #define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) 991 992 /* USB Device Endpoint Realization Registers */ 993 #define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) 994 #define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) 995 #define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) 996 997 /* USB Device Command Reagisters */ 998 #define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) 999 #define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) 1000 1001 /* USB Device Data Transfer Registers */ 1002 #define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) 1003 #define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) 1004 #define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) 1005 #define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) 1006 #define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) 1007 1008 /* USB Device DMA Registers */ 1009 #define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) 1010 #define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) 1011 #define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) 1012 #define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) 1013 #define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) 1014 #define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) 1015 #define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) 1016 #define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) 1017 #define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) 1018 #define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) 1019 #define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) 1020 #define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) 1021 #define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) 1022 #define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) 1023 #define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) 1024 #define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) 1025 #define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) 1026 #define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) 1027 1028 /* USB Host and OTG registers are for LPC24xx only */ 1029 /* USB Host Controller */ 1030 #define USBHC_BASE_ADDR 0xFFE0C000 1031 #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) 1032 #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) 1033 #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) 1034 #define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) 1035 #define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) 1036 #define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) 1037 #define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) 1038 #define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) 1039 #define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) 1040 #define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) 1041 #define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) 1042 #define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) 1043 #define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) 1044 #define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) 1045 #define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) 1046 #define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) 1047 #define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) 1048 #define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) 1049 #define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) 1050 #define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) 1051 #define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) 1052 #define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) 1053 #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) 1054 1055 /* USB OTG Controller */ 1056 #define USBOTG_BASE_ADDR 0xFFE0C100 1057 #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) 1058 #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) 1059 #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) 1060 #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) 1061 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ 1062 #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) 1063 #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) 1064 1065 #define USBOTG_I2C_BASE_ADDR 0xFFE0C300 1066 #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) 1067 #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) 1068 #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) 1069 #define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) 1070 #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) 1071 #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) 1072 1073 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are 1074 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ 1075 #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 1076 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) 1077 #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) 1078 1079 /* Note: below three register name convention is for LPC23xx USB device only, match 1080 with the spec. update in USB Device Section. */ 1081 #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) 1082 #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) 1083 #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) 1084 1085 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ 1086 #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ 1087 #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ 1088 #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ 1089 #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ 1090 #define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ 1091 #define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ 1092 #define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ 1093 #define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ 1094 #define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ 1095 #define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ 1096 #define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ 1097 #define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ 1098 #define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ 1099 #define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ 1100 #define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ 1101 1102 #define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ 1103 #define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ 1104 #define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ 1105 1106 #define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ 1107 #define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ 1108 #define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ 1109 #define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ 1110 #define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ 1111 #define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ 1112 #define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ 1113 #define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ 1114 #define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ 1115 #define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ 1116 #define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ 1117 #define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ 1118 1119 #define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ 1120 #define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ 1121 #define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ 1122 1123 #define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ 1124 #define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ 1125 1126 #define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ 1127 #define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ 1128 #define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ 1129 1130 #define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ 1131 #define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ 1132 1133 #define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ 1134 #define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ 1135 #define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ 1136 #define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ 1137 1138 #define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ 1139 #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ 1140 1141 /* LCD Controller registers */ 1142 #define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ 1143 #define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) 1144 #define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) 1145 #define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) 1146 #define LCD_POL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x008)) 1147 #define LCD_LE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x00C)) 1148 #define LCD_UPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x010)) 1149 #define LCD_LPBASE (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x014)) 1150 #define LCD_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x018)) 1151 #define LCD_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x01C)) 1152 #define LCD_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x020)) 1153 #define LCD_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x024)) 1154 #define LCD_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x028)) 1155 #define LCD_UPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x02C)) 1156 #define LCD_LPCURR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x030)) 1157 #define LCD_PAL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x200)) 1158 #define CRSR_IMG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x800)) 1159 #define CRSR_CTRL (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC00)) 1160 #define CRSR_CFG (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC04)) 1161 #define CRSR_PAL0 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC08)) 1162 #define CRSR_PAL1 (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC0C)) 1163 #define CRSR_XY (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC10)) 1164 #define CRSR_CLIP (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC14)) 1165 #define CRSR_INTMSK (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC20)) 1166 #define CRSR_INTCLR (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC24)) 1167 #define CRSR_INTRAW (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC28)) 1168 #define CRSR_INTSTAT (*(volatile unsigned long *)(LCD_BASE_ADDR + 0xC2C)) 1169 1170 struct rt_hw_register 1171 { 1172 unsigned long r0; 1173 unsigned long r1; 1174 unsigned long r2; 1175 unsigned long r3; 1176 unsigned long r4; 1177 unsigned long r5; 1178 unsigned long r6; 1179 unsigned long r7; 1180 unsigned long r8; 1181 unsigned long r9; 1182 unsigned long r10; 1183 unsigned long fp; 1184 unsigned long ip; 1185 unsigned long sp; 1186 unsigned long lr; 1187 unsigned long pc; 1188 unsigned long cpsr; 1189 unsigned long ORIG_r0; 1190 }; 1191 1192 #ifdef __cplusplus 1193 } 1194 #endif 1195 1196 #endif // __LPC24xx_H 1197 1198